147 lines
3.3 KiB
C
147 lines
3.3 KiB
C
/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <platform.h>
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#include <platform/soc/chipid.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/soc/pmgr.h>
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bool chipid_get_current_production_mode(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_XTRCT(rCFG_FUSE0) != 0;
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}
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bool chipid_get_raw_production_mode(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_XTRCT(rCFG_FUSE0_RAW) != 0;
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}
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void chipid_clear_production_mode(void)
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{
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rCFG_FUSE0 &= ~MINIPMGR_FUSE_CFG_FUSE0_PRODUCTION_MODE_UMASK;
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}
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bool chipid_get_secure_mode(void)
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{
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// demotion only applies to the SEP, so iBoot always reads
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// the raw value for secure mode (<rdar://problem/15182573>)
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return MINIPMGR_FUSE_CFG_FUSE0_SECURE_MODE_XTRCT(rCFG_FUSE0_RAW);
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}
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uint32_t chipid_get_security_domain(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_SECURITY_DOMAIN_XTRCT(rCFG_FUSE0);
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}
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uint32_t chipid_get_board_id(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_BID_XTRCT(rCFG_FUSE0);
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}
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uint32_t chipid_get_minimum_epoch(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE0_MINIMUM_EPOCH_XTRCT(rCFG_FUSE0);
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}
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uint32_t chipid_get_chip_id(void)
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{
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return 0x8002;
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}
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uint32_t chipid_get_chip_revision(void)
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{
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uint32_t fuse_val = MINIPMGR_FUSE_CFG_FUSE4_DEV_VERSION_XTRCT(rCFG_FUSE4);
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// we use 4 bits for base layer and 4 bits for metal,
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// the fuses use 3 for each
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return (fuse_val & 0x7) | (((fuse_val >> 3) & 0x7) << 4);
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}
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uint32_t chipid_get_osc_frequency(void)
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{
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return OSC_FREQ;
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}
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uint64_t chipid_get_ecid_id(void)
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{
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return ((uint64_t)rECIDHI << 32) | rECIDLO;
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}
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uint64_t chipid_get_die_id(void)
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{
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return ((uint64_t)rECIDHI << 32) | rECIDLO;
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}
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uint32_t chipid_get_soc_voltage(uint32_t index)
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{
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uint32_t soc_voltage = 0;
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return soc_voltage;
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}
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uint32_t chipid_get_cpu_voltage(uint32_t index)
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{
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uint32_t cpu_voltage = 0;
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return cpu_voltage;
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}
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uint32_t chipid_get_ram_voltage(uint32_t index)
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{
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uint32_t sram_voltage = 0;
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return sram_voltage;
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}
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bool chipid_get_fuse_lock(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE1_AP_LOCK_XTRCT(rCFG_FUSE1) != 0;
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}
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void chipid_set_fuse_lock(bool locked)
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{
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if (locked) {
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rCFG_FUSE1 |= MINIPMGR_FUSE_CFG_FUSE1_AP_LOCK_INSRT(1);
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asm("dsb sy");
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if (!chipid_get_fuse_lock()) {
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panic("Failed to lock fuses\n");
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}
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}
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}
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bool chipid_get_fuse_seal(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE1_SEAL_FUSES_XTRCT(rCFG_FUSE1) != 0;
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}
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uint32_t chipid_get_fuse_revision(void)
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{
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return MINIPMGR_FUSE_CFG_FUSE4_REV_XTRCT(rCFG_FUSE4);
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}
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uint32_t chipid_get_total_rails_leakage()
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{
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uint32_t total_leakage;
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uint32_t leakage_data0;
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uint8_t leakage_data1;
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leakage_data0 = rCFG_FUSE5;
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leakage_data1 = (rCFG_FUSE4 >> 31) & 1;
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total_leakage = ((leakage_data0 >> 28) & 0xf) + 1; // soc_sram: cfg_fuse4[31:28]
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total_leakage += ((leakage_data0 >> 24) & 0xf) + 1; // cpu_sram: cfg_fuse4[27:24]
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total_leakage += ((leakage_data0 >> 16) & 0xff) + 1; // gpu: cfg_fuse4[23:16]
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total_leakage += ((leakage_data0 >> 8) & 0xff) + 1; // soc: cfg_fuse4[15:8]
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total_leakage += ((((leakage_data0 >> 0) & 0xff) << 1) | leakage_data1) + 1; // cpu: cfg_fuse4[7:0], cfg_fuse4[31]
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return total_leakage;
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}
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