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iBoot/target/alcatrazref/pinconfig.c

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/*
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#include <drivers/apple/gpio.h>
#include <platform/soc/hwregbase.h>
#include <stdint.h>
/* N51/N53 (iPhone6,x) Pin Configuration */
/*
* N51 pinlist v0.13
* <rdar://problem/11763484> N51 HW ERS | System | Pinlist
*/
#define CFG_DISABLED_SS_X4 (CFG_DISABLED | SLOW_SLEW | DRIVE_X4 )
#define CFG_DISABLED_SS_X4_PD (CFG_DISABLED | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
#define CFG_DISABLED_SS_X1_PD (CFG_DISABLED | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
#define CFG_DISABLED_SS_X4_PU (CFG_DISABLED | SLOW_SLEW | DRIVE_X4 | PULL_UP )
#define CFG_DISABLED_SS_X1_PU (CFG_DISABLED | SLOW_SLEW | DRIVE_X1 | PULL_UP )
#define CFG_IN_SS_X1 (CFG_IN | SLOW_SLEW | DRIVE_X1 )
#define CFG_IN_SS_X2 (CFG_IN | SLOW_SLEW | DRIVE_X2 )
#define CFG_IN_SS_X4 (CFG_IN | SLOW_SLEW | DRIVE_X4 )
#define CFG_IN_SS_X4_PD (CFG_IN | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
#define CFG_IN_SS_X1_PD (CFG_IN | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
#define CFG_IN_SS_X4_PU (CFG_IN | SLOW_SLEW | DRIVE_X4 | PULL_UP )
#define CFG_IN_SS_X1_PU (CFG_IN | SLOW_SLEW | DRIVE_X1 | PULL_UP )
#define CFG_OUT_0_SS_X4 (CFG_OUT_0 | SLOW_SLEW | DRIVE_X4 )
#define CFG_OUT_0_SS_X4_PD (CFG_OUT_0 | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
#define CFG_OUT_0_SS_X1_PD (CFG_OUT_0 | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
#define CFG_OUT_0_SS_X4_PU (CFG_OUT_0 | SLOW_SLEW | DRIVE_X4 | PULL_UP )
#define CFG_OUT_0_SS_X1_PU (CFG_OUT_0 | SLOW_SLEW | DRIVE_X1 | PULL_UP )
#define CFG_OUT_1_SS_X4 (CFG_OUT_1 | SLOW_SLEW | DRIVE_X4 )
#define CFG_OUT_1_SS_X4_PD (CFG_OUT_1 | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
#define CFG_OUT_1_SS_X1_PD (CFG_OUT_1 | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
#define CFG_OUT_1_SS_X4_PU (CFG_OUT_1 | SLOW_SLEW | DRIVE_X4 | PULL_UP )
#define CFG_OUT_1_SS_X1_PU (CFG_OUT_1 | SLOW_SLEW | DRIVE_X1 | PULL_UP )
#define CFG_FUNC0_SS_X1 (CFG_FUNC0 | SLOW_SLEW | DRIVE_X1 )
#define CFG_FUNC0_SS_X2 (CFG_FUNC0 | SLOW_SLEW | DRIVE_X2 )
#define CFG_FUNC0_SS_X4 (CFG_FUNC0 | SLOW_SLEW | DRIVE_X4 )
#define CFG_FUNC0_SS_X4_PD (CFG_FUNC0 | SLOW_SLEW | DRIVE_X4 | PULL_DOWN)
#define CFG_FUNC0_SS_X2_PD (CFG_FUNC0 | SLOW_SLEW | DRIVE_X2 | PULL_DOWN)
#define CFG_FUNC0_SS_X1_PD (CFG_FUNC0 | SLOW_SLEW | DRIVE_X1 | PULL_DOWN)
#define CFG_FUNC0_SS_X4_PU (CFG_FUNC0 | SLOW_SLEW | DRIVE_X4 | PULL_UP )
#define CFG_FUNC0_SS_X1_PU (CFG_FUNC0 | SLOW_SLEW | DRIVE_X1 | PULL_UP )
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_DISABLED_SS_X4_PD, // TST_CLKOUT -> AP_TO_PMU_TEST_CLKOUT
CFG_DISABLED_SS_X4_PD, // WDOG -> AP_TO_PMU_RESET_IN
CFG_IN_SS_X1, // GPIO0 -> BUTTON_TO_AP_MENU_KEY_BUFF_L
CFG_IN_SS_X1, // GPIO1 -> BUTTON_TO_AP_HOLD_KEY_BUFF_L
CFG_IN_SS_X1_PU, // GPIO2 -> BUTTON_TO_AP_VOL_UP_L
CFG_IN_SS_X1_PU, // GPIO3 -> BUTTON_TO_AP_VOL_DOWN_L
CFG_IN_SS_X1_PU, // GPIO4 -> PMU_NIRQ [PMU_TO_AP_IRQ_L in N51]
CFG_OUT_0_SS_X4_PD, // GPIO5 -> AP_TO_SPKAMP_BEE_GEES
/* Port 1 */
CFG_OUT_0_SS_X4_PD, // GPIO6 -> AP_TO_SPKAMP_RESET_L
CFG_OUT_0_SS_X4_PD, // GPIO7 -> AP_TO_BT_WAKE
CFG_IN_SS_X4, // GPIO8 -> AP_TO_BB_RST_L
CFG_DISABLED_SS_X4, // GPIO9 -> AP_TO_BB_JTAG_TDI
CFG_DISABLED_SS_X4_PD, // GPIO10 -> AP_TO_BB_JTAG_TDO
CFG_DISABLED_SS_X4_PD, // GPIO11 -> AP_TO_HEADSET_HS3_CTRL
CFG_DISABLED_SS_X4_PD, // GPIO12 -> AP_TO_HEADSET_HS4_CTRL
CFG_DISABLED, // GPIO13 -> NULL
/* Port 2 */
CFG_IN_SS_X1, // GPIO14 -> BUTTON_TO_AP_RINGER_A
CFG_OUT_0_SS_X4, // GPIO15 -> AP_TO_BB_WAKE_MODEM
CFG_DISABLED_SS_X1_PU, // GPIO16 -> N/C -> BOARD_ID[3]
CFG_IN_SS_X1, // GPIO17 -> AP_TO_OSCAR_DBGEN
CFG_DISABLED_SS_X1_PU, // GPIO18 -> BOARD_INFO -> BOOT_CONFIG[0]
CFG_DISABLED, // GPIO19 -> NULL
CFG_DISABLED, // GPIO20 -> NULL
CFG_DISABLED, // GPIO21 -> NULL
/* Port 3 */
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 4 */
CFG_FUNC0_SS_X4_PU, // UART1_TXD -> AP_TO_BT_UART1_TXD
CFG_FUNC0_SS_X1_PU, // UART1_RXD -> BT_TO_AP_UART1_RXD
CFG_FUNC0_SS_X4_PU, // UART1_RTSN -> AP_TO_BT_UART1_RTS_L
CFG_FUNC0_SS_X1_PU, // UART1_CTSN -> BT_TO_AP_UART1_CTS_L
CFG_FUNC0_SS_X4_PU, // UART2_TXD -> AP_TO_OSCAR_UART2_TXD
CFG_FUNC0_SS_X1_PU, // UART2_RXD -> OSCAR_TO_AP_UART2_RXD
CFG_OUT_1_SS_X4_PU, // UART2_RTSN -> AP_TO_OSCAR_RESET_L
CFG_IN_SS_X1_PD, // UART2_CTSN -> OSCAR_TO_PMU_HOST_WAKE
/* Port 5 */
CFG_FUNC0_SS_X4, // UART3_TXD -> AP_TO_WLAN_UART3_TXD
CFG_FUNC0_SS_X1, // UART3_RXD -> WLAN_TO_AP_UART3_RXD
CFG_DISABLED_SS_X1_PD, // UART3_RTSN -> BB_TO_AP_PP_SYNC
CFG_OUT_0_SS_X4_PD, // UART3_CTSN -> AP_TO_RCAM_VDDCORE_EN
CFG_FUNC0_SS_X2, // UART5_RXD -> AP_BI_BATTERY_SWI
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 6 */
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 7 */
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 8 */
CFG_OUT_0_SS_X4, // UART4_TXD -> AP_TO_BB_UART4_TXD
CFG_FUNC0_SS_X1, // UART4_RXD -> BB_TO_AP_UART4_RXD
CFG_OUT_0_SS_X4, // UART4_RTSN -> AP_TO_BB_UART4_RTS_L
CFG_FUNC0_SS_X1, // UART4_CTSN -> BB_TO_AP_UART4_CTS_L
CFG_FUNC0_SS_X4_PD, // SPI1_SCLK -> AP_TO_TOUCH_SPI1_CLK
CFG_FUNC0_SS_X4_PD, // SPI1_MOSI -> AP_TO_TOUCH_SPI1_MOSI
CFG_FUNC0_SS_X1_PD, // SPI1_MISO -> TOUCH_TO_AP_SPI1_MISO
CFG_FUNC0_SS_X4_PU, // SPI1_SSIN -> AP_TO_TOUCH_SPI1_CS_L
/* Port 9 */
CFG_DISABLED_SS_X1_PU, // SPI0_SCLK -> N/C -> SPI0_SCLK/BOARD_ID[0]
CFG_DISABLED_SS_X1_PU, // SPI0_MOSI -> N/C -> SPI0_MOSI/BOARD_ID[1]
CFG_DISABLED_SS_X1_PU, // SPI0_MISO -> N/C -> SPI0_MISO/BOARD_ID[2]
CFG_DISABLED_SS_X1_PD, // SPI0_SSIN -> LCM_TO_AP_PIFA
CFG_FUNC0_SS_X2, // SPI2_SCLK -> AP_TO_NAVAJO_SPI2_CLK
CFG_FUNC0_SS_X2, // SPI2_MOSI -> AP_TO_NAVAJO_SPI2_MOSI
CFG_FUNC0_SS_X2_PD, // SPI2_MISO -> NAVAJO_TO_AP_SPI2_MISO
CFG_FUNC0_SS_X2, // SPI2_SSIN -> NAVAJO_TO_PMU_INT_H
/* Port 10 */
CFG_FUNC0_SS_X4, // I2C0_SDA -> AP_BI_I2C0_SDA
CFG_FUNC0_SS_X4, // I2C0_SCL -> AP_TO_I2C0_SDA
CFG_FUNC0_SS_X4, // I2C1_SDA -> AP_BI_I2C1_SDA
CFG_FUNC0_SS_X4, // I2C1_SCL -> AP_TO_ISC1_SCL
CFG_FUNC0_SS_X4, // ISP0_SDA -> AP_BI_RCAM_I2C_SDA
CFG_FUNC0_SS_X4, // ISP0_SCL -> AP_TO_RCAM_I2C_SCL
CFG_FUNC0_SS_X4, // ISP1_SDA -> AP_TO_FCAM_I2C_SCL
CFG_FUNC0_SS_X4, // ISP1_SCL -> AP_TO_FCAM_I2C_SCL
/* Port 11 */
CFG_OUT_0_SS_X4_PD, // SENSOR0_RST -> AP_TO_RCAM_SHUTDOWN
CFG_DISABLED_SS_X4_PD, // SENSOR0_CLK -> 45_AP_TO_RCAM_CLK_R
CFG_IN_SS_X1_PU, // SENSOR0_XSHUTDOWN -> FCAM_TO_AP_ALS_INT_L
CFG_DISABLED_SS_X1_PD, // SENSOR0_ISTRB -> BB_TO_AP_IPC_GPIO
CFG_OUT_0_SS_X4_PD, // SENSOR1_RST -> AP_TO_FCAM_SHUTDOWN
CFG_DISABLED_SS_X4_PD, // SENSOR1_CLK -> 45_AP_TO_FCAM_CLK_R
CFG_DISABLED_SS_X1_PD, // SENSOR1_XSHUTDOWN -> N/C
CFG_OUT_0_SS_X4_PD, // SENSOR1_ISTRB -> AP_TO_LEDDRV_EN
/* Port 12 */
CFG_FUNC0_SS_X4_PD, // SPI3_MOSI -> AP_TO_CODEC_SPI3_MOSI
CFG_FUNC0_SS_X1_PD, // SPI3_MISO -> CODEC_TO_AP_SPI3_MISO
CFG_FUNC0_SS_X4_PD, // SPI3_SCLK -> AP_TO_CODEC_SPI3_CLK
CFG_FUNC0_SS_X4_PD, // SPI3_SSIN -> AP_TO_CODEC_SPI3_CS_L
CFG_DISABLED_SS_X1_PD, // I2C2_SDA -> N/C
CFG_DISABLED_SS_X1_PD, // I2C2_SCL -> N/C
CFG_DISABLED_SS_X4_PD, // GPIO22 -> AP_TO_PMU_KEEPACT
CFG_DISABLED_SS_X1_PD, // GPIO23 -> LCM_TO_AP_HIFA_BSYNC
/* Port 13 */
CFG_DISABLED_SS_X1_PD, // GPIO24 -> BB_TO_AP_RESET_DET_L
CFG_DISABLED_SS_X1_PU, // GPIO25 -> BOARD_INFO -> BOOT_CONFIG[1]
CFG_DISABLED_SS_X1_PD, // GPIO26 -> FORCE_DFU
CFG_DISABLED_SS_X1_PD, // GPIO27 -> DFU_STATUS
CFG_DISABLED_SS_X1_PU, // GPIO28 -> N/C -> BOOT_CONFIG[2]
CFG_DISABLED_SS_X1_PU, // GPIO29 -> N/C -> BOOT_CONFIG[3]
CFG_DISABLED, // GPIO30 -> NULL
CFG_IN_SS_X4, // GPIO31 -> AP_TO_RADIO_ON_L
/* Port 14 */
CFG_DISABLED_SS_X4, // GPIO32 -> AP_TO_BB_JTAG_TCK
CFG_DISABLED_SS_X4, // GPIO33 -> AP_TO_BB_JTAG_TMS
CFG_DISABLED_SS_X1_PU, // GPIO34 -> BOARD_INFO -> BOARD_REV3
CFG_DISABLED_SS_X1_PU, // GPIO35 -> BOARD_INFO -> BOARD_REV2
CFG_DISABLED_SS_X1_PU, // GPIO36 -> BOARD_INFO -> BOARD_REV1
CFG_DISABLED_SS_X1_PU, // GPIO37 -> BOARD_INFO -> BOARD_REV0
CFG_DISABLED_SS_X1_PU, // GPIO38 -> AP_TO_NAVAJO_DAISY_CHAIN
CFG_DISABLED_SS_X1_PD, // DISPLAY_SYNC -> N/C
/* Port 15 */
CFG_DISABLED_SS_X1_PU, // SOCHOT0 -> BB_TO_AP_SOCHOT0
CFG_FUNC0_SS_X4, // SOCHOT1 -> AP_TO_PMU_SOCHOT1
CFG_FUNC0_SS_X4_PU, // UART0_TXD -> AP_TO_TRISTAR_DEBUG_UART0_TXD
CFG_FUNC0_SS_X1_PU, // UART0_RXD -> TRISTAR_TO_AP_DEBUG_UART0_RXD
CFG_DISABLED_SS_X1_PD, // DWI_DI -> N/C
CFG_FUNC0_SS_X4_PD, // DWI_D0 -> 45_AP_TO_PMU_DWI_DO
CFG_FUNC0_SS_X4_PD, // DWI_CLK -> 45_AP_TO_PMU_DWI_CLK
CFG_DISABLED, // NULL ->
/* Port 16 */
CFG_FUNC0_SS_X4_PD, // I2S0_LRCK -> AP_TO_CODEC_ASP_I2S0_LRCLK
CFG_FUNC0_SS_X4_PD, // I2S0_BCLK -> 45_AP_TO_CODEC_ASP_I2S0_BCLK
CFG_FUNC0_SS_X4_PD, // I2S0_DOUT -> AP_TO_CODEC_ASP_I2S0_DOUT
CFG_FUNC0_SS_X1_PD, // I2S0_DIN -> CODEC_TO_AP_ASP_I2S0_DIN
CFG_DISABLED_SS_X4, // I2S1_MCK -> AP_TO_BB_JTAG_TRST_L
CFG_FUNC0_SS_X4_PD, // I2S1_LRCK -> AP_TO_BB_I2S1_LRCLK
CFG_FUNC0_SS_X4_PD, // I2S1_BCLK -> 45_AP_TO_BB_I2S1_BCLK
CFG_FUNC0_SS_X4_PD, // I2S1_DOUT -> AP_TO_BB_I2S1_DOUT
/* Port 17 */
CFG_FUNC0_SS_X1_PD, // I2S1_DIN -> BB_TO_AP_I2S1_DIN
CFG_FUNC0_SS_X4_PD, // I2S2_LRCK -> AP_TO_CODEC_XSP_I2S2_LRCLK
CFG_FUNC0_SS_X4_PD, // I2S2_BCLK -> 45_AP_TO_CODEC_XSP_I2S2_BCLK
CFG_FUNC0_SS_X4_PD, // I2S2_DOUT -> AP_TO_CODEC_XSP_I2S2_DOUT
CFG_FUNC0_SS_X1_PD, // I2S2_DIN -> CODEC_TO_AP_XSP_I2S2_DIN
CFG_IN_SS_X1_PU, // I2S3_MCK -> ALS_TO_AP_INT_L
CFG_FUNC0_SS_X4_PD, // I2S3_LRCK -> AP_TO_BT_I2S3_LRCLK
CFG_FUNC0_SS_X4_PD, // I2S3_BCLK -> 45_AP_TO_BT_I2S3_BCLK
/* Port 18 */
CFG_FUNC0_SS_X4_PD, // I2S3_DOUT -> AP_TO_BT_I2S3_DOUT
CFG_FUNC0_SS_X1_PD, // I2S3_DIN -> BT_TO_AP_I2S3_DIN
CFG_IN_SS_X1_PD, // I2S4_MCK -> TRISTAR_TO_AP_INT
CFG_FUNC0_SS_X4_PD, // I2S4_LRCK -> AP_TO_CODEC_VSP_I2S4_LRCLK
CFG_FUNC0_SS_X4_PD, // I2S4_BCLK -> 45_AP_TO_CODEC_VSP_I2S4_BCLK
CFG_FUNC0_SS_X4_PD, // I2S4_DOUT -> AP_TO_CODEC_VSP_I2S4_DOUT
CFG_FUNC0_SS_X1_PD, // I2S4_DIN -> CODEC_TO_AP_VSP_I2S4_DIN
CFG_DISABLED, // NULL ->
/* Port 19 */
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 20 */
CFG_OUT_0_SS_X4_PD, // TMR32_PWM0 -> OSCAR_BI_AP_TIME_SYNC_HOST_INT
CFG_DISABLED_SS_X4_PD, // TMR32_PWM1 -> AP_TO_PMU_VIBE_PWM_EN
CFG_FUNC0_SS_X4, // TMR32_PWM2 -> 45_AP_TO_TOUCH_CLK32K_RESET_L
CFG_OUT_0_SS_X4, // SIO_7816UART0_SDA -> AP_TO_BB_HSIC1_RDY
CFG_DISABLED_SS_X1_PD, // SIO_7816UART0_SCL -> BB_TO_AP_HSIC1_RDY
CFG_DISABLED_SS_X1_PD, // SIO_7816UART0_RST -> BB_TO_AP_HSIC1_REMOTE_WAKE
CFG_OUT_0_SS_X4, // SIO_7816UART1_SDA -> AP_TO_WLAN_HSIC2_RDY
CFG_IN_SS_X1_PD, // SIO_7816UART1_SCL -> WLAN_TO_AP_HSIC2_RDY
/* Port 21 */
CFG_IN_SS_X1_PD, // SIO_7816UART0_RST -> WLAN_TO_AP_HSIC2_REMOTE_WAKE
CFG_FUNC0_SS_X4_PU, // UART6_TXD -> AP_TO_TRISTAR_ACC_UART6_TXD
CFG_FUNC0_SS_X1_PU, // UART6_RXD -> TRISTAR_TO_AP_ACC_UART6_RXD
CFG_DISABLED_SS_X4_PD, // I2C3_SDA -> AP_BI_OSCAR_SWDIO_1V8
CFG_DISABLED_SS_X4_PD, // I2C3_SCL -> AP_TO_OSCAR_SWDCLK_1V8
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 22 */
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 23 */
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
/* Port 24 */
CFG_DISABLED_SS_X1_PD, // EPD_HPD -> N/C
CFG_FUNC0_SS_X4_PD, // I2S0_MCK -> 45_AP_TO_CODEC_I2S_MCLK_R
CFG_FUNC0_SS_X4_PD, // I2S2_MCK -> 45_AP_TO_SPKAMP_I2S2_MCLK_R
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
CFG_DISABLED, // NULL ->
};
const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
{
return gpio_default_cfg;
}
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