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iBoot/target/elbaref/pinconfig.c

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/*
* Copyright (C) 2015 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
I/O Spreadsheet version: rev 0.1
I/O Spreadsheet tracker: rdar://problem/18695359
Conversion command: csvtopinconfig.py --soc elba --config-column 'J99A Config' --radar rdar://problem/18695359 --copyright 2015 <filename>
*/
#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform.h>
#include <platform/soc/hwregbase.h>
#include <stdint.h>
static const uint32_t pinconfig_ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 0 : SPI1_SCLK -> SPI_CODEC_SCLK_R
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 1 : SPI1_MOSI -> SPI_CODEC_MOSI
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 2 : SPI1_MISO -> SPI_CODEC_MISO
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 3 : SPI1_SSIN -> SPI_CODEC_CS_L
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 4 : ISP_I2C1_SDA -> ISP_FRONT_CAM_SDA
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 5 : ISP_I2C1_SCL -> ISP_FRONT_CAM_SCL
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 6 : ISP_I2C0_SDA -> ISP_REAR_CAM_SDA
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 7 : ISP_I2C0_SCL -> ISP_REAR_CAM_SCL
/* Port 1 */
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 8 : SENSOR0_ISTRB -> NC_GPIO_SOC_TO_AUDIO_FH_KEEPALIVE
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 9 : SENSOR0_RST -> GPIO_SOC_TO_REAR_CAM_SHTDWN_L
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 10 : SENSOR0_CLK -> CLK_SOC_TO_REAR_CAM_12MHZ_R
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 11 : SENSOR0_XSHUTDOWN -> NC_SENSOR0_XSHUTDOWN
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 12 : SENSOR1_ISTRB -> GPIO_BTN_VOL_UP_L
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 13 : SENSOR1_RST -> GPIO_SOC_TO_FRONT_CAM_SHTDWN_L
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 14 : SENSOR1_CLK -> CLK_SOC_TO_FRONT_CAM_12MHZ_R
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 15 : SENSOR1_XSHUTDOWN -> GPIO_BTN_VOL_DOWN_L
/* Port 2 */
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 16 : GPIO[16] -> GPIO_BRD_ID3
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 17 : GPIO[17] -> GPIO_SOC2AJ_HS4_SHUNT_EN
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 18 : GPIO[18] -> GPIO_BOOT_CFG0
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 19 : I2S1_MCK -> SWD_KONA_IO
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 20 : I2S1_BCLK -> I2S_SOC2CODEC_ASP_BCLK_R
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 21 : I2S1_LRCK -> I2S_SOC2CODEC_ASP_LRCK
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 22 : I2S1_DIN -> I2S_CODEC2SOC_ASP_DOUT
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 23 : I2S1_DOUT -> I2S_SOC2CODEC_ASP_DOUT
/* Port 3 */
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 24 : NAND_SYS_CLK -> NAND_SYS_CLK_24MHZ
CFG_FUNC0 | PULL_UP | DRIVE_S3 | SLOW_SLEW, // 25 : S3E0_RESETN -> GPIO_SOC_TO_NAND_RESET_L
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 26 : S3E1_RESETN -> NC_PCIE_S3E1_RESET
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 27 : UART1_TXD -> UART_SOC2BB_TX
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 28 : UART1_RXD -> UART_BB2SOC_TX
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 29 : UART1_RTSN -> UART_SOC2BB_RTS_L
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 30 : UART1_CTSN -> UART_BB2SOC_RTS_L
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 31 : GPIO[43] -> GPIO_SOC2AJ_HS3_SHUNT_EN
/* Port 4 */
CFG_FUNC0 | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 32 : I2S0_BCLK -> I2S_SOC2CODEC_XSP_BCLK_R
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 33 : I2S0_LRCK -> I2S_SOC2CODEC_XSP_LRCK
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 34 : I2S0_DIN -> I2S_CODEC2SOC_XSP_DOUT
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 35 : I2S0_DOUT -> I2S_SOC2CODEC_XSP_DOUT
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 36 : I2S0_MCK -> I2S_AOP_MCLK_R
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 5 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 6 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 7 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 8 */
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 64 : I2S4_MCK -> SWD_KONA_CLK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 65 : I2S4_BCLK -> I2S_SOC_TO_BT_BCLK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 66 : I2S4_LRCK -> I2S_SOC_TO_BT_LRCK
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 67 : I2S4_DIN -> I2S_BT_TO_SOC_DOUT
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 68 : I2S4_DOUT -> I2S_SOC_TO_BT_DOUT
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 69 : I2S2_MCK -> I2S_SOC_TO_SPKRAMP_FH_MCLK_R
CFG_FUNC0 | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 70 : I2S2_BCLK -> I2S_SOC_TO_SPKRAMP_FH_BCLK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 71 : I2S2_LRCK -> I2S_SOC_TO_SPKRAMP_FH_LRCK
/* Port 9 */
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 72 : I2S2_DIN -> I2S_SPKRAMP_FH_TO_SOC_DOUT
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 73 : I2S2_DOUT -> I2S_SOC_TO_SPKRAMP_FH_DOUT
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 74 : GPIO[0] -> GPIO_CODEC_TO_SOC_IRQ_L
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 75 : GPIO[1] -> GPIO_SOC_TO_BB_RADIO_ON_L
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 76 : GPIO[2] -> GPIO_SOC_TO_NAND_FW_STRAP
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW, // 77 : GPIO[3] -> GPIO_BB_TO_SOC_RESET_DET_L
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 78 : GPIO[4] -> GPIO_TOUCH_TO_SOC_IRQ_L
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 79 : GPIO[5] -> GPIO_FH_ALS_TO_SOC_IRQ_L
/* Port 10 */
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 80 : GPIO[6] -> NC_DISPLAY_ID0
CFG_DISABLED, // 81 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 82 : GPIO[8] -> GPIO_BB_TO_SOC_GPS_SYNC
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 83 : GPIO[9] -> GPIO_CN_ALS_TO_SOC_IRQ_L
CFG_FUNC1 | DRIVE_S3 | SLOW_SLEW, // 84 : GPIO[10] -> GPIO_SOC_TO_KONA_DISPLAY_SYNC
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 85 : GPIO[11] -> GPIO_SPKAMP_FH_RIGHT_TO_SOC_IRQ_L
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 86 : GPIO[12] -> NC_DISPLAY_ID0
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 87 : GPIO[13] -> GPIO_PMU_TO_SOC_IRQ_L
/* Port 11 */
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 88 : GPIO[14] -> NC_DISPLAY_ID0
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 89 : GPIO[15] -> GPIO_SOC_TO_1V8_TOUCH_EXT_SW_ON
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 90 : UART3_TXD -> UART_SOC_TO_BT_TX
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 91 : UART3_RXD -> UART_BT_TO_SOC_TX
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 92 : UART3_RTSN -> UART_SOC_TO_BT_RTS_L
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 93 : UART3_CTSN -> UART_BT_TO_SOC_RTS_L
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 94 : SPI0_SCLK -> GPIO_BRD_ID0
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 95 : SPI0_MOSI -> GPIO_BRD_ID1
/* Port 12 */
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 96 : SPI0_MISO -> GPIO_BRD_ID2
CFG_IN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 97 : SPI0_SSIN -> GPIO_USBPD_TO_SOC_IRQ
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 98 : PCIE_PERST0_N -> PCIE_SOC_TO_NAND_RESET_L
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 99 : PCIE_PERST1_N -> NC_PCIE_PERST1
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 100 : PCIE_PERST2_N -> PCIE_SOC_TO_WLAN_RESET_L
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 101 : PCIE_PERST3_N -> GPIO_SOC_TO_BB_WAKE_MODEM
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 102 : PCIE_PERST4_N -> PCIE_SOC_TO_USB3_RESET_L
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 103 : PCIE_PERST5_N -> NC_PCIE_PERST5
/* Port 13 */
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 104 : PCIE_CLKREQ0_N -> PCIE_NAND_TO_SOC_CLKREQ_L
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 105 : PCIE_CLKREQ1_N -> NC_PCIE_CLKREQ1
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 106 : PCIE_CLKREQ2_N -> PCIE_WLAN_TO_SOC_CLKREQ_L
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 107 : PCIE_CLKREQ3_N -> PCIE_BB_TO_SOC_CLKREQ_L
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 108 : PCIE_CLKREQ4_N -> PCIE_USB3_TO_SOC_CLKREQ_L
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 109 : PCIE_CLKREQ5_N -> NC_PCIE_CLKREQ5
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 110 : UART2_TXD -> UART_SOC_TO_WLAN_TX
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 111 : UART2_RXD -> UART_WLAN_TO_SOC_TX
/* Port 14 */
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 112 : UART2_RTSN -> UART_SOC_TO_WLAN_RTS_L
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 113 : UART2_CTSN -> UART_WLAN_TO_SOC_RTS_L
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 114 : I2C3_SDA -> I2C3_SDA_1V8
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 115 : I2C3_SCL -> I2C3_SCL_1V8
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 116 : GPIO[44] -> GPIO_BRD_REV0
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 117 : GPIO[45] -> GPIO_BRD_REV1
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 118 : GPIO[46] -> GPIO_BRD_REV2
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 119 : GPIO[47] -> GPIO_BRD_REV2
/* Port 15 */
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 120 : GPIO[48] -> GPIO_TS_TO_SOC_TO_PMU_IRQ
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 121 : GPIO[49] -> GPIO_BRD_REV3
CFG_IN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 122 : MENU_KEY_L -> GPIO_BTN_HOME_L
CFG_IN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 123 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 124 : SKEY_L -> NC_SKEY_ID
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 16 */
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 128 : SWD_TMS2 -> SWD_NAND_SWDIO
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 129 : SWD_TMS3 -> SWD_KONA_SWDIO
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 130 : UART5_RTXD -> UART_BATT_HDQ
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 131 : I2C2_SDA -> I2C2_SDA_1V8
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 132 : I2C2_SCL -> I2C2_SCL_1V8
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW, // 133 : UART4_TXD -> UART_SOC_TO_ROTTERDAM_TX
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 134 : UART4_RXD -> UART_ROTTERDAM_TO_SOC_TX
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW, // 135 : UART4_RTSN -> UART_SOC_TO_ROTTERDAM_RTS_L
/* Port 17 */
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 136 : UART4_CTSN -> UART_ROTTERDAM_TO_SOC_RTS_L
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 137 : UART7_TXD -> NC_GPIO_SOC_TO_3V3_TOUCH_EXT_SW_ON
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 138 : UART7_RXD -> 1v25_CAM_LDO_EN
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 139 : CLK32K_OUT -> NC_CLK32K_OUT_24MHZ
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 140 : DP_WAKEUP0 -> SWD_ORION_SWCLK
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 141 : DP_WAKEUP1 -> SWD_ORION_SWDIO
CFG_DISABLED,
CFG_DISABLED,
/* Port 18 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 19 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 20 */
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 160 : SPI2_SCLK -> SPI_MESA_SCLK_R
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 161 : SPI2_MOSI -> SPI_MESA_MOSI
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 162 : SPI2_MISO -> SPI_MESA_MISO
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 163 : SPI2_SSIN -> GPIO_MESA_TO_SOC_IRQ
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 164 : I2C0_SDA -> I2C0_SDA_1V8
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 165 : I2C0_SCL -> I2C0_SCL_1V8
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 166 : SPI3_SCLK -> SPI_TOUCH_SCLK_R
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 167 : SPI3_MOSI -> SPI_TOUCH_MOSI
/* Port 21 */
CFG_FUNC0 | PULL_DOWN | DRIVE_S3 | SLOW_SLEW, // 168 : SPI3_MISO -> SPI_TOUCH_MISO
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 169 : SPI3_SSIN -> SPI_TOUCH_CS_L
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 170 : UART0_TXD -> UART_SOC_TO_DEBUG_TX
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 171 : UART0_RXD -> UART_DEBUG_TO_SOC_TX
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 172 : UART6_TXD -> UART_SOC_TO_ACC_TX
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 173 : UART6_RXD -> UART_ACC_TO_SOC_TX
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 174 : TMR32_PWM0 -> GPIO_SOC_TO_WLAN_DEVICE_WAKE
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 175 : TMR32_PWM1 -> GPIO_SOC_TO_BT_TO_TOUCH_TS_SYNC
/* Port 22 */
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 176 : TMR32_PWM2 -> NC_TMR32_PWM2
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 177 : I2C1_SDA -> I2C1_SDA_1V8
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 178 : I2C1_SCL -> I2C1_SCL_1V8
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 179 : GPIO[19] -> GPIO_SPKAMP_CN_RIGHT_TO_SOC_IRQ_L
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 180 : GPIO[20] -> GPIO_SOC_TO_USB3_XBAR_EN_PULSE_L
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 181 : GPIO[21] -> GPIO_SOC_TO_USB3_XBAR_DIS_PULSE_L
CFG_IN | PULL_UP | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 182 : GPIO[22] -> GPIO_SPKAMP_CN_LEFT_TO_SOC_IRQ_L
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 183 : GPIO[23] -> GPIO_USB3_TO_SOC_SMI_L
/* Port 23 */
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 184 : GPIO[24] -> GPIO_SOC_TO_AUDIO_KEEPALIVE_FH
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 185 : GPIO[25] -> GPIO_BOOT_CFG1
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 186 : GPIO[26] -> GPIO_FORCE_DFU
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 187 : PSPI_MOSI -> SPI_SOC_TO_PMU_DATA
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 188 : DWI_DO -> DWI_SOC_TO_BEACON_DO
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 189 : PMGR_MISO -> SPI_PMU_TO_SOC_DATA
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 190 : PMGR_SCLK0 -> SPI_SOC_TO_PMU_SCLK
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 191 : PMGR_SSCLK1 -> DWI_SOC_TO_BEACON_CLK
/* Port 24 */
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 192 : DROOP -> SOCHOT0_PMU_TO_SOC_L
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 193 : SOCHOT1 -> SOCHOT1_SOC_TO_PMU_L
CFG_FUNC0 | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 194 : EDP_HPD0 -> LPDP_TCON_TO_SOC_HPD
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 195 : EDP_HPD1 -> NC_EDP_HPD1
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 196 : I2S3_MCK -> I2S_SOC_TO_SPKRAMP_CN_MCLK_R
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 197 : I2S3_BCLK -> I2S_SOC_TO_SPKRAMP_CN_BCLK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 198 : I2S3_LRCK -> I2S_SOC_TO_SPKRAMP_CN_LRCK
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 199 : I2S3_DOUT -> I2S_SOC_TO_SPKRAMP_CN_DOUT
/* Port 25 */
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 200 : I2S3_DIN -> I2S_SPKRAMP_CN_TO_SOC_DOUT
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 201 : GPIO[27] -> TP_GPIO_DFU_STATUS
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 202 : GPIO[28] -> GPIO_BOOT_CFG2
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 203 : GPIO[29] -> GPIO_BRD_ID4
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 204 : GPIO[30] -> NC_EDP_HPD1
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 205 : GPIO[31] -> NC_EDP_HPD1
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 206 : GPIO[32] -> NC_EDP_HPD1
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 207 : GPIO[33] -> NC_EDP_HPD1
/* Port 26 */
CFG_DISABLED, // 208 : UNSPECIFIED -> UNSPECIFIED
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 209 : GPIO[35] -> GPIO_SOC_TO_2V85_CAM_LDO_EN
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 210 : GPIO[36] -> GPIO_SOC_TO_TOUCH_RESET_L
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 211 : GPIO[37] -> NC_EDP_HPD1
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 212 : GPIO[38] -> NC_EDP_HPD1
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 213 : GPIO[39] -> NC_EDP_HPD1
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 214 : GPIO[40] -> GPIO_SOC_TO_AUDIO_KEEPALIVE_CN
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 215 : GPIO[41] -> NC_EDP_HPD1
/* Port 27 */
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 216 : GPIO[42] -> GPIO_ORION_TO_SOC_TO_PMU_IRQ
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 217 : TST_CLKOUT -> TP_TST_CLKOUT
CFG_IN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 218 : GPU_TRIGGER1 -> GPIO_PMU_TO_SOC_UV_WARN_L
CFG_IN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 219 : GPU_TRIGGER2 -> GPIO_PMU_TO_SOC_UV_PEAKI_L
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_ap_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 0 : AOP_SPI_SCLK -> SPI_SENSORS_SCLK_R
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 1 : AOP_SPI_MOSI -> SPI_SENSORS_MOSI_R
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 2 : AOP_SPI_MISO -> SPI_SENSORS_MISO
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 3 : AOP_UART1_TXD -> GPIO_AOP_TO_WLAN_CONTEXT_A
CFG_OUT_0 | DRIVE_S3 | SLOW_SLEW, // 4 : AOP_UART1_RXD -> GPIO_AOP_TO_WLAN_CONTEXT_B
CFG_IN | DRIVE_S3 | SLOW_SLEW, // 5 : AOP_UART0_TXD -> UART_AOP_TO_BB_TX
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 6 : AOP_UART0_RXD -> UART_BB_TO_AOP_TX
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 7 : AOP_UART2_TXD -> NC_UART_AOP_TO_TOUCH_TX
/* Port 1 */
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 8 : AOP_UART2_RXD -> NC_GPIO_TOUCH_TO_AOP_DATA_REQUEST
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 9 : AOP_I2CM_SDA -> GPIO_ACCEL_TO_AOP_IRQ1
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 10 : AOP_I2CM_SCL -> SPI_ACCEL_CS_L
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 11 : AOP_FUNC[0] -> SPI_COMPASS_CS_L
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 12 : AOP_FUNC[1] -> GPIO_COMPASS_TO_AOP_IRQ
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 13 : AOP_FUNC[2] -> NC_GPIO_PHOSPHORUS_TO_AOP_IRQ
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 14 : AOP_FUNC[3] -> GPIO_CARBON_TO_AOP_IRQ1
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 15 : AOP_FUNC[4] -> SPI_CARBON_CS_L
/* Port 2 */
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 16 : AOP_FUNC[5] -> GPIO_CARBON_TO_AOP_IRQ2
CFG_OUT_1 | DRIVE_S3 | SLOW_SLEW, // 17 : AOP_FUNC[6] -> SPI_PHOSPHORUS_CS_L
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 18 : AOP_FUNC[7] -> NC_GPIO_SOC_TO_TCON_DISPLAY_SYNC
CFG_IN | PULL_DOWN | DRIVE_S3 | SLOW_SLEW | INPUT_SCHMITT, // 19 : AOP_FUNC[8] -> GPIO_ACCEL_TO_AOP_IRQ2
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 20 : AOP_FUNC[9] -> NC_GPIO_AOP_TO_LPOSC_EN
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 21 : AOP_SWD_TCK_OUT -> SWD_PERIPHERAL_SWCLK
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 22 : AOP_SWD_TMS0 -> SWD_USBPD_SWDIO
CFG_DISABLED | DRIVE_S3 | SLOW_SLEW, // 23 : AOP_SWD_TMS1 -> NC_SWD_BB_SWDIO
/* Port 3 */
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 24 : AOP_I2S_MCK -> I2S_AOP_MCLK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 25 : AOP_I2S_BCLK -> I2S_SOC2CODEC_ASP_BCLK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 26 : AOP_I2S_LRCK -> I2S_SOC2CODEC_ASP_LRCK
CFG_FUNC0 | DRIVE_S3 | SLOW_SLEW, // 27 : AOP_I2S_DIN -> I2S_CODEC2SOC_ASP_DOUT
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 0 : SPI1_SCLK -> SPI_CODEC_SCLK_R
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 1 : SPI1_MOSI -> SPI_CODEC_MOSI
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 2 : SPI1_MISO -> SPI_CODEC_MISO
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 3 : SPI1_SSIN -> SPI_CODEC_CS_L
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 4 : ISP_I2C1_SDA -> ISP_FRONT_CAM_SDA
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 5 : ISP_I2C1_SCL -> ISP_FRONT_CAM_SCL
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 6 : ISP_I2C0_SDA -> ISP_REAR_CAM_SDA
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 7 : ISP_I2C0_SCL -> ISP_REAR_CAM_SCL
/* Port 1 */
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 8 : SENSOR0_ISTRB -> NC_GPIO_SOC_TO_AUDIO_FH_KEEPALIVE
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 9 : SENSOR0_RST -> GPIO_SOC_TO_REAR_CAM_SHTDWN_L
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 10 : SENSOR0_CLK -> CLK_SOC_TO_REAR_CAM_12MHZ_R
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 11 : SENSOR0_XSHUTDOWN -> NC_SENSOR0_XSHUTDOWN
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 12 : SENSOR1_ISTRB -> GPIO_BTN_VOL_UP_L
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 13 : SENSOR1_RST -> GPIO_SOC_TO_FRONT_CAM_SHTDWN_L
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 14 : SENSOR1_CLK -> CLK_SOC_TO_FRONT_CAM_12MHZ_R
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 15 : SENSOR1_XSHUTDOWN -> GPIO_BTN_VOL_DOWN_L
/* Port 2 */
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 16 : GPIO[16] -> GPIO_BRD_ID3
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 17 : GPIO[17] -> GPIO_SOC2AJ_HS4_SHUNT_EN
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 18 : GPIO[18] -> GPIO_BOOT_CFG0
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 19 : I2S1_MCK -> SWD_KONA_IO
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 20 : I2S1_BCLK -> I2S_SOC2CODEC_ASP_BCLK_R
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 21 : I2S1_LRCK -> I2S_SOC2CODEC_ASP_LRCK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 22 : I2S1_DIN -> I2S_CODEC2SOC_ASP_DOUT
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 23 : I2S1_DOUT -> I2S_SOC2CODEC_ASP_DOUT
/* Port 3 */
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 24 : NAND_SYS_CLK -> NAND_SYS_CLK_24MHZ
CFG_FUNC0 | PULL_UP | DRIVE_S7 | SLOW_SLEW, // 25 : S3E0_RESETN -> GPIO_SOC_TO_NAND_RESET_L
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 26 : S3E1_RESETN -> NC_PCIE_S3E1_RESET
CFG_IN | DRIVE_S7 | SLOW_SLEW, // 27 : UART1_TXD -> UART_SOC2BB_TX
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 28 : UART1_RXD -> UART_BB2SOC_TX
CFG_IN | DRIVE_S7 | SLOW_SLEW, // 29 : UART1_RTSN -> UART_SOC2BB_RTS_L
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 30 : UART1_CTSN -> UART_BB2SOC_RTS_L
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 31 : GPIO[43] -> GPIO_SOC2AJ_HS3_SHUNT_EN
/* Port 4 */
CFG_FUNC0 | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 32 : I2S0_BCLK -> I2S_SOC2CODEC_XSP_BCLK_R
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 33 : I2S0_LRCK -> I2S_SOC2CODEC_XSP_LRCK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 34 : I2S0_DIN -> I2S_CODEC2SOC_XSP_DOUT
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 35 : I2S0_DOUT -> I2S_SOC2CODEC_XSP_DOUT
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 36 : I2S0_MCK -> I2S_AOP_MCLK_R
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 5 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 6 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 7 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 8 */
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 64 : I2S4_MCK -> SWD_KONA_CLK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 65 : I2S4_BCLK -> I2S_SOC_TO_BT_BCLK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 66 : I2S4_LRCK -> I2S_SOC_TO_BT_LRCK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 67 : I2S4_DIN -> I2S_BT_TO_SOC_DOUT
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 68 : I2S4_DOUT -> I2S_SOC_TO_BT_DOUT
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 69 : I2S2_MCK -> I2S_SOC_TO_SPKRAMP_FH_MCLK_R
CFG_FUNC0 | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 70 : I2S2_BCLK -> I2S_SOC_TO_SPKRAMP_FH_BCLK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 71 : I2S2_LRCK -> I2S_SOC_TO_SPKRAMP_FH_LRCK
/* Port 9 */
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 72 : I2S2_DIN -> I2S_SPKRAMP_FH_TO_SOC_DOUT
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 73 : I2S2_DOUT -> I2S_SOC_TO_SPKRAMP_FH_DOUT
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 74 : GPIO[0] -> GPIO_CODEC_TO_SOC_IRQ_L
CFG_IN | DRIVE_S4 | SLOW_SLEW, // 75 : GPIO[1] -> GPIO_SOC_TO_BB_RADIO_ON_L
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 76 : GPIO[2] -> GPIO_SOC_TO_NAND_FW_STRAP
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW, // 77 : GPIO[3] -> GPIO_BB_TO_SOC_RESET_DET_L
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 78 : GPIO[4] -> GPIO_TOUCH_TO_SOC_IRQ_L
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 79 : GPIO[5] -> GPIO_FH_ALS_TO_SOC_IRQ_L
/* Port 10 */
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 80 : GPIO[6] -> NC_DISPLAY_ID0
CFG_DISABLED, // 81 : UNSPECIFIED -> UNSPECIFIED
CFG_DISABLED | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 82 : GPIO[8] -> GPIO_BB_TO_SOC_GPS_SYNC
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 83 : GPIO[9] -> GPIO_CN_ALS_TO_SOC_IRQ_L
CFG_FUNC1 | DRIVE_S7 | SLOW_SLEW, // 84 : GPIO[10] -> GPIO_SOC_TO_KONA_DISPLAY_SYNC
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 85 : GPIO[11] -> GPIO_SPKAMP_FH_RIGHT_TO_SOC_IRQ_L
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 86 : GPIO[12] -> NC_DISPLAY_ID0
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 87 : GPIO[13] -> GPIO_PMU_TO_SOC_IRQ_L
/* Port 11 */
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 88 : GPIO[14] -> NC_DISPLAY_ID0
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 89 : GPIO[15] -> GPIO_SOC_TO_1V8_TOUCH_EXT_SW_ON
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 90 : UART3_TXD -> UART_SOC_TO_BT_TX
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 91 : UART3_RXD -> UART_BT_TO_SOC_TX
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 92 : UART3_RTSN -> UART_SOC_TO_BT_RTS_L
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 93 : UART3_CTSN -> UART_BT_TO_SOC_RTS_L
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 94 : SPI0_SCLK -> GPIO_BRD_ID0
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 95 : SPI0_MOSI -> GPIO_BRD_ID1
/* Port 12 */
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 96 : SPI0_MISO -> GPIO_BRD_ID2
CFG_IN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 97 : SPI0_SSIN -> GPIO_USBPD_TO_SOC_IRQ
CFG_IN | DRIVE_S7 | SLOW_SLEW, // 98 : PCIE_PERST0_N -> PCIE_SOC_TO_NAND_RESET_L
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 99 : PCIE_PERST1_N -> NC_PCIE_PERST1
CFG_IN | DRIVE_S4 | SLOW_SLEW, // 100 : PCIE_PERST2_N -> PCIE_SOC_TO_WLAN_RESET_L
CFG_IN | DRIVE_S7 | SLOW_SLEW, // 101 : PCIE_PERST3_N -> GPIO_SOC_TO_BB_WAKE_MODEM
CFG_IN | DRIVE_S7 | SLOW_SLEW, // 102 : PCIE_PERST4_N -> PCIE_SOC_TO_USB3_RESET_L
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 103 : PCIE_PERST5_N -> NC_PCIE_PERST5
/* Port 13 */
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 104 : PCIE_CLKREQ0_N -> PCIE_NAND_TO_SOC_CLKREQ_L
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 105 : PCIE_CLKREQ1_N -> NC_PCIE_CLKREQ1
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 106 : PCIE_CLKREQ2_N -> PCIE_WLAN_TO_SOC_CLKREQ_L
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 107 : PCIE_CLKREQ3_N -> PCIE_BB_TO_SOC_CLKREQ_L
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 108 : PCIE_CLKREQ4_N -> PCIE_USB3_TO_SOC_CLKREQ_L
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 109 : PCIE_CLKREQ5_N -> NC_PCIE_CLKREQ5
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 110 : UART2_TXD -> UART_SOC_TO_WLAN_TX
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 111 : UART2_RXD -> UART_WLAN_TO_SOC_TX
/* Port 14 */
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 112 : UART2_RTSN -> UART_SOC_TO_WLAN_RTS_L
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 113 : UART2_CTSN -> UART_WLAN_TO_SOC_RTS_L
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 114 : I2C3_SDA -> I2C3_SDA_1V8
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 115 : I2C3_SCL -> I2C3_SCL_1V8
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 116 : GPIO[44] -> GPIO_BRD_REV0
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 117 : GPIO[45] -> GPIO_BRD_REV1
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 118 : GPIO[46] -> GPIO_BRD_REV2
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 119 : GPIO[47] -> GPIO_BRD_REV2
/* Port 15 */
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 120 : GPIO[48] -> GPIO_TS_TO_SOC_TO_PMU_IRQ
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 121 : GPIO[49] -> GPIO_BRD_REV3
CFG_IN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 122 : MENU_KEY_L -> GPIO_BTN_HOME_L
CFG_IN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 123 : HOLD_KEY_L -> GPIO_BTN_ONOFF_L
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 124 : SKEY_L -> NC_SKEY_ID
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 16 */
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 128 : SWD_TMS2 -> SWD_NAND_SWDIO
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 129 : SWD_TMS3 -> SWD_KONA_SWDIO
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 130 : UART5_RTXD -> UART_BATT_HDQ
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 131 : I2C2_SDA -> I2C2_SDA_1V8
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 132 : I2C2_SCL -> I2C2_SCL_1V8
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW, // 133 : UART4_TXD -> UART_SOC_TO_ROTTERDAM_TX
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 134 : UART4_RXD -> UART_ROTTERDAM_TO_SOC_TX
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW, // 135 : UART4_RTSN -> UART_SOC_TO_ROTTERDAM_RTS_L
/* Port 17 */
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 136 : UART4_CTSN -> UART_ROTTERDAM_TO_SOC_RTS_L
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 137 : UART7_TXD -> NC_GPIO_SOC_TO_3V3_TOUCH_EXT_SW_ON
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 138 : UART7_RXD -> 1v25_CAM_LDO_EN
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 139 : CLK32K_OUT -> NC_CLK32K_OUT_24MHZ
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 140 : DP_WAKEUP0 -> SWD_ORION_SWCLK
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 141 : DP_WAKEUP1 -> SWD_ORION_SWDIO
CFG_DISABLED,
CFG_DISABLED,
/* Port 18 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 19 */
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
/* Port 20 */
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 160 : SPI2_SCLK -> SPI_MESA_SCLK_R
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 161 : SPI2_MOSI -> SPI_MESA_MOSI
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 162 : SPI2_MISO -> SPI_MESA_MISO
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 163 : SPI2_SSIN -> GPIO_MESA_TO_SOC_IRQ
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 164 : I2C0_SDA -> I2C0_SDA_1V8
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 165 : I2C0_SCL -> I2C0_SCL_1V8
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 166 : SPI3_SCLK -> SPI_TOUCH_SCLK_R
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 167 : SPI3_MOSI -> SPI_TOUCH_MOSI
/* Port 21 */
CFG_FUNC0 | PULL_DOWN | DRIVE_S7 | SLOW_SLEW, // 168 : SPI3_MISO -> SPI_TOUCH_MISO
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 169 : SPI3_SSIN -> SPI_TOUCH_CS_L
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 170 : UART0_TXD -> UART_SOC_TO_DEBUG_TX
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 171 : UART0_RXD -> UART_DEBUG_TO_SOC_TX
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 172 : UART6_TXD -> UART_SOC_TO_ACC_TX
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 173 : UART6_RXD -> UART_ACC_TO_SOC_TX
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 174 : TMR32_PWM0 -> GPIO_SOC_TO_WLAN_DEVICE_WAKE
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 175 : TMR32_PWM1 -> GPIO_SOC_TO_BT_TO_TOUCH_TS_SYNC
/* Port 22 */
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 176 : TMR32_PWM2 -> NC_TMR32_PWM2
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 177 : I2C1_SDA -> I2C1_SDA_1V8
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 178 : I2C1_SCL -> I2C1_SCL_1V8
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 179 : GPIO[19] -> GPIO_SPKAMP_CN_RIGHT_TO_SOC_IRQ_L
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 180 : GPIO[20] -> GPIO_SOC_TO_USB3_XBAR_EN_PULSE_L
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 181 : GPIO[21] -> GPIO_SOC_TO_USB3_XBAR_DIS_PULSE_L
CFG_IN | PULL_UP | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 182 : GPIO[22] -> GPIO_SPKAMP_CN_LEFT_TO_SOC_IRQ_L
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 183 : GPIO[23] -> GPIO_USB3_TO_SOC_SMI_L
/* Port 23 */
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 184 : GPIO[24] -> GPIO_SOC_TO_AUDIO_KEEPALIVE_FH
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 185 : GPIO[25] -> GPIO_BOOT_CFG1
CFG_IN | DRIVE_S7 | SLOW_SLEW, // 186 : GPIO[26] -> GPIO_FORCE_DFU
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 187 : PSPI_MOSI -> SPI_SOC_TO_PMU_DATA
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 188 : DWI_DO -> DWI_SOC_TO_BEACON_DO
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 189 : PMGR_MISO -> SPI_PMU_TO_SOC_DATA
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 190 : PMGR_SCLK0 -> SPI_SOC_TO_PMU_SCLK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 191 : PMGR_SSCLK1 -> DWI_SOC_TO_BEACON_CLK
/* Port 24 */
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 192 : DROOP -> SOCHOT0_PMU_TO_SOC_L
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 193 : SOCHOT1 -> SOCHOT1_SOC_TO_PMU_L
CFG_FUNC0 | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 194 : EDP_HPD0 -> LPDP_TCON_TO_SOC_HPD
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 195 : EDP_HPD1 -> NC_EDP_HPD1
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 196 : I2S3_MCK -> I2S_SOC_TO_SPKRAMP_CN_MCLK_R
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 197 : I2S3_BCLK -> I2S_SOC_TO_SPKRAMP_CN_BCLK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 198 : I2S3_LRCK -> I2S_SOC_TO_SPKRAMP_CN_LRCK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 199 : I2S3_DOUT -> I2S_SOC_TO_SPKRAMP_CN_DOUT
/* Port 25 */
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 200 : I2S3_DIN -> I2S_SPKRAMP_CN_TO_SOC_DOUT
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 201 : GPIO[27] -> TP_GPIO_DFU_STATUS
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 202 : GPIO[28] -> GPIO_BOOT_CFG2
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 203 : GPIO[29] -> GPIO_BRD_ID4
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 204 : GPIO[30] -> NC_EDP_HPD1
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 205 : GPIO[31] -> NC_EDP_HPD1
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 206 : GPIO[32] -> NC_EDP_HPD1
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 207 : GPIO[33] -> NC_EDP_HPD1
/* Port 26 */
CFG_DISABLED, // 208 : UNSPECIFIED -> UNSPECIFIED
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 209 : GPIO[35] -> GPIO_SOC_TO_2V85_CAM_LDO_EN
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 210 : GPIO[36] -> GPIO_SOC_TO_TOUCH_RESET_L
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 211 : GPIO[37] -> NC_EDP_HPD1
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 212 : GPIO[38] -> NC_EDP_HPD1
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 213 : GPIO[39] -> NC_EDP_HPD1
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 214 : GPIO[40] -> GPIO_SOC_TO_AUDIO_KEEPALIVE_CN
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 215 : GPIO[41] -> NC_EDP_HPD1
/* Port 27 */
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 216 : GPIO[42] -> GPIO_ORION_TO_SOC_TO_PMU_IRQ
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 217 : TST_CLKOUT -> TP_TST_CLKOUT
CFG_IN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 218 : GPU_TRIGGER1 -> GPIO_PMU_TO_SOC_UV_WARN_L
CFG_IN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 219 : GPU_TRIGGER2 -> GPIO_PMU_TO_SOC_UV_PEAKI_L
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
static const uint32_t pinconfig_dev_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {
/* Port 0 */
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 0 : AOP_SPI_SCLK -> SPI_SENSORS_SCLK_R
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 1 : AOP_SPI_MOSI -> SPI_SENSORS_MOSI_R
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 2 : AOP_SPI_MISO -> SPI_SENSORS_MISO
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 3 : AOP_UART1_TXD -> GPIO_AOP_TO_WLAN_CONTEXT_A
CFG_OUT_0 | DRIVE_S7 | SLOW_SLEW, // 4 : AOP_UART1_RXD -> GPIO_AOP_TO_WLAN_CONTEXT_B
CFG_IN | DRIVE_S7 | SLOW_SLEW, // 5 : AOP_UART0_TXD -> UART_AOP_TO_BB_TX
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 6 : AOP_UART0_RXD -> UART_BB_TO_AOP_TX
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 7 : AOP_UART2_TXD -> NC_UART_AOP_TO_TOUCH_TX
/* Port 1 */
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 8 : AOP_UART2_RXD -> NC_GPIO_TOUCH_TO_AOP_DATA_REQUEST
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 9 : AOP_I2CM_SDA -> GPIO_ACCEL_TO_AOP_IRQ1
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 10 : AOP_I2CM_SCL -> SPI_ACCEL_CS_L
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 11 : AOP_FUNC[0] -> SPI_COMPASS_CS_L
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 12 : AOP_FUNC[1] -> GPIO_COMPASS_TO_AOP_IRQ
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 13 : AOP_FUNC[2] -> NC_GPIO_PHOSPHORUS_TO_AOP_IRQ
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 14 : AOP_FUNC[3] -> GPIO_CARBON_TO_AOP_IRQ1
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 15 : AOP_FUNC[4] -> SPI_CARBON_CS_L
/* Port 2 */
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 16 : AOP_FUNC[5] -> GPIO_CARBON_TO_AOP_IRQ2
CFG_OUT_1 | DRIVE_S7 | SLOW_SLEW, // 17 : AOP_FUNC[6] -> SPI_PHOSPHORUS_CS_L
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 18 : AOP_FUNC[7] -> NC_GPIO_SOC_TO_TCON_DISPLAY_SYNC
CFG_IN | PULL_DOWN | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 19 : AOP_FUNC[8] -> GPIO_ACCEL_TO_AOP_IRQ2
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 20 : AOP_FUNC[9] -> NC_GPIO_AOP_TO_LPOSC_EN
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 21 : AOP_SWD_TCK_OUT -> SWD_PERIPHERAL_SWCLK
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 22 : AOP_SWD_TMS0 -> SWD_USBPD_SWDIO
CFG_DISABLED | DRIVE_S7 | SLOW_SLEW, // 23 : AOP_SWD_TMS1 -> NC_SWD_BB_SWDIO
/* Port 3 */
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 24 : AOP_I2S_MCK -> I2S_AOP_MCLK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 25 : AOP_I2S_BCLK -> I2S_SOC2CODEC_ASP_BCLK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW | INPUT_SCHMITT, // 26 : AOP_I2S_LRCK -> I2S_SOC2CODEC_ASP_LRCK
CFG_FUNC0 | DRIVE_S7 | SLOW_SLEW, // 27 : AOP_I2S_DIN -> I2S_CODEC2SOC_ASP_DOUT
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
CFG_DISABLED,
};
struct pinconfig_map {
uint32_t board_id;
uint32_t board_id_mask;
const uint32_t *pinconfigs[GPIOC_COUNT];
};
static const struct pinconfig_map cfg_map[] = {
{ 0, 1, { pinconfig_ap_0, pinconfig_ap_1 } },
{ 1, 1, { pinconfig_dev_0, pinconfig_dev_1 } },
};
const uint32_t * target_get_default_gpio_cfg(int gpioc)
{
static const struct pinconfig_map *selected_map = NULL;
if (selected_map == NULL) {
uint32_t board_id = platform_get_board_id();
for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
selected_map = &cfg_map[i];
break;
}
}
if (selected_map == NULL)
panic("no default pinconfig for board id %u", board_id);
}
ASSERT(gpioc < GPIOC_COUNT);
return selected_map->pinconfigs[gpioc];
}
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