2949 lines
333 KiB
HTML
2949 lines
333 KiB
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<style type="text/css">
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width = 1000px;
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td.description
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width:350px;
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td.programming
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</style>
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</head>
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<h1>AMC Initialization Sequence</h1>
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This file was created using the following files on: Tue Jul 14 10:45:09 2015<br />AMC Version: 14 Major Release: 2 Minor Release: 0<br />AMP Version: 3 Major Release: 1 Minor Release: 3<br />AMC UM Init sourced from: //depot/ip_lib/apple/amcc/a0.elba/amcc/tb/cfg/static/maqstb_cfg.pl#16<br />AMP UM Init sourced from: //depot/ip_lib/apple/amp/a0.elba/amp/tb/cfg/phy_helper_fxns.pl#7<br />
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<h4> Change Log</h4>
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* ------------------------------------------------------------------<br /> * Version:1 - Files Edited: all<br /> * Initial fiji checkin<br /> * ------------------------------------------------------------------<br /> * Version:6 - cpolapra - Files Edited: maqs_gen_cfg.pl#6 - maqs_gen_cfg_c.pl#6 - maqstb_cfg.pl#13 - mcu_helper_fxns.c#8 - <br /> * Fix compile errors from cortex boot<br /> * ------------------------------------------------------------------<br /> * Version:7 - cpolapra - Files Edited: maqstb_cfg.pl#17 - mcu_helper_fxns.c#10 - <br /> * 1600 Mhz mcu init changes<br /> * ------------------------------------------------------------------<br /> * Version:8 - herb - Files Edited: gen_mcu_init.pl#7 - <br /> * amp v0.9.2<br /> * amcx v0.0.10<br /> * amph V0007<br /> * ------------------------------------------------------------------<br /> * Version:9 - thuang - Files Edited: maqstb_cfg.pl#33 - <br /> * add back SPLLCtrl programming now that <rdar://problem/16856111> is resolved<br /> * ------------------------------------------------------------------<br />
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<h4>0. AMC Prolog</h4>
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<p>Program SPLL registers<br /> </p>
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<table class="section">
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<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td style="font-weight: bold">if (platform == ONE_CH_ONE_RANK)</td></tr>
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<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00050100<br /> ChSelHiBits = 0x5 <br /> ChSelTyp = 0x0 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x0 <br /> </td></tr>
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<tr><td style="font-weight: bold">else if (platform == ONE_CH_TWO_RANK)</td></tr>
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<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00050100<br /> ChSelHiBits = 0x5 <br /> ChSelTyp = 0x0 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x0 <br /> </td></tr>
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<tr><td style="font-weight: bold">else if (platform == FOUR_CH_ONE_RANK)</td></tr>
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<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00050110<br /> ChSelHiBits = 0x5 <br /> ChSelTyp = 0x0 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x1 <br /> </td></tr>
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<tr><td style="font-weight: bold">else if (platform == TWO_CH_TWO_RANK)</td></tr>
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<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00050100<br /> ChSelHiBits = 0x5 <br /> ChSelTyp = 0x0 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x0 <br /> </td></tr>
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<tr><td style="font-weight: bold">else if (platform == FOUR_CH_TWO_RANK)</td></tr>
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<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00050110<br /> ChSelHiBits = 0x5 <br /> ChSelTyp = 0x0 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x1 <br /> </td></tr>
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<tr><td style="font-weight: bold">else if (platform == EIGHT_CH_ONE_RANK)</td></tr>
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<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00050120<br /> ChSelHiBits = 0x5 <br /> ChSelTyp = 0x0 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x2 <br /> </td></tr>
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<tr><td style="font-weight: bold">else if (platform == TWO_CH_ONE_RANK)</td></tr>
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<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00050100<br /> ChSelHiBits = 0x5 <br /> ChSelTyp = 0x0 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x0 <br /> </td></tr>
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<tr><td style="font-weight: bold">else</td></tr>
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<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00050120<br /> ChSelHiBits = 0x5 <br /> ChSelTyp = 0x0 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x2 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> spllctrl_SpllCtrl_ChargePump(n) = 0x00000068<br /> slvpll_cp_boost = 0x0 <br /> slvpll_cp_i_set = 0x3 <br /> slvpll_cp_lp = 0x0 <br /> slvpll_cp_md = 0x0 <br /> slvpll_cp_pd = 0x0 <br /> slvpll_cp_r_set = 0x8 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> spllctrl_SpllCtrl_ModeReg(n) = 0x00000001<br /> override_spll_lock = 0x0 <br /> override_spllseq_outputs = 0x0 <br /> override_value_spll_lock = 0x0 <br /> slvpll_byp = 0x0 <br /> slvpll_mode = 0x1 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> spllctrl_SpllCtrl_VCO(n) = 0x00000016<br /> slvpll_vco_buf_pd = 0x0 <br /> slvpll_vco_cap = 0x1 <br /> slvpll_vco_kvco = 0x0 <br /> slvpll_vco_pd = 0x0 <br /> slvpll_vco_rv2i = 0x6 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> spllctrl_SpllCtrl_VCO(n) = 0x00000015<br /> slvpll_vco_buf_pd = 0x0 <br /> slvpll_vco_cap = 0x1 <br /> slvpll_vco_kvco = 0x0 <br /> slvpll_vco_pd = 0x0 <br /> slvpll_vco_rv2i = 0x5 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> spllctrl_SpllCtrl_LDO(n) = 0x00000004<br /> slvpll_bg_start_sel = 0x0 <br /> slvpll_reg_pd = 0x0 <br /> slvpll_vreg_adj = 0x4 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> spllctrl_SpllCtrl_SPLLPwrDnCfg(n) = 0x00000011<br /> bypass_en_stby_pd = 0x1 <br /> spll_fast_pd_exit = 0x0 <br /> spll_mode_dcs_pwrdn = 0x1 <br /> use_idle_for_pd = 0x0 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Call custom API provided in mcu_helper_fxns.c for setting PLL3 frequency to 132.33Mhz. This call is only applicable to Cold boot. <br /><br /><b>FPGA:</b> Skip this step<br /><br /> </td>
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<td><table class="platform">
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Call custom API provided in mcu_helper_fxns.c for setting PLL3 frequency to 132.33Mhz. This call is only applicable to Cold boot. <br /><br /><b>FPGA:</b> Skip this step<br /><br /> </td>
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<td><table class="platform">
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
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<h4>1. AMC Initial Configuration</h4>
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<p>Perform the proper configurations of the AMC. Note that all the timing parameters should be programmed with respect to the normal clock, not the slow boot clock.<br /> </p>
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<table class="section">
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<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
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</table>
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<h4> Setting up MCU registers and FSP for Freq change</h4>
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<p><br /> </p>
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<table class="section">
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<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
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</tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> amcx_dramcfg_freqchngctl0_freq0(n) = 0x18cd104d<br /> freqchngmrw0_addr_freq0 = 0xd <br /> freqchngmrw0_ctrl_freq0 = 0x1 <br /> freqchngmrw0_data_freq0 = 0x10 <br /> freqchngmrw1_addr_freq0 = 0xd <br /> freqchngmrw1_ctrl_freq0 = 0x3 <br /> freqchngmrw1_data_freq0 = 0x18 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> amcx_dramcfg_freqchngctl1_freq0(n) = 0x110c110e<br /> freqchngmrw2_addr_freq0 = 0xe <br /> freqchngmrw2_ctrl_freq0 = 0x0 <br /> freqchngmrw2_data_freq0 = 0x11 <br /> freqchngmrw3_addr_freq0 = 0xc <br /> freqchngmrw3_ctrl_freq0 = 0x0 <br /> freqchngmrw3_data_freq0 = 0x11 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
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<tr><td class="programming"> amcx_dramcfg_freqchngctl2_freq0(n) = 0xb303000b<br /> freqchngmrw4_addr_freq0 = 0xb <br /> freqchngmrw4_ctrl_freq0 = 0x0 <br /> freqchngmrw4_data_freq0 = 0x0 <br /> freqchngmrw5_addr_freq0 = 0x3 <br /> freqchngmrw5_ctrl_freq0 = 0x0 <br /> freqchngmrw5_data_freq0 = 0xb3 <br /> </td></tr>
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<tr><td style="font-weight: bold">else</td></tr>
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<tr><td class="programming"> amcx_dramcfg_freqchngctl2_freq0(n) = 0xb303440b<br /> freqchngmrw4_addr_freq0 = 0xb <br /> freqchngmrw4_ctrl_freq0 = 0x0 <br /> freqchngmrw4_data_freq0 = 0x44 <br /> freqchngmrw5_addr_freq0 = 0x3 <br /> freqchngmrw5_ctrl_freq0 = 0x0 <br /> freqchngmrw5_data_freq0 = 0xb3 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> amcx_dramcfg_freqchngctl3_freq0(n) = 0xde012d02<br /> freqchngmrw6_addr_freq0 = 0x2 <br /> freqchngmrw6_ctrl_freq0 = 0x0 <br /> freqchngmrw6_data_freq0 = 0x2d <br /> freqchngmrw7_addr_freq0 = 0x1 <br /> freqchngmrw7_ctrl_freq0 = 0x0 <br /> freqchngmrw7_data_freq0 = 0xde <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> amcx_dramcfg_freqchngctl4_freq0(n) = 0x00000416<br /> freqchngmrw8_addr_freq0 = 0x16 <br /> freqchngmrw8_ctrl_freq0 = 0x0 <br /> freqchngmrw8_data_freq0 = 0x4 <br /> freqchngmrw9_addr_freq0 = 0x0 <br /> freqchngmrw9_ctrl_freq0 = 0x0 <br /> freqchngmrw9_data_freq0 = 0x0 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> amcx_dramcfg_freqchngtim_freq0(n) = 0x000c1108<br /> freqchngclkofflat_freq0 = 0x8 <br /> freqchngclkonlat_freq0 = 0x11 <br /> freqchngsocupdlat_freq0 = 0xc <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> amcx_dramcfg_freqchngctl0_freq1(n) = 0x18cd104d<br /> freqchngmrw0_addr_freq1 = 0xd <br /> freqchngmrw0_ctrl_freq1 = 0x1 <br /> freqchngmrw0_data_freq1 = 0x10 <br /> freqchngmrw1_addr_freq1 = 0xd <br /> freqchngmrw1_ctrl_freq1 = 0x3 <br /> freqchngmrw1_data_freq1 = 0x18 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> amcx_dramcfg_freqchngctl1_freq1(n) = 0x110c110e<br /> freqchngmrw2_addr_freq1 = 0xe <br /> freqchngmrw2_ctrl_freq1 = 0x0 <br /> freqchngmrw2_data_freq1 = 0x11 <br /> freqchngmrw3_addr_freq1 = 0xc <br /> freqchngmrw3_ctrl_freq1 = 0x0 <br /> freqchngmrw3_data_freq1 = 0x11 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
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<tr><td class="programming"> amcx_dramcfg_freqchngctl2_freq1(n) = 0xd303000b<br /> freqchngmrw4_addr_freq1 = 0xb <br /> freqchngmrw4_ctrl_freq1 = 0x0 <br /> freqchngmrw4_data_freq1 = 0x0 <br /> freqchngmrw5_addr_freq1 = 0x3 <br /> freqchngmrw5_ctrl_freq1 = 0x0 <br /> freqchngmrw5_data_freq1 = 0xd3 <br /> </td></tr>
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<tr><td style="font-weight: bold">else</td></tr>
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<tr><td class="programming"> amcx_dramcfg_freqchngctl2_freq1(n) = 0xd303220b<br /> freqchngmrw4_addr_freq1 = 0xb <br /> freqchngmrw4_ctrl_freq1 = 0x0 <br /> freqchngmrw4_data_freq1 = 0x22 <br /> freqchngmrw5_addr_freq1 = 0x3 <br /> freqchngmrw5_ctrl_freq1 = 0x0 <br /> freqchngmrw5_data_freq1 = 0xd3 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> amcx_dramcfg_freqchngctl3_freq1(n) = 0xae015202<br /> freqchngmrw6_addr_freq1 = 0x2 <br /> freqchngmrw6_ctrl_freq1 = 0x0 <br /> freqchngmrw6_data_freq1 = 0x52 <br /> freqchngmrw7_addr_freq1 = 0x1 <br /> freqchngmrw7_ctrl_freq1 = 0x0 <br /> freqchngmrw7_data_freq1 = 0xae <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> amcx_dramcfg_freqchngctl4_freq1(n) = 0x00000216<br /> freqchngmrw8_addr_freq1 = 0x16 <br /> freqchngmrw8_ctrl_freq1 = 0x0 <br /> freqchngmrw8_data_freq1 = 0x2 <br /> freqchngmrw9_addr_freq1 = 0x0 <br /> freqchngmrw9_ctrl_freq1 = 0x0 <br /> freqchngmrw9_data_freq1 = 0x0 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> amcx_dramcfg_freqchngtim_freq1(n) = 0x000c1108<br /> freqchngclkofflat_freq1 = 0x8 <br /> freqchngclkonlat_freq1 = 0x11 <br /> freqchngsocupdlat_freq1 = 0xc <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<td class="description" valign="top" > </td>
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<td><table class="platform">
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<tr><td class="programming"> amcx_dramcfg_freqchngctl0_freq2(n) = 0x18cd104d<br /> freqchngmrw0_addr_freq2 = 0xd <br /> freqchngmrw0_ctrl_freq2 = 0x1 <br /> freqchngmrw0_data_freq2 = 0x10 <br /> freqchngmrw1_addr_freq2 = 0xd <br /> freqchngmrw1_ctrl_freq2 = 0x3 <br /> freqchngmrw1_data_freq2 = 0x18 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl1_freq2(n) = 0x590c590e<br /> freqchngmrw2_addr_freq2 = 0xe <br /> freqchngmrw2_ctrl_freq2 = 0x0 <br /> freqchngmrw2_data_freq2 = 0x59 <br /> freqchngmrw3_addr_freq2 = 0xc <br /> freqchngmrw3_ctrl_freq2 = 0x0 <br /> freqchngmrw3_data_freq2 = 0x59 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl2_freq2(n) = 0xf303000b<br /> freqchngmrw4_addr_freq2 = 0xb <br /> freqchngmrw4_ctrl_freq2 = 0x0 <br /> freqchngmrw4_data_freq2 = 0x0 <br /> freqchngmrw5_addr_freq2 = 0x3 <br /> freqchngmrw5_ctrl_freq2 = 0x0 <br /> freqchngmrw5_data_freq2 = 0xf3 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl2_freq2(n) = 0xf303000b<br /> freqchngmrw4_addr_freq2 = 0xb <br /> freqchngmrw4_ctrl_freq2 = 0x0 <br /> freqchngmrw4_data_freq2 = 0x0 <br /> freqchngmrw5_addr_freq2 = 0x3 <br /> freqchngmrw5_ctrl_freq2 = 0x0 <br /> freqchngmrw5_data_freq2 = 0xf3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl3_freq2(n) = 0x8e010002<br /> freqchngmrw6_addr_freq2 = 0x2 <br /> freqchngmrw6_ctrl_freq2 = 0x0 <br /> freqchngmrw6_data_freq2 = 0x0 <br /> freqchngmrw7_addr_freq2 = 0x1 <br /> freqchngmrw7_ctrl_freq2 = 0x0 <br /> freqchngmrw7_data_freq2 = 0x8e <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl4_freq2(n) = 0x00000016<br /> freqchngmrw8_addr_freq2 = 0x16 <br /> freqchngmrw8_ctrl_freq2 = 0x0 <br /> freqchngmrw8_data_freq2 = 0x0 <br /> freqchngmrw9_addr_freq2 = 0x0 <br /> freqchngmrw9_ctrl_freq2 = 0x0 <br /> freqchngmrw9_data_freq2 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngtim_freq2(n) = 0x000c1108<br /> freqchngclkofflat_freq2 = 0x8 <br /> freqchngclkonlat_freq2 = 0x11 <br /> freqchngsocupdlat_freq2 = 0xc <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl0_freq3(n) = 0x18cd104d<br /> freqchngmrw0_addr_freq3 = 0xd <br /> freqchngmrw0_ctrl_freq3 = 0x1 <br /> freqchngmrw0_data_freq3 = 0x10 <br /> freqchngmrw1_addr_freq3 = 0xd <br /> freqchngmrw1_ctrl_freq3 = 0x3 <br /> freqchngmrw1_data_freq3 = 0x18 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl1_freq3(n) = 0x590c590e<br /> freqchngmrw2_addr_freq3 = 0xe <br /> freqchngmrw2_ctrl_freq3 = 0x0 <br /> freqchngmrw2_data_freq3 = 0x59 <br /> freqchngmrw3_addr_freq3 = 0xc <br /> freqchngmrw3_ctrl_freq3 = 0x0 <br /> freqchngmrw3_data_freq3 = 0x59 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl2_freq3(n) = 0xf303000b<br /> freqchngmrw4_addr_freq3 = 0xb <br /> freqchngmrw4_ctrl_freq3 = 0x0 <br /> freqchngmrw4_data_freq3 = 0x0 <br /> freqchngmrw5_addr_freq3 = 0x3 <br /> freqchngmrw5_ctrl_freq3 = 0x0 <br /> freqchngmrw5_data_freq3 = 0xf3 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl2_freq3(n) = 0xf303000b<br /> freqchngmrw4_addr_freq3 = 0xb <br /> freqchngmrw4_ctrl_freq3 = 0x0 <br /> freqchngmrw4_data_freq3 = 0x0 <br /> freqchngmrw5_addr_freq3 = 0x3 <br /> freqchngmrw5_ctrl_freq3 = 0x0 <br /> freqchngmrw5_data_freq3 = 0xf3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl3_freq3(n) = 0x8e010002<br /> freqchngmrw6_addr_freq3 = 0x2 <br /> freqchngmrw6_ctrl_freq3 = 0x0 <br /> freqchngmrw6_data_freq3 = 0x0 <br /> freqchngmrw7_addr_freq3 = 0x1 <br /> freqchngmrw7_ctrl_freq3 = 0x0 <br /> freqchngmrw7_data_freq3 = 0x8e <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl4_freq3(n) = 0x00000016<br /> freqchngmrw8_addr_freq3 = 0x16 <br /> freqchngmrw8_ctrl_freq3 = 0x0 <br /> freqchngmrw8_data_freq3 = 0x0 <br /> freqchngmrw9_addr_freq3 = 0x0 <br /> freqchngmrw9_ctrl_freq3 = 0x0 <br /> freqchngmrw9_data_freq3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngtim_freq3(n) = 0x000c1108<br /> freqchngclkofflat_freq3 = 0x8 <br /> freqchngclkonlat_freq3 = 0x11 <br /> freqchngsocupdlat_freq3 = 0xc <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_WrDqCalVREFCodeControl(n) = 0x19191111<br /> WrDqCalVREFCode_f0 = 0x11 <br /> WrDqCalVREFCode_f1 = 0x11 <br /> WrDqCalVREFCode_f2 = 0x19 <br /> WrDqCalVREFCode_f3 = 0x19 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_RdDqCalVREFCodeControl(n) = 0x19191191<br /> RdDqCalVREFCode_f0 = 0x91 <br /> RdDqCalVREFCode_f1 = 0x11 <br /> RdDqCalVREFCode_f2 = 0x19 <br /> RdDqCalVREFCode_f3 = 0x19 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWRdDqCalVREFControl(n) = 0x02d0b060<br /> HWRdDqCalVREFEnable = 0x0 <br /> HWRdDqCalVREFMax = 0xd0 <br /> HWRdDqCalVREFMaxOffsetScaleFactor = 0x2 <br /> HWRdDqCalVREFMaxScoreSel = 0x0 <br /> HWRdDqCalVREFMin = 0xb0 <br /> HWRdDqCalVREFNumPoints = 0x6 <br /> HWRdDqCalVREFScoreMinSel = 0x0 <br /> HWRdDqCalVREFStaticSel = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWRdDqCalVREFOffsetControl1(n) = 0x06040200<br /> HWRdDqCalOffset0 = 0x0 <br /> HWRdDqCalOffset1 = 0x2 <br /> HWRdDqCalOffset2 = 0x4 <br /> HWRdDqCalOffset3 = 0x6 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWRdDqCalVREFOffsetControl2(n) = 0x00fafcfe<br /> HWRdDqCalOffset4 = 0xfe <br /> HWRdDqCalOffset5 = 0xfc <br /> HWRdDqCalOffset6 = 0xfa <br /> HWRdDqCalOffset7 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWWrDqCalVREFControl(n) = 0x02200060<br /> HWWrDqCalVREFEnable = 0x0 <br /> HWWrDqCalVREFMax = 0x20 <br /> HWWrDqCalVREFMaxOffsetScaleFactor = 0x2 <br /> HWWrDqCalVREFMaxScoreSel = 0x0 <br /> HWWrDqCalVREFMin = 0x0 <br /> HWWrDqCalVREFNumPoints = 0x6 <br /> HWWrDqCalVREFScoreMinSel = 0x0 <br /> HWWrDqCalVREFStaticSel = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWWrDqCalVREFOffsetControl1(n) = 0x06040200<br /> HWWrDqCalOffset0 = 0x0 <br /> HWWrDqCalOffset1 = 0x2 <br /> HWWrDqCalOffset2 = 0x4 <br /> HWWrDqCalOffset3 = 0x6 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWWrDqCalVREFOffsetControl2(n) = 0x00fafcfe<br /> HWWrDqCalOffset4 = 0xfe <br /> HWWrDqCalOffset5 = 0xfc <br /> HWWrDqCalOffset6 = 0xfa <br /> HWWrDqCalOffset7 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_PerVrefCalCfg = 0x00000003<br /> LegacyMode = 0x0 <br /> PreVrefDcc = 0x1 <br /> PreVrefMdll = 0x1 <br /> PreVrefTimCal = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_VrefCntrl = 0x00060006<br /> VrefPointsRd = 0x6 <br /> VrefPointsWr = 0x6 <br /> override_refready = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramtim_modereg(n) = 0x120c90b8<br /> tMRRCyc = 0x8 <br /> tMRRICyc = 0xb <br /> tMRWCyc = 0x9 <br /> tVRCGOFFCyc = 0xc <br /> tZQLatCyc = 0x12 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramcfg_rwcfg(n) = 0x000210ef<br /> CasAPEn = 0x1 <br /> DBIRDEn_freq0 = 0x0 <br /> DBIRDEn_freq1 = 0x1 <br /> DBIRDEn_freq2 = 0x1 <br /> DBIRDEn_freq3 = 0x1 <br /> DBIWREn_freq0 = 0x1 <br /> DBIWREn_freq1 = 0x1 <br /> DBIWREn_freq2 = 0x1 <br /> DBIWREn_freq3 = 0x1 <br /> DBIWRType = 0x0 <br /> tCCDMWCyc = 0x2 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramcfg_rwcfg(n) = 0x000210ef<br /> CasAPEn = 0x1 <br /> DBIRDEn_freq0 = 0x0 <br /> DBIRDEn_freq1 = 0x1 <br /> DBIRDEn_freq2 = 0x1 <br /> DBIRDEn_freq3 = 0x1 <br /> DBIWREn_freq0 = 0x1 <br /> DBIWREn_freq1 = 0x1 <br /> DBIWREn_freq2 = 0x1 <br /> DBIWREn_freq3 = 0x1 <br /> DBIWRType = 0x0 <br /> tCCDMWCyc = 0x2 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqdllctl_dllupdtctrl(n) = 0x50017350<br /> DllInitUpdtDur = 0x7 <br /> DllUpdtDur = 0x3 <br /> DllUpdtMode = 0x1 <br /> DllUpdtPhyUpdtTyp = 0x0 <br /> FreqChangeSDLLUpdDur = 0x50 <br /> SDLLUpdDur = 0x50 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscadllctl_dllupdtctrl(n) = 0x50017350<br /> DllInitUpdtDur = 0x7 <br /> DllUpdtDur = 0x3 <br /> DllUpdtMode = 0x1 <br /> DllUpdtPhyUpdtTyp = 0x0 <br /> FreqChangeSDLLUpdDur = 0x50 <br /> SDLLUpdDur = 0x50 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramtim_pdn(n) = 0x72276265<br /> tCKECyc = 0x5 <br /> tCKEPDECyc = 0x1 <br /> tCKESRCyc = 0x6 <br /> tCKEafSRCyc = 0x2 <br /> tCKEb4SRCyc = 0x7 <br /> tCKafCKECyc = 0x7 <br /> tCKb4CKECyc = 0x2 <br /> tXPCyc = 0x6 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Configure DRAM timing parameters for default frequencyset. Example here shows LPDDR4-3200 8Gb DRAM die. See Section 3.2.2.4 for other value. <br /> Configure the PHY timing. These are determined by the design of the PHY and the interface between the PHY and AMC. </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_lat_freq0(n) = 0x001030c2<br /> DRAMRL_freq0 = 0x3 <br /> DRAMWL_freq0 = 0x2 <br /> tDQSCKMaxCyc_freq0 = 0x3 <br /> tDQSCKMinCyc_freq0 = 0x0 <br /> tDQSSMaxCyc_freq0 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_lat_freq0(n) = 0x00103387<br /> DRAMRL_freq0 = 0xe <br /> DRAMWL_freq0 = 0x7 <br /> tDQSCKMaxCyc_freq0 = 0x3 <br /> tDQSCKMinCyc_freq0 = 0x0 <br /> tDQSSMaxCyc_freq0 = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_lat_freq1(n) = 0x001020c2<br /> DRAMRL_freq1 = 0x3 <br /> DRAMWL_freq1 = 0x2 <br /> tDQSCKMaxCyc_freq1 = 0x2 <br /> tDQSCKMinCyc_freq1 = 0x0 <br /> tDQSSMaxCyc_freq1 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_lat_freq1(n) = 0x00102206<br /> DRAMRL_freq1 = 0x8 <br /> DRAMWL_freq1 = 0x6 <br /> tDQSCKMaxCyc_freq1 = 0x2 <br /> tDQSCKMinCyc_freq1 = 0x0 <br /> tDQSSMaxCyc_freq1 = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_phytim_phyrdwrtim_freq0(n) = 0x00010d01<br /> PHYRdLat_freq0 = 0xd <br /> PHYtPhyWrlat_freq0 = 0x1 <br /> PHYtRddataEn_freq0 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_phytim_phyrdwrtim_freq0(n) = 0x00060d0c<br /> PHYRdLat_freq0 = 0xd <br /> PHYtPhyWrlat_freq0 = 0x6 <br /> PHYtRddataEn_freq0 = 0xc <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_phytim_phyrdwrtim_freq1(n) = 0x00010b01<br /> PHYRdLat_freq1 = 0xb <br /> PHYtPhyWrlat_freq1 = 0x1 <br /> PHYtRddataEn_freq1 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_phytim_phyrdwrtim_freq1(n) = 0x00050b06<br /> PHYRdLat_freq1 = 0xb <br /> PHYtPhyWrlat_freq1 = 0x5 <br /> PHYtRddataEn_freq1 = 0x6 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_phytim_phyrdwrtim_freq2(n) = 0x00010b01<br /> PHYRdLat_freq2 = 0xb <br /> PHYtPhyWrlat_freq2 = 0x1 <br /> PHYtRddataEn_freq2 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_phytim_phyrdwrtim_freq2(n) = 0x00010b01<br /> PHYRdLat_freq2 = 0xb <br /> PHYtPhyWrlat_freq2 = 0x1 <br /> PHYtRddataEn_freq2 = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_phytim_phyrdwrtim_freq3(n) = 0x00010901<br /> PHYRdLat_freq3 = 0x9 <br /> PHYtPhyWrlat_freq3 = 0x1 <br /> PHYtRddataEn_freq3 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_phytim_phyrdwrtim_freq3(n) = 0x00010901<br /> PHYRdLat_freq3 = 0x9 <br /> PHYtPhyWrlat_freq3 = 0x1 <br /> PHYtRddataEn_freq3 = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_caspch_freq0(n) = 0x63e2080f<br /> tRASCyc_freq0 = 0x22 <br /> tRCDCyc_freq0 = 0xf <br /> tRTPCyc_freq0 = 0x6 <br /> tWRCyc_freq0 = 0xf <br /> tWTRCyc_freq0 = 0x8 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_caspch_freq0(n) = 0x40c20402<br /> tRASCyc_freq0 = 0x2 <br /> tRCDCyc_freq0 = 0x2 <br /> tRTPCyc_freq0 = 0x4 <br /> tWRCyc_freq0 = 0x3 <br /> tWTRCyc_freq0 = 0x4 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_caspch_freq0(n) = 0x63e2080f<br /> tRASCyc_freq0 = 0x22 <br /> tRCDCyc_freq0 = 0xf <br /> tRTPCyc_freq0 = 0x6 <br /> tWRCyc_freq0 = 0xf <br /> tWTRCyc_freq0 = 0x8 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_act_freq0(n) = 0x2008110f<br /> tFAWCyc_freq0 = 0x20 <br /> tRPCyc_freq0 = 0xf <br /> tRPabCyc_freq0 = 0x11 <br /> tRRDCyc_freq0 = 0x8 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_act_freq0(n) = 0x01020202<br /> tFAWCyc_freq0 = 0x1 <br /> tRPCyc_freq0 = 0x2 <br /> tRPabCyc_freq0 = 0x2 <br /> tRRDCyc_freq0 = 0x2 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_act_freq0(n) = 0x2008110f<br /> tFAWCyc_freq0 = 0x20 <br /> tRPCyc_freq0 = 0xf <br /> tRPabCyc_freq0 = 0x11 <br /> tRRDCyc_freq0 = 0x8 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq0(n) = 0x48900078<br /> tRFCBaseCyc_freq0 = 0x78 <br /> tRFCCyc_freq0 = 0x90 <br /> tRFCpbCyc_freq0 = 0x48 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq0(n) = 0x01010078<br /> tRFCBaseCyc_freq0 = 0x78 <br /> tRFCCyc_freq0 = 0x1 <br /> tRFCpbCyc_freq0 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq0(n) = 0x48900078<br /> tRFCBaseCyc_freq0 = 0x78 <br /> tRFCCyc_freq0 = 0x90 <br /> tRFCpbCyc_freq0 = 0x48 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_selfref_freq0(n) = 0xa0096012<br /> tFCCyc_freq0 = 0xa0 <br /> tXSRCyc_freq0 = 0x96 <br /> tZQCalCyc_freq0 = 0x12 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_selfref_freq0(n) = 0x28002012<br /> tFCCyc_freq0 = 0x28 <br /> tXSRCyc_freq0 = 0x2 <br /> tZQCalCyc_freq0 = 0x12 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_selfref_freq0(n) = 0xa0096012<br /> tFCCyc_freq0 = 0xa0 <br /> tXSRCyc_freq0 = 0x96 <br /> tZQCalCyc_freq0 = 0x12 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_modereg(n) = 0x1a0cc0f4<br /> tMRRCyc = 0x4 <br /> tMRRICyc = 0xf <br /> tMRWCyc = 0xc <br /> tVRCGOFFCyc = 0xc <br /> tZQLatCyc = 0x1a <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_modereg(n) = 0x060c5024<br /> tMRRCyc = 0x4 <br /> tMRRICyc = 0x2 <br /> tMRWCyc = 0x5 <br /> tVRCGOFFCyc = 0xc <br /> tZQLatCyc = 0x6 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_modereg(n) = 0x1a0cc0f4<br /> tMRRCyc = 0x4 <br /> tMRRICyc = 0xf <br /> tMRWCyc = 0xc <br /> tVRCGOFFCyc = 0xc <br /> tZQLatCyc = 0x1a <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Configure DRAM timing parameters for alternative frequency points. For the dynamic frequency change support, all frequency sets should be programmed. See Section 3.2.2.3 for details. The actual values should correspond to the desired frequency points and the actual device specifications. <br />(N=1/2/3)<br />*since mcu_clk freq1 = 200MHz and per-bank refresh is not enabled,<br />mcusch.mifcassch_freq1. HiTempRefRnkAgeOut_freq1 =0x0 </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_caspch_freq1(n) = 0x63e2080f<br /> tRASCyc_freq1 = 0x22 <br /> tRCDCyc_freq1 = 0xf <br /> tRTPCyc_freq1 = 0x6 <br /> tWRCyc_freq1 = 0xf <br /> tWTRCyc_freq1 = 0x8 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_caspch_freq1(n) = 0x40c20402<br /> tRASCyc_freq1 = 0x2 <br /> tRCDCyc_freq1 = 0x2 <br /> tRTPCyc_freq1 = 0x4 <br /> tWRCyc_freq1 = 0x3 <br /> tWTRCyc_freq1 = 0x4 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_caspch_freq1(n) = 0x42110408<br /> tRASCyc_freq1 = 0x11 <br /> tRCDCyc_freq1 = 0x8 <br /> tRTPCyc_freq1 = 0x4 <br /> tWRCyc_freq1 = 0x8 <br /> tWTRCyc_freq1 = 0x4 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_act_freq1(n) = 0x2008110f<br /> tFAWCyc_freq1 = 0x20 <br /> tRPCyc_freq1 = 0xf <br /> tRPabCyc_freq1 = 0x11 <br /> tRRDCyc_freq1 = 0x8 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_act_freq1(n) = 0x01020202<br /> tFAWCyc_freq1 = 0x1 <br /> tRPCyc_freq1 = 0x2 <br /> tRPabCyc_freq1 = 0x2 <br /> tRRDCyc_freq1 = 0x2 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_act_freq1(n) = 0x10040908<br /> tFAWCyc_freq1 = 0x10 <br /> tRPCyc_freq1 = 0x8 <br /> tRPabCyc_freq1 = 0x9 <br /> tRRDCyc_freq1 = 0x4 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq1(n) = 0x48900050<br /> tRFCBaseCyc_freq1 = 0x50 <br /> tRFCCyc_freq1 = 0x90 <br /> tRFCpbCyc_freq1 = 0x48 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq1(n) = 0x01010050<br /> tRFCBaseCyc_freq1 = 0x50 <br /> tRFCCyc_freq1 = 0x1 <br /> tRFCpbCyc_freq1 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq1(n) = 0x24480050<br /> tRFCBaseCyc_freq1 = 0x50 <br /> tRFCCyc_freq1 = 0x48 <br /> tRFCpbCyc_freq1 = 0x24 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_selfref_freq1(n) = 0xa0096012<br /> tFCCyc_freq1 = 0xa0 <br /> tXSRCyc_freq1 = 0x96 <br /> tZQCalCyc_freq1 = 0x12 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_selfref_freq1(n) = 0x28002012<br /> tFCCyc_freq1 = 0x28 <br /> tXSRCyc_freq1 = 0x2 <br /> tZQCalCyc_freq1 = 0x12 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_selfref_freq1(n) = 0x5004b012<br /> tFCCyc_freq1 = 0x50 <br /> tXSRCyc_freq1 = 0x4b <br /> tZQCalCyc_freq1 = 0x12 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_caspch_freq2(n) = 0x63e2080f<br /> tRASCyc_freq2 = 0x22 <br /> tRCDCyc_freq2 = 0xf <br /> tRTPCyc_freq2 = 0x6 <br /> tWRCyc_freq2 = 0xf <br /> tWTRCyc_freq2 = 0x8 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_caspch_freq2(n) = 0x40c20402<br /> tRASCyc_freq2 = 0x2 <br /> tRCDCyc_freq2 = 0x2 <br /> tRTPCyc_freq2 = 0x4 <br /> tWRCyc_freq2 = 0x3 <br /> tWTRCyc_freq2 = 0x4 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_caspch_freq2(n) = 0x40c50402<br /> tRASCyc_freq2 = 0x5 <br /> tRCDCyc_freq2 = 0x2 <br /> tRTPCyc_freq2 = 0x4 <br /> tWRCyc_freq2 = 0x3 <br /> tWTRCyc_freq2 = 0x4 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_act_freq2(n) = 0x2008110f<br /> tFAWCyc_freq2 = 0x20 <br /> tRPCyc_freq2 = 0xf <br /> tRPabCyc_freq2 = 0x11 <br /> tRRDCyc_freq2 = 0x8 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_act_freq2(n) = 0x01020202<br /> tFAWCyc_freq2 = 0x1 <br /> tRPCyc_freq2 = 0x2 <br /> tRPabCyc_freq2 = 0x2 <br /> tRRDCyc_freq2 = 0x2 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_act_freq2(n) = 0x04020302<br /> tFAWCyc_freq2 = 0x4 <br /> tRPCyc_freq2 = 0x2 <br /> tRPabCyc_freq2 = 0x3 <br /> tRRDCyc_freq2 = 0x2 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq2(n) = 0x48900014<br /> tRFCBaseCyc_freq2 = 0x14 <br /> tRFCCyc_freq2 = 0x90 <br /> tRFCpbCyc_freq2 = 0x48 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq2(n) = 0x01010014<br /> tRFCBaseCyc_freq2 = 0x14 <br /> tRFCCyc_freq2 = 0x1 <br /> tRFCpbCyc_freq2 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq2(n) = 0x09120014<br /> tRFCBaseCyc_freq2 = 0x14 <br /> tRFCCyc_freq2 = 0x12 <br /> tRFCpbCyc_freq2 = 0x9 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_selfref_freq2(n) = 0xa0096012<br /> tFCCyc_freq2 = 0xa0 <br /> tXSRCyc_freq2 = 0x96 <br /> tZQCalCyc_freq2 = 0x12 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_selfref_freq2(n) = 0x28002012<br /> tFCCyc_freq2 = 0x28 <br /> tXSRCyc_freq2 = 0x2 <br /> tZQCalCyc_freq2 = 0x12 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_selfref_freq2(n) = 0x28013012<br /> tFCCyc_freq2 = 0x28 <br /> tXSRCyc_freq2 = 0x13 <br /> tZQCalCyc_freq2 = 0x12 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_caspch_freq3(n) = 0x40c20402<br /> tRASCyc_freq3 = 0x2 <br /> tRCDCyc_freq3 = 0x2 <br /> tRTPCyc_freq3 = 0x4 <br /> tWRCyc_freq3 = 0x3 <br /> tWTRCyc_freq3 = 0x4 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_caspch_freq3(n) = 0x40c20402<br /> tRASCyc_freq3 = 0x2 <br /> tRCDCyc_freq3 = 0x2 <br /> tRTPCyc_freq3 = 0x4 <br /> tWRCyc_freq3 = 0x3 <br /> tWTRCyc_freq3 = 0x4 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_caspch_freq3(n) = 0x40c20402<br /> tRASCyc_freq3 = 0x2 <br /> tRCDCyc_freq3 = 0x2 <br /> tRTPCyc_freq3 = 0x4 <br /> tWRCyc_freq3 = 0x3 <br /> tWTRCyc_freq3 = 0x4 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Process act_freq3 for all platforms </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_act_freq3(n) = 0x01020404<br /> tFAWCyc_freq3 = 0x1 <br /> tRPCyc_freq3 = 0x4 <br /> tRPabCyc_freq3 = 0x4 <br /> tRRDCyc_freq3 = 0x2 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_act_freq3(n) = 0x01020404<br /> tFAWCyc_freq3 = 0x1 <br /> tRPCyc_freq3 = 0x4 <br /> tRPabCyc_freq3 = 0x4 <br /> tRRDCyc_freq3 = 0x2 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_act_freq3(n) = 0x02020404<br /> tFAWCyc_freq3 = 0x2 <br /> tRPCyc_freq3 = 0x4 <br /> tRPabCyc_freq3 = 0x4 <br /> tRRDCyc_freq3 = 0x2 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq3(n) = 0x03050005<br /> tRFCBaseCyc_freq3 = 0x5 <br /> tRFCCyc_freq3 = 0x5 <br /> tRFCpbCyc_freq3 = 0x3 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq3(n) = 0x01010005<br /> tRFCBaseCyc_freq3 = 0x5 <br /> tRFCCyc_freq3 = 0x1 <br /> tRFCpbCyc_freq3 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq3(n) = 0x03050005<br /> tRFCBaseCyc_freq3 = 0x5 <br /> tRFCCyc_freq3 = 0x5 <br /> tRFCpbCyc_freq3 = 0x3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_selfref_freq3(n) = 0x28005012<br /> tFCCyc_freq3 = 0x28 <br /> tXSRCyc_freq3 = 0x5 <br /> tZQCalCyc_freq3 = 0x12 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_selfref_freq3(n) = 0x28002012<br /> tFCCyc_freq3 = 0x28 <br /> tXSRCyc_freq3 = 0x2 <br /> tZQCalCyc_freq3 = 0x12 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_selfref_freq3(n) = 0x28006012<br /> tFCCyc_freq3 = 0x28 <br /> tXSRCyc_freq3 = 0x6 <br /> tZQCalCyc_freq3 = 0x12 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_params(n) = 0x0015005d<br /> tREFBWtRFCcnt = 0x15 <br /> tREFICyc = 0x5d <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_params(n) = 0x00150013<br /> tREFBWtRFCcnt = 0x15 <br /> tREFICyc = 0x13 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_params(n) = 0x0015005d<br /> tREFBWtRFCcnt = 0x15 <br /> tREFICyc = 0x5d <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_pdn(n) = 0x612762c6<br /> tCKECyc = 0x6 <br /> tCKEPDECyc = 0x1 <br /> tCKESRCyc = 0xc <br /> tCKEafSRCyc = 0x2 <br /> tCKEb4SRCyc = 0x7 <br /> tCKafCKECyc = 0x6 <br /> tCKb4CKECyc = 0x1 <br /> tXPCyc = 0x6 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_pdn(n) = 0x21272222<br /> tCKECyc = 0x2 <br /> tCKEPDECyc = 0x1 <br /> tCKESRCyc = 0x2 <br /> tCKEafSRCyc = 0x2 <br /> tCKEb4SRCyc = 0x7 <br /> tCKafCKECyc = 0x2 <br /> tCKb4CKECyc = 0x1 <br /> tXPCyc = 0x2 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_pdn(n) = 0x722762c6<br /> tCKECyc = 0x6 <br /> tCKEPDECyc = 0x1 <br /> tCKESRCyc = 0xc <br /> tCKEafSRCyc = 0x2 <br /> tCKEb4SRCyc = 0x7 <br /> tCKafCKECyc = 0x7 <br /> tCKb4CKECyc = 0x2 <br /> tXPCyc = 0x6 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_derate_freq0(n) = 0x4d05a910<br /> tDQSCKMaxDrtCyc_freq0 = 0x5 <br /> tRASDrtCyc_freq0 = 0x24 <br /> tRCDDrtCyc_freq0 = 0x10 <br /> tRPDrtCyc_freq0 = 0x10 <br /> tRPabDrtCyc_freq0 = 0x13 <br /> tRRDDrtCyc_freq0 = 0xa <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_derate_freq0(n) = 0x08212082<br /> tDQSCKMaxDrtCyc_freq0 = 0x1 <br /> tRASDrtCyc_freq0 = 0x2 <br /> tRCDDrtCyc_freq0 = 0x2 <br /> tRPDrtCyc_freq0 = 0x2 <br /> tRPabDrtCyc_freq0 = 0x2 <br /> tRRDDrtCyc_freq0 = 0x2 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_derate_freq0(n) = 0x4d05a910<br /> tDQSCKMaxDrtCyc_freq0 = 0x5 <br /> tRASDrtCyc_freq0 = 0x24 <br /> tRCDDrtCyc_freq0 = 0x10 <br /> tRPDrtCyc_freq0 = 0x10 <br /> tRPabDrtCyc_freq0 = 0x13 <br /> tRRDDrtCyc_freq0 = 0xa <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_derate_freq1(n) = 0x4d05a910<br /> tDQSCKMaxDrtCyc_freq1 = 0x5 <br /> tRASDrtCyc_freq1 = 0x24 <br /> tRCDDrtCyc_freq1 = 0x10 <br /> tRPDrtCyc_freq1 = 0x10 <br /> tRPabDrtCyc_freq1 = 0x13 <br /> tRRDDrtCyc_freq1 = 0xa <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_derate_freq1(n) = 0x08212082<br /> tDQSCKMaxDrtCyc_freq1 = 0x1 <br /> tRASDrtCyc_freq1 = 0x2 <br /> tRCDDrtCyc_freq1 = 0x2 <br /> tRPDrtCyc_freq1 = 0x2 <br /> tRPabDrtCyc_freq1 = 0x2 <br /> tRRDDrtCyc_freq1 = 0x2 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_derate_freq1(n) = 0x28835488<br /> tDQSCKMaxDrtCyc_freq1 = 0x3 <br /> tRASDrtCyc_freq1 = 0x12 <br /> tRCDDrtCyc_freq1 = 0x8 <br /> tRPDrtCyc_freq1 = 0x8 <br /> tRPabDrtCyc_freq1 = 0xa <br /> tRRDDrtCyc_freq1 = 0x5 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_derate_freq2(n) = 0x4d05a910<br /> tDQSCKMaxDrtCyc_freq2 = 0x5 <br /> tRASDrtCyc_freq2 = 0x24 <br /> tRCDDrtCyc_freq2 = 0x10 <br /> tRPDrtCyc_freq2 = 0x10 <br /> tRPabDrtCyc_freq2 = 0x13 <br /> tRRDDrtCyc_freq2 = 0xa <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_derate_freq2(n) = 0x08212082<br /> tDQSCKMaxDrtCyc_freq2 = 0x1 <br /> tRASDrtCyc_freq2 = 0x2 <br /> tRCDDrtCyc_freq2 = 0x2 <br /> tRPDrtCyc_freq2 = 0x2 <br /> tRPabDrtCyc_freq2 = 0x2 <br /> tRRDDrtCyc_freq2 = 0x2 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_derate_freq2(n) = 0x0c212142<br /> tDQSCKMaxDrtCyc_freq2 = 0x1 <br /> tRASDrtCyc_freq2 = 0x5 <br /> tRCDDrtCyc_freq2 = 0x2 <br /> tRPDrtCyc_freq2 = 0x2 <br /> tRPabDrtCyc_freq2 = 0x3 <br /> tRRDDrtCyc_freq2 = 0x2 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_derate_freq3(n) = 0x10412082<br /> tDQSCKMaxDrtCyc_freq3 = 0x1 <br /> tRASDrtCyc_freq3 = 0x2 <br /> tRCDDrtCyc_freq3 = 0x2 <br /> tRPDrtCyc_freq3 = 0x4 <br /> tRPabDrtCyc_freq3 = 0x4 <br /> tRRDDrtCyc_freq3 = 0x2 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_derate_freq3(n) = 0x10412082<br /> tDQSCKMaxDrtCyc_freq3 = 0x1 <br /> tRASDrtCyc_freq3 = 0x2 <br /> tRCDDrtCyc_freq3 = 0x2 <br /> tRPDrtCyc_freq3 = 0x4 <br /> tRPabDrtCyc_freq3 = 0x4 <br /> tRRDDrtCyc_freq3 = 0x2 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_derate_freq3(n) = 0x10412082<br /> tDQSCKMaxDrtCyc_freq3 = 0x1 <br /> tRASDrtCyc_freq3 = 0x2 <br /> tRCDDrtCyc_freq3 = 0x2 <br /> tRPDrtCyc_freq3 = 0x4 <br /> tRPabDrtCyc_freq3 = 0x4 <br /> tRRDDrtCyc_freq3 = 0x2 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_lat_freq0(n) = 0x00123387<br /> DRAMRL_freq0 = 0xe <br /> DRAMWL_freq0 = 0x7 <br /> tDQSCKMaxCyc_freq0 = 0x3 <br /> tDQSCKMinCyc_freq0 = 0x2 <br /> tDQSSMaxCyc_freq0 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_lat_freq0(n) = 0x001110c2<br /> DRAMRL_freq0 = 0x3 <br /> DRAMWL_freq0 = 0x2 <br /> tDQSCKMaxCyc_freq0 = 0x1 <br /> tDQSCKMinCyc_freq0 = 0x1 <br /> tDQSSMaxCyc_freq0 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_lat_freq0(n) = 0x00123387<br /> DRAMRL_freq0 = 0xe <br /> DRAMWL_freq0 = 0x7 <br /> tDQSCKMaxCyc_freq0 = 0x3 <br /> tDQSCKMinCyc_freq0 = 0x2 <br /> tDQSSMaxCyc_freq0 = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_lat_freq1(n) = 0x00123206<br /> DRAMRL_freq1 = 0x8 <br /> DRAMWL_freq1 = 0x6 <br /> tDQSCKMaxCyc_freq1 = 0x3 <br /> tDQSCKMinCyc_freq1 = 0x2 <br /> tDQSSMaxCyc_freq1 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_lat_freq1(n) = 0x001110c2<br /> DRAMRL_freq1 = 0x3 <br /> DRAMWL_freq1 = 0x2 <br /> tDQSCKMaxCyc_freq1 = 0x1 <br /> tDQSCKMinCyc_freq1 = 0x1 <br /> tDQSSMaxCyc_freq1 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_lat_freq1(n) = 0x00112206<br /> DRAMRL_freq1 = 0x8 <br /> DRAMWL_freq1 = 0x6 <br /> tDQSCKMaxCyc_freq1 = 0x2 <br /> tDQSCKMinCyc_freq1 = 0x1 <br /> tDQSSMaxCyc_freq1 = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_lat_freq2(n) = 0x001230c2<br /> DRAMRL_freq2 = 0x3 <br /> DRAMWL_freq2 = 0x2 <br /> tDQSCKMaxCyc_freq2 = 0x3 <br /> tDQSCKMinCyc_freq2 = 0x2 <br /> tDQSSMaxCyc_freq2 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_lat_freq2(n) = 0x001110c2<br /> DRAMRL_freq2 = 0x3 <br /> DRAMWL_freq2 = 0x2 <br /> tDQSCKMaxCyc_freq2 = 0x1 <br /> tDQSCKMinCyc_freq2 = 0x1 <br /> tDQSSMaxCyc_freq2 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_lat_freq2(n) = 0x001110c2<br /> DRAMRL_freq2 = 0x3 <br /> DRAMWL_freq2 = 0x2 <br /> tDQSCKMaxCyc_freq2 = 0x1 <br /> tDQSCKMinCyc_freq2 = 0x1 <br /> tDQSSMaxCyc_freq2 = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_lat_freq3(n) = 0x001110c2<br /> DRAMRL_freq3 = 0x3 <br /> DRAMWL_freq3 = 0x2 <br /> tDQSCKMaxCyc_freq3 = 0x1 <br /> tDQSCKMinCyc_freq3 = 0x1 <br /> tDQSSMaxCyc_freq3 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_lat_freq3(n) = 0x001110c2<br /> DRAMRL_freq3 = 0x3 <br /> DRAMWL_freq3 = 0x2 <br /> tDQSCKMaxCyc_freq3 = 0x1 <br /> tDQSCKMinCyc_freq3 = 0x1 <br /> tDQSSMaxCyc_freq3 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_lat_freq3(n) = 0x001110c2<br /> DRAMRL_freq3 = 0x3 <br /> DRAMWL_freq3 = 0x2 <br /> tDQSCKMaxCyc_freq3 = 0x1 <br /> tDQSCKMinCyc_freq3 = 0x1 <br /> tDQSSMaxCyc_freq3 = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_tat_freq0(n) = 0x01412222<br /> R2rRnkMissTatDeadCyc_freq0 = 0x2 <br /> R2rTatDeadCyc_freq0 = 0x1 <br /> R2wRnkMissTatDeadCyc_freq0 = 0x2 <br /> R2wTatDeadCyc_freq0 = 0x4 <br /> W2rRnkMissTatDeadCyc_freq0 = 0x2 <br /> W2wRnkMissTatDeadCyc_freq0 = 0x2 <br /> W2wTatDeadCyc_freq0 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_tat_freq0(n) = 0x01212222<br /> R2rRnkMissTatDeadCyc_freq0 = 0x2 <br /> R2rTatDeadCyc_freq0 = 0x1 <br /> R2wRnkMissTatDeadCyc_freq0 = 0x2 <br /> R2wTatDeadCyc_freq0 = 0x2 <br /> W2rRnkMissTatDeadCyc_freq0 = 0x2 <br /> W2wRnkMissTatDeadCyc_freq0 = 0x2 <br /> W2wTatDeadCyc_freq0 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_tat_freq0(n) = 0x01412222<br /> R2rRnkMissTatDeadCyc_freq0 = 0x2 <br /> R2rTatDeadCyc_freq0 = 0x1 <br /> R2wRnkMissTatDeadCyc_freq0 = 0x2 <br /> R2wTatDeadCyc_freq0 = 0x4 <br /> W2rRnkMissTatDeadCyc_freq0 = 0x2 <br /> W2wRnkMissTatDeadCyc_freq0 = 0x2 <br /> W2wTatDeadCyc_freq0 = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_tat_freq1(n) = 0x01412222<br /> R2rRnkMissTatDeadCyc_freq1 = 0x2 <br /> R2rTatDeadCyc_freq1 = 0x1 <br /> R2wRnkMissTatDeadCyc_freq1 = 0x2 <br /> R2wTatDeadCyc_freq1 = 0x4 <br /> W2rRnkMissTatDeadCyc_freq1 = 0x2 <br /> W2wRnkMissTatDeadCyc_freq1 = 0x2 <br /> W2wTatDeadCyc_freq1 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_tat_freq1(n) = 0x01212222<br /> R2rRnkMissTatDeadCyc_freq1 = 0x2 <br /> R2rTatDeadCyc_freq1 = 0x1 <br /> R2wRnkMissTatDeadCyc_freq1 = 0x2 <br /> R2wTatDeadCyc_freq1 = 0x2 <br /> W2rRnkMissTatDeadCyc_freq1 = 0x2 <br /> W2wRnkMissTatDeadCyc_freq1 = 0x2 <br /> W2wTatDeadCyc_freq1 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_tat_freq1(n) = 0x01312222<br /> R2rRnkMissTatDeadCyc_freq1 = 0x2 <br /> R2rTatDeadCyc_freq1 = 0x1 <br /> R2wRnkMissTatDeadCyc_freq1 = 0x2 <br /> R2wTatDeadCyc_freq1 = 0x3 <br /> W2rRnkMissTatDeadCyc_freq1 = 0x2 <br /> W2wRnkMissTatDeadCyc_freq1 = 0x2 <br /> W2wTatDeadCyc_freq1 = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_tat_freq2(n) = 0x01412222<br /> R2rRnkMissTatDeadCyc_freq2 = 0x2 <br /> R2rTatDeadCyc_freq2 = 0x1 <br /> R2wRnkMissTatDeadCyc_freq2 = 0x2 <br /> R2wTatDeadCyc_freq2 = 0x4 <br /> W2rRnkMissTatDeadCyc_freq2 = 0x2 <br /> W2wRnkMissTatDeadCyc_freq2 = 0x2 <br /> W2wTatDeadCyc_freq2 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_tat_freq2(n) = 0x01212222<br /> R2rRnkMissTatDeadCyc_freq2 = 0x2 <br /> R2rTatDeadCyc_freq2 = 0x1 <br /> R2wRnkMissTatDeadCyc_freq2 = 0x2 <br /> R2wTatDeadCyc_freq2 = 0x2 <br /> W2rRnkMissTatDeadCyc_freq2 = 0x2 <br /> W2wRnkMissTatDeadCyc_freq2 = 0x2 <br /> W2wTatDeadCyc_freq2 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_tat_freq2(n) = 0x01212222<br /> R2rRnkMissTatDeadCyc_freq2 = 0x2 <br /> R2rTatDeadCyc_freq2 = 0x1 <br /> R2wRnkMissTatDeadCyc_freq2 = 0x2 <br /> R2wTatDeadCyc_freq2 = 0x2 <br /> W2rRnkMissTatDeadCyc_freq2 = 0x2 <br /> W2wRnkMissTatDeadCyc_freq2 = 0x2 <br /> W2wTatDeadCyc_freq2 = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_rnkcfg(n) = 0x00006061<br /> Rnk0Odts = 0x6 *read-only<br /> Rnk0Valid = 0x1 <br /> Rnk1Odts = 0x6 *read-only<br /> Rnk1Valid = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_mifqctrl_mifqmaxctrl_freq0(n) = 0x00000100<br /> HiTempMifQMax_freq0 = 0x0 <br /> MifQMaxAlways = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_mifqctrl_mifqmaxctrl_freq3(n) = 0x00000003<br /> HiTempMifQMax_freq3 = 0x3 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_mifqctrl_mifqmaxctrl_freq3(n) = 0x00000001<br /> HiTempMifQMax_freq3 = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn off optional power- savingfeatures. This includes dynamic power down, auto self-refresh entry, and clock stopping. </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_pwrmngten(n) = 0x00000000<br /> AutoSR = 0x0 <br /> DynPwrDnEn = 0x0 <br /> McPhyUpdDramClkOff = 0x0 <br /> PwrDnClkOff = 0x0 <br /> SRClkOff = 0x0 <br /> SRExitOpt = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn off optional power- savingfeatures. This includes dynamic power down, auto self-refresh entry, and clock stopping. </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_odtszqc(n) = 0x00002000<br /> DerateParamSRExit = 0x1 <br /> OdtsRdIntrvl = 0x0 <br /> SRExitZQCChnlQuiet = 0x0 <br /> ShareZQRes = 0x0 <br /> TempDrtEn = 0x0 <br /> ZQCChnlQuiet = 0x0 <br /> ZQCStack = 0x0 <br /> ZqCalIntrvl = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn off transaction scheduling for non- initialization commands </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_amcgen_amcctrl(n) = 0x00000002<br /> McuEn = 0x0 <br /> SchEn = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program AMC to <br /> - wait tXP+2tCK after actual clock changes before valid command<br /> - wait 2 cycles after all timing parameter are satisfied before actual clock change<br /> - wait indefinitely for AMP to complete handshake. </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_mcphyupdtparam(n) = 0x15030000<br /> FreqCSettleCyc = 0x5 <br /> McPhyTimeParamCyc = 0x3 <br /> PhyInitStartCyc = 0x0 <br /> PhyUpdMDLL = 0x1 <br /> UpdPhyLatCyc = 0x0 <br /> tPhyUpdGap = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
|
|
<h4>2. AMP Initial Configurations</h4>
|
|
<p>Perform the proper configurations of the AMP. There are two separate AMP register blocks; the code below must be repeated on both AMP0 and AMP1. (N=0..1)<br /> </p>
|
|
<table class="section">
|
|
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
|
|
</tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DCC_BYPCK(n) = 0x00003f3f<br /> ck_bypass = 0x0 <br /> ck_bypn = 0x3f <br /> ck_bypp = 0x3f <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DCC_BYPCS(n) = 0x00003f3f<br /> cs_bypass = 0x0 <br /> cs_bypn = 0x3f <br /> cs_bypp = 0x3f <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DCC_BYPB0(n) = 0x00003f3f<br /> b0_bypass = 0x0 <br /> b0_bypn = 0x3f <br /> b0_bypp = 0x3f <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DCC_BYPDQS0(n) = 0x00003f3f<br /> dqs0_bypass = 0x0 <br /> dqs0_bypn = 0x3f <br /> dqs0_bypp = 0x3f <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DCC_BYPB1(n) = 0x00003f3f<br /> b1_bypass = 0x0 <br /> b1_bypn = 0x3f <br /> b1_bypp = 0x3f <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DCC_BYPDQS1(n) = 0x00003f3f<br /> dqs1_bypass = 0x0 <br /> dqs1_bypn = 0x3f <br /> dqs1_bypp = 0x3f <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DCC_BYPCA(n) = 0x00003f3f<br /> ca_bypass = 0x0 <br /> ca_bypn = 0x3f <br /> ca_bypp = 0x3f <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DCC_BYPCK(n) = 0x00013f3f<br /> ck_bypass = 0x1 <br /> ck_bypn = 0x3f <br /> ck_bypp = 0x3f <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DCC_BYPCS(n) = 0x00013f3f<br /> cs_bypass = 0x1 <br /> cs_bypn = 0x3f <br /> cs_bypp = 0x3f <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DCC_BYPB0(n) = 0x00013f3f<br /> b0_bypass = 0x1 <br /> b0_bypn = 0x3f <br /> b0_bypp = 0x3f <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DCC_BYPDQS0(n) = 0x00013f3f<br /> dqs0_bypass = 0x1 <br /> dqs0_bypn = 0x3f <br /> dqs0_bypp = 0x3f <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DCC_BYPB1(n) = 0x00013f3f<br /> b1_bypass = 0x1 <br /> b1_bypn = 0x3f <br /> b1_bypp = 0x3f <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DCC_BYPDQS1(n) = 0x00013f3f<br /> dqs1_bypass = 0x1 <br /> dqs1_bypn = 0x3f <br /> dqs1_bypp = 0x3f <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DCC_BYPCA(n) = 0x00013f3f<br /> ca_bypass = 0x1 <br /> ca_bypn = 0x3f <br /> ca_bypp = 0x3f <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Assert AMP enable </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscagen_ampen(n) = 0x00000001<br /> AmpEn = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Assert AMP enable </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqgen_ampen(n) = 0x00000001<br /> AmpEn = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaodt_VRef_f0(n) = 0x00000003<br /> VRefSel = 0x3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaodt_VRef_f1(n) = 0x00000003<br /> VRefSel = 0x3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaodt_VRef_f2(n) = 0x00000003<br /> VRefSel = 0x3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaodt_VRef_f3(n) = 0x00000003<br /> VRefSel = 0x3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > ODTEnable_f0 </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> ampsca_ampscaodt_ODTEnable_f0(n) = 0x00000000<br /> ODTEnable = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> ampsca_ampscaodt_ODTEnable_f0(n) = 0x00000000<br /> ODTEnable = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> ampsca_ampscaodt_ODTEnable_f0(n) = 0x00000001<br /> ODTEnable = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > ODTEnable_f1 </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> ampsca_ampscaodt_ODTEnable_f1(n) = 0x00000000<br /> ODTEnable = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> ampsca_ampscaodt_ODTEnable_f1(n) = 0x00000000<br /> ODTEnable = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> ampsca_ampscaodt_ODTEnable_f1(n) = 0x00000001<br /> ODTEnable = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > ODTEnable_f3 </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaodt_ODTEnable_f3(n) = 0x00000000<br /> ODTEnable = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqodt_VRef_f0(n) = 0x00c000c0<br /> DqsVRefSel = 0xc0 <br /> VRefSel = 0xc0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqodt_VRef_f1(n) = 0x00c000c0<br /> DqsVRefSel = 0xc0 <br /> VRefSel = 0xc0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscasdllctrl_SDLLUpdateCtrl(n) = 0x03030305<br /> ClkEn2Valid = 0x3 <br /> ReqWaitDelay = 0x5 <br /> Valid2ClkEn = 0x3 <br /> ValidLen = 0x3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqsdllctrl_SDLLUpdateCtrl(n) = 0x00030005<br /> ClkEn2Valid = 0x0 <br /> ReqWaitDelay = 0x5 <br /> Valid2ClkEn = 0x0 <br /> ValidLen = 0x3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqsdllctrl_rd0sdllctrl(n) = 0x00ff0002<br /> Rd0RunSDLLUpd = 0x0 <br /> Rd0RunSDLLUpdOverride = 0x1 <br /> Rd0RunSDLLUpdWrResult = 0x0 <br /> Rd0SDLLOvrVal = 0xff <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll ampsdqsdllctrl rd0sdllctrl </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: ampsdqsdllctrl_rd0sdllctrl<br />
|
|
Rd0RunSDLLUpdOverride<br />
|
|
while((CSR(ampsdq_ampsdqsdllctrl_rd0sdllctrl(n)) & 0x2) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqsdllctrl_rd0sdllctrl(n) = 0x00ff0000<br /> Rd0RunSDLLUpd = 0x0 <br /> Rd0RunSDLLUpdOverride = 0x0 <br /> Rd0RunSDLLUpdWrResult = 0x0 <br /> Rd0SDLLOvrVal = 0xff <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n) = 0xff000002<br /> WrDqDqsRunSDLLUpd = 0x0 <br /> WrDqDqsRunSDLLUpdOverride = 0x1 <br /> WrDqDqsRunSDLLUpdWrResult = 0x0 <br /> WrDqDqsWrLvlReBalanceEn = 0x0 <br /> WrDqSDLLAddHalfClk_f0 = 0x0 <br /> WrDqSDLLAddHalfClk_f1 = 0x0 <br /> WrDqSDLLAddHalfClk_f2 = 0x0 <br /> WrDqSDLLAddHalfClk_f3 = 0x0 <br /> WrDqSDLLHalfClkEn = 0x0 <br /> WrDqSDLLHalfClkOvrVal = 0x0 <br /> WrDqSDLLHalfClkStatus = 0x0 *read-only<br /> WrDqSDLLOvrVal = 0x0 <br /> WrDqsSDLLOvrVal = 0xff <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll ampsdqsdllctrl WrDqDqsSDLLCtrl </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: ampsdqsdllctrl_WrDqDqsSDLLCtrl<br />
|
|
WrDqDqsRunSDLLUpdOverride<br />
|
|
while((CSR(ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n)) & 0x2) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n) = 0xff000000<br /> WrDqDqsRunSDLLUpd = 0x0 <br /> WrDqDqsRunSDLLUpdOverride = 0x0 <br /> WrDqDqsRunSDLLUpdWrResult = 0x0 <br /> WrDqDqsWrLvlReBalanceEn = 0x0 <br /> WrDqSDLLAddHalfClk_f0 = 0x0 <br /> WrDqSDLLAddHalfClk_f1 = 0x0 <br /> WrDqSDLLAddHalfClk_f2 = 0x0 <br /> WrDqSDLLAddHalfClk_f3 = 0x0 <br /> WrDqSDLLHalfClkEn = 0x0 <br /> WrDqSDLLHalfClkOvrVal = 0x0 <br /> WrDqSDLLHalfClkStatus = 0x0 *read-only<br /> WrDqSDLLOvrVal = 0x0 <br /> WrDqsSDLLOvrVal = 0xff <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscawrlvl_ampcawrlvlsdllcode(n) = 0x00ff01ff<br /> WrLvlMaxWrDqsSDLLCode = 0xff <br /> WrLvlRunUpdOverride = 0x1 <br /> WrLvlRunUpdWrResult = 0x0 <br /> WrLvlSDLLCode = 0xff <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll ampscawrlvl ampcawrlvlsdllcode </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: ampscawrlvl_ampcawrlvlsdllcode<br />
|
|
WrLvlRunUpdOverride<br />
|
|
while((CSR(ampsca_ampscawrlvl_ampcawrlvlsdllcode(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscawrlvl_ampcawrlvlsdllcode(n) = 0x00ff00ff<br /> WrLvlMaxWrDqsSDLLCode = 0xff <br /> WrLvlRunUpdOverride = 0x0 <br /> WrLvlRunUpdWrResult = 0x0 <br /> WrLvlSDLLCode = 0xff <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL Init and Incr lock timers based on 24 MHz value<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscadllctl_dlllocktim(n) = 0x00c801f4<br /> DllIncLockTim = 0xc8 <br /> DllInitLockTim = 0x1f4 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL Init and Incr lock timers based on 24 MHz value<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqdllctl_dlllocktim(n) = 0x00c801f4<br /> DllIncLockTim = 0xc8 <br /> DllInitLockTim = 0x1f4 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_DFICalTiming2_DFICalTiming_f1(n) = 0x04000410<br /> tCA2CAEntry_f1 = 0x10 <br /> tCA2CAExit_f1 = 0x0 <br /> tCKEHEntry_f1 = 0x4 <br /> tCKEHExit_f1 = 0x4 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_DFICalTiming2_DFICalTiming_f2(n) = 0x04000410<br /> tCA2CAEntry_f2 = 0x10 <br /> tCA2CAExit_f2 = 0x0 <br /> tCKEHEntry_f2 = 0x4 <br /> tCKEHExit_f2 = 0x4 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_DFICalTiming2_DFICalTiming_f3(n) = 0x04000410<br /> tCA2CAEntry_f3 = 0x10 <br /> tCA2CAExit_f3 = 0x0 <br /> tCKEHEntry_f3 = 0x4 <br /> tCKEHExit_f3 = 0x4 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_DFICalTiming_DFICalTiming_f0(n) = 0x06020404<br /> tCA2CAEntry_f0 = 0x4 <br /> tCA2CAExit_f0 = 0x2 <br /> tCKEHEntry_f0 = 0x4 <br /> tCKEHExit_f0 = 0x6 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_DFICalTiming_DFICalTiming_f1(n) = 0x04020402<br /> tCA2CAEntry_f1 = 0x2 <br /> tCA2CAExit_f1 = 0x2 <br /> tCKEHEntry_f1 = 0x4 <br /> tCKEHExit_f1 = 0x4 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_DFICalTiming_DFICalTiming_f2(n) = 0x04020402<br /> tCA2CAEntry_f2 = 0x2 <br /> tCA2CAExit_f2 = 0x2 <br /> tCKEHEntry_f2 = 0x4 <br /> tCKEHExit_f2 = 0x4 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_DFICalTiming_DFICalTiming_f3(n) = 0x04020404<br /> tCA2CAEntry_f3 = 0x4 <br /> tCA2CAExit_f3 = 0x2 <br /> tCKEHEntry_f3 = 0x4 <br /> tCKEHExit_f3 = 0x4 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqdllctl_MDLLCodeCaptureControl(n) = 0x00000002<br /> MDLLLoopCnt = 0x2 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_RdWrDqCalTiming_f0(n) = 0x01040508<br /> CoarseStepSize = 0x4 <br /> FineStepSize = 0x1 <br /> tRL = 0x8 <br /> tWL = 0x5 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_RdWrDqCalSegLen_f0(n) = 0x000c0012<br /> tRdDqCalSegLen = 0x12 <br /> tWrDqCalSegLen = 0xc <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_RdWrDqCalTiming_f1(n) = 0x01040402<br /> CoarseStepSize = 0x4 <br /> FineStepSize = 0x1 <br /> tRL = 0x2 <br /> tWL = 0x4 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_RdWrDqCalTiming_f3(n) = 0x01040508<br /> CoarseStepSize = 0x4 <br /> FineStepSize = 0x1 <br /> tRL = 0x8 <br /> tWL = 0x5 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_RdWrDqCalSegLen_f1(n) = 0x000c0012<br /> tRdDqCalSegLen = 0x12 <br /> tWrDqCalSegLen = 0xc <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWRdWrDqCalTimingCtrl1(n) = 0x0000381e<br /> tRd2SDLL = 0x0 <br /> tSDLL2Rd = 0x1e <br /> tSDLL2Wr = 0x38 <br /> tWr2SDLL = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWRdWrDqCalTimingCtrl2(n) = 0x01141101<br /> tRd2Rd = 0x1 <br /> tRd2Wr = 0x11 <br /> tWr2Rd = 0x14 <br /> tWr2Wr = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWRdDqCalPatPRBS4I(n) = 0x55553c5a<br /> PatInvertMask = 0x5555 <br /> PatPRBS4 = 0x3c5a <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWWrDqCalPatPRBS4I(n) = 0x00003c5a<br /> PatInvertMask = 0x0 <br /> PatPRBS4 = 0x3c5a <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWWrDqCalPatPRBS7_0(n) = 0x87654321<br /> PatPRBS7 = 0x87654321 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWWrDqCalPatPRBS7_1(n) = 0xcdedcba9<br /> PatPRBS7 = 0xcdedcba9 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWWrDqCalPatPRBS7_2(n) = 0x456789ab<br /> PatPRBS7 = 0x456789ab <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWWrDqCalPatPRBS7_3(n) = 0x5fa63123<br /> PatPRBS7 = 0x5fa63123 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWWrDqCalPatInvertMask(n) = 0x55550000<br /> PatInvertMask = 0x5555 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_RdDqCalWindow_f0(n) = 0x00ff01d1<br /> EndPoint = 0xff <br /> StartPoint = 0x1d1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_WrDqCalWindow_f0(n) = 0x00ff0160<br /> EndPoint = 0xff <br /> StartPoint = 0x160 *read-only<br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_RdDqCalWindow_f1(n) = 0x00ff01d1<br /> EndPoint = 0xff <br /> StartPoint = 0x1d1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_WrDqCalWindow_f1(n) = 0x00ff0160<br /> EndPoint = 0xff <br /> StartPoint = 0x160 *read-only<br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_MaxRdDqsSDLLMulFactor(n) = 0x00a01414<br /> MaxRdDqsSDLLCodeStatus = 0xa0 *read-only<br /> RdDqsSDLLMulFactorF0 = 0x14 <br /> RdDqsSDLLMulFactorF1 = 0x14 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_MaxWrDqsSDLLMulFactor(n) = 0xa0a00c0d<br /> MaxWrDqsSDLLCodeStatusF0 = 0xa0 *read-only<br /> MaxWrDqsSDLLCodeStatusF1 = 0xa0 *read-only<br /> WrDqsSDLLMulFactorF0 = 0xd <br /> WrDqsSDLLMulFactorF1 = 0xc <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqMulFactor_RdDqsMulFactor(n) = 0x20181000<br /> Factor0 = 0x0 <br /> Factor1 = 0x10 <br /> Factor2 = 0x18 <br /> Factor3 = 0x20 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program capture latency and recapture latency </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> ampsdq_ampsdqrdtim_rdcapcfg_freq0(n) = 0x01000606<br /> DqIeDeAssertPullIn_f0 = 0x0 <br /> DqsPdEn_f0 = 0x1 <br /> RdCapLat_f0 = 0x6 <br /> RdDatLat_f0 = 0x6 <br /> WrPhaseDelay_f0 = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> ampsdq_ampsdqrdtim_rdcapcfg_freq0(n) = 0x01000810<br /> DqIeDeAssertPullIn_f0 = 0x0 <br /> DqsPdEn_f0 = 0x1 <br /> RdCapLat_f0 = 0x10 <br /> RdDatLat_f0 = 0x8 <br /> WrPhaseDelay_f0 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program capture latency and recapture latency </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> ampsdq_ampsdqrdtim_rdcapcfg_freq1(n) = 0x21000606<br /> DqIeDeAssertPullIn_f1 = 0x2 <br /> DqsPdEn_f1 = 0x1 <br /> RdCapLat_f1 = 0x6 <br /> RdDatLat_f1 = 0x6 <br /> WrPhaseDelay_f1 = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> ampsdq_ampsdqrdtim_rdcapcfg_freq1(n) = 0x2100060a<br /> DqIeDeAssertPullIn_f1 = 0x2 <br /> DqsPdEn_f1 = 0x1 <br /> RdCapLat_f1 = 0xa <br /> RdDatLat_f1 = 0x6 <br /> WrPhaseDelay_f1 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program capture latency and recapture latency </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> ampsdq_ampsdqrdtim_rdcapcfg_freq2(n) = 0x41000606<br /> DqIeDeAssertPullIn_f2 = 0x4 <br /> DqsPdEn_f2 = 0x1 <br /> RdCapLat_f2 = 0x6 <br /> RdDatLat_f2 = 0x6 <br /> WrPhaseDelay_f2 = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> ampsdq_ampsdqrdtim_rdcapcfg_freq2(n) = 0x41000408<br /> DqIeDeAssertPullIn_f2 = 0x4 <br /> DqsPdEn_f2 = 0x1 <br /> RdCapLat_f2 = 0x8 <br /> RdDatLat_f2 = 0x4 <br /> WrPhaseDelay_f2 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program capture latency and recapture latency </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> ampsdq_ampsdqrdtim_rdcapcfg_freq3(n) = 0x61000606<br /> DqIeDeAssertPullIn_f3 = 0x6 <br /> DqsPdEn_f3 = 0x1 <br /> RdCapLat_f3 = 0x6 <br /> RdDatLat_f3 = 0x6 <br /> WrPhaseDelay_f3 = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> ampsdq_ampsdqrdtim_rdcapcfg_freq3(n) = 0x61000408<br /> DqIeDeAssertPullIn_f3 = 0x6 <br /> DqsPdEn_f3 = 0x1 <br /> RdCapLat_f3 = 0x8 <br /> RdDatLat_f3 = 0x4 <br /> WrPhaseDelay_f3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Updating the programming of DLL*UpdtDur Fields<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscadllctl_dllupdtctrl(n) = 0x80017580<br /> DllInitUpdtDur = 0x7 <br /> DllUpdtDur = 0x5 <br /> DllUpdtMode = 0x1 <br /> DllUpdtPhyUpdtTyp = 0x0 <br /> FreqChangeSDLLUpdDur = 0x80 <br /> SDLLUpdDur = 0x80 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Updating the programming of DLL*UpdtDur Fields<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqdllctl_dllupdtctrl(n) = 0x80017580<br /> DllInitUpdtDur = 0x7 <br /> DllUpdtDur = 0x5 <br /> DllUpdtMode = 0x1 <br /> DllUpdtPhyUpdtTyp = 0x0 <br /> FreqChangeSDLLUpdDur = 0x80 <br /> SDLLUpdDur = 0x80 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscadllctl_dllupdtintvl(n) = 0x10200020<br /> DllFastUpdtAlwaysON = 0x1 <br /> DllFastUpdtIntvl = 0x20 <br /> DllUpdtAlwaysON = 0x0 <br /> DllUpdtIntvl = 0x20 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqdllctl_dllupdtintvl(n) = 0x10200020<br /> DllFastUpdtAlwaysON = 0x1 <br /> DllFastUpdtIntvl = 0x20 <br /> DllUpdtAlwaysON = 0x0 <br /> DllUpdtIntvl = 0x20 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable DLL </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqdllctl_dllen(n) = 0x00000100<br /> DLLEn = 0x1 <br /> MDllReset = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaiocfg_DCCControl(n) = 0x10050b27<br /> DCCEnable = 0x1 <br /> DCCIdle1Len = 0x27 <br /> DCCIdle2Len = 0x5 <br /> DCCStopClk2Upd = 0x0 <br /> DCCUpdLen = 0xb <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaiocfg_DCCTimer(n) = 0x00000190<br /> DCCTimer = 0x190 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWWrDqCalDynamicHalfClkDelayControl(n) = 0x00000001<br /> DynamicHalfClkDelayEn = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_CB_WKPUPD(n) = 0x00000000<br /> pdpwk_f0 = 0x0 <br /> pdpwk_f1 = 0x0 <br /> pdpwk_f2 = 0x0 <br /> pdpwk_f3 = 0x0 <br /> pupwk_f0 = 0x0 <br /> pupwk_f1 = 0x0 <br /> pupwk_f2 = 0x0 <br /> pupwk_f3 = 0x0 <br /> wkds = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_CB_DRIVE_STR(n) = 0x33838317<br /> dspd_f0 = 0x7 <br /> dspd_f1 = 0x3 <br /> dspd_f2 = 0x3 <br /> dspd_f3 = 0x3 <br /> dspu_f0 = 0x1 <br /> dspu_f1 = 0x8 <br /> dspu_f2 = 0x8 <br /> dspu_f3 = 0x3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_CB_IOCTL(n) = 0x00020023<br /> en_pulse_tx_f0 = 0x1 <br /> en_pulse_tx_f1 = 0x1 <br /> en_pulse_tx_f2 = 0x0 <br /> en_pulse_tx_f3 = 0x0 <br /> isel = 0x0 <br /> protect_drvstren = 0x1 <br /> sel_rx_ac = 0x0 <br /> sel_rx_dc = 0x0 <br /> tx_ac_f0 = 0x2 <br /> tx_ac_f1 = 0x0 <br /> tx_ac_f2 = 0x0 <br /> tx_ac_f3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_CK_WKPUPD(n) = 0x00000000<br /> pdpwk_f0 = 0x0 <br /> pdpwk_f1 = 0x0 <br /> pdpwk_f2 = 0x0 <br /> pdpwk_f3 = 0x0 <br /> pupwk_f0 = 0x0 <br /> pupwk_f1 = 0x0 <br /> pupwk_f2 = 0x0 <br /> pupwk_f3 = 0x0 <br /> wkds = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_CK_ZDET_BIASEN(n) = 0x00000000<br /> bias_ena = 0x0 <br /> disable_zdet = 0x0 <br /> sel_zdet = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_CK_DRIVE_STR(n) = 0x33838317<br /> dspd_f0 = 0x7 <br /> dspd_f1 = 0x3 <br /> dspd_f2 = 0x3 <br /> dspd_f3 = 0x3 <br /> dspu_f0 = 0x1 <br /> dspu_f1 = 0x8 <br /> dspu_f2 = 0x8 <br /> dspu_f3 = 0x3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_CK_IOCTL(n) = 0x00000027<br /> en_pulse_tx_f0 = 0x1 <br /> en_pulse_tx_f1 = 0x1 <br /> en_pulse_tx_f2 = 0x1 <br /> en_pulse_tx_f3 = 0x0 <br /> isel = 0x0 <br /> sel_rx_ac = 0x0 <br /> sel_rx_dc = 0x0 <br /> tx_ac_f0 = 0x2 <br /> tx_ac_f1 = 0x0 <br /> tx_ac_f2 = 0x0 <br /> tx_ac_f3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_B0_DRIVE_STR(n) = 0x33838317<br /> dspd_f0 = 0x7 <br /> dspd_f1 = 0x3 <br /> dspd_f2 = 0x3 <br /> dspd_f3 = 0x3 <br /> dspu_f0 = 0x1 <br /> dspu_f1 = 0x8 <br /> dspu_f2 = 0x8 <br /> dspu_f3 = 0x3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_B0_WKPUPD(n) = 0x00000000<br /> idle_active_en_f0 = 0x0 <br /> idle_active_en_f1 = 0x0 <br /> idle_active_en_f2 = 0x0 <br /> idle_active_en_f3 = 0x0 <br /> pdpwk_f0 = 0x0 <br /> pdpwk_f1 = 0x0 <br /> pdpwk_f2 = 0x0 <br /> pdpwk_f3 = 0x0 <br /> pupwk_f0 = 0x0 <br /> pupwk_f1 = 0x0 <br /> pupwk_f2 = 0x0 <br /> pupwk_f3 = 0x0 <br /> wkds = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_B0_IOCTL(n) = 0x71500027<br /> en_pulse_tx_f0 = 0x1 <br /> en_pulse_tx_f1 = 0x1 <br /> en_pulse_tx_f2 = 0x1 <br /> en_pulse_tx_f3 = 0x0 <br /> isel_f0 = 0x1 <br /> isel_f1 = 0x1 <br /> isel_f2 = 0x1 <br /> isel_f3 = 0x0 <br /> sel_rx_ac_f0 = 0x0 <br /> sel_rx_ac_f1 = 0x0 <br /> sel_rx_ac_f2 = 0x0 <br /> sel_rx_ac_f3 = 0x0 <br /> sel_rx_dc_f0 = 0x1 <br /> sel_rx_dc_f1 = 0x1 <br /> sel_rx_dc_f2 = 0x1 <br /> sel_rx_dc_f3 = 0x0 <br /> tx_ac_f0 = 0x2 <br /> tx_ac_f1 = 0x0 <br /> tx_ac_f2 = 0x0 <br /> tx_ac_f3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_B0_ODT(n) = 0x01c00333<br /> dspd_f0 = 0x3 <br /> dspd_f1 = 0x3 <br /> dspd_f2 = 0x3 <br /> dspd_f3 = 0x0 <br /> zcpd_ovrr = 0x0 <br /> zcpd_val = 0x1c <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amph_CFGH_B0_ODTCTRL(n) = 0x00000000<br /> dspu_f0 = 0x0 <br /> dspu_f1 = 0x0 <br /> dspu_f2 = 0x0 <br /> dspu_f3 = 0x0 <br /> odten_f0 = 0x0 <br /> odten_f1 = 0x0 <br /> odten_f2 = 0x0 <br /> odten_f3 = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amph_CFGH_B0_ODTCTRL(n) = 0x00000000<br /> dspu_f0 = 0x0 <br /> dspu_f1 = 0x0 <br /> dspu_f2 = 0x0 <br /> dspu_f3 = 0x0 <br /> odten_f0 = 0x0 <br /> odten_f1 = 0x0 <br /> odten_f2 = 0x0 <br /> odten_f3 = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amph_CFGH_B0_ODTCTRL(n) = 0x00000007<br /> dspu_f0 = 0x0 <br /> dspu_f1 = 0x0 <br /> dspu_f2 = 0x0 <br /> dspu_f3 = 0x0 <br /> odten_f0 = 0x1 <br /> odten_f1 = 0x1 <br /> odten_f2 = 0x1 <br /> odten_f3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_B1_DRIVE_STR(n) = 0x33838317<br /> dspd_f0 = 0x7 <br /> dspd_f1 = 0x3 <br /> dspd_f2 = 0x3 <br /> dspd_f3 = 0x3 <br /> dspu_f0 = 0x1 <br /> dspu_f1 = 0x8 <br /> dspu_f2 = 0x8 <br /> dspu_f3 = 0x3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amph_CFGH_B1_ODTCTRL(n) = 0x00000000<br /> dspu_f0 = 0x0 <br /> dspu_f1 = 0x0 <br /> dspu_f2 = 0x0 <br /> dspu_f3 = 0x0 <br /> odten_f0 = 0x0 <br /> odten_f1 = 0x0 <br /> odten_f2 = 0x0 <br /> odten_f3 = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amph_CFGH_B1_ODTCTRL(n) = 0x00000000<br /> dspu_f0 = 0x0 <br /> dspu_f1 = 0x0 <br /> dspu_f2 = 0x0 <br /> dspu_f3 = 0x0 <br /> odten_f0 = 0x0 <br /> odten_f1 = 0x0 <br /> odten_f2 = 0x0 <br /> odten_f3 = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amph_CFGH_B1_ODTCTRL(n) = 0x00000007<br /> dspu_f0 = 0x0 <br /> dspu_f1 = 0x0 <br /> dspu_f2 = 0x0 <br /> dspu_f3 = 0x0 <br /> odten_f0 = 0x1 <br /> odten_f1 = 0x1 <br /> odten_f2 = 0x1 <br /> odten_f3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_B1_WKPUPD(n) = 0x00000000<br /> idle_active_en_f0 = 0x0 <br /> idle_active_en_f1 = 0x0 <br /> idle_active_en_f2 = 0x0 <br /> idle_active_en_f3 = 0x0 <br /> pdpwk_f0 = 0x0 <br /> pdpwk_f1 = 0x0 <br /> pdpwk_f2 = 0x0 <br /> pdpwk_f3 = 0x0 <br /> pupwk_f0 = 0x0 <br /> pupwk_f1 = 0x0 <br /> pupwk_f2 = 0x0 <br /> pupwk_f3 = 0x0 <br /> wkds = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_B1_IOCTL(n) = 0x71500027<br /> en_pulse_tx_f0 = 0x1 <br /> en_pulse_tx_f1 = 0x1 <br /> en_pulse_tx_f2 = 0x1 <br /> en_pulse_tx_f3 = 0x0 <br /> isel_f0 = 0x1 <br /> isel_f1 = 0x1 <br /> isel_f2 = 0x1 <br /> isel_f3 = 0x0 <br /> sel_rx_ac_f0 = 0x0 <br /> sel_rx_ac_f1 = 0x0 <br /> sel_rx_ac_f2 = 0x0 <br /> sel_rx_ac_f3 = 0x0 <br /> sel_rx_dc_f0 = 0x1 <br /> sel_rx_dc_f1 = 0x1 <br /> sel_rx_dc_f2 = 0x1 <br /> sel_rx_dc_f3 = 0x0 <br /> tx_ac_f0 = 0x2 <br /> tx_ac_f1 = 0x0 <br /> tx_ac_f2 = 0x0 <br /> tx_ac_f3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_B1_ODT(n) = 0x01c00333<br /> dspd_f0 = 0x3 <br /> dspd_f1 = 0x3 <br /> dspd_f2 = 0x3 <br /> dspd_f3 = 0x0 <br /> zcpd_ovrr = 0x0 <br /> zcpd_val = 0x1c <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DQS0_WKPUPD(n) = 0x00000782<br /> idle_active_en_f0 = 0x0 <br /> idle_active_en_f1 = 0x0 <br /> idle_active_en_f2 = 0x0 <br /> idle_active_en_f3 = 0x0 <br /> pdpwk_f0 = 0x1 <br /> pdpwk_f1 = 0x0 <br /> pdpwk_f2 = 0x0 <br /> pdpwk_f3 = 0x1 <br /> pupwk_f0 = 0x0 <br /> pupwk_f1 = 0x0 <br /> pupwk_f2 = 0x0 <br /> pupwk_f3 = 0x0 <br /> wkds = 0x7 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DQS0_DRIVE_STR(n) = 0x33838317<br /> dspd_f0 = 0x7 <br /> dspd_f1 = 0x3 <br /> dspd_f2 = 0x3 <br /> dspd_f3 = 0x3 <br /> dspu_f0 = 0x1 <br /> dspu_f1 = 0x8 <br /> dspu_f2 = 0x8 <br /> dspu_f3 = 0x3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DQS0_IOCTL(n) = 0x71500007<br /> en_pulse_tx_f0 = 0x1 <br /> en_pulse_tx_f1 = 0x1 <br /> en_pulse_tx_f2 = 0x1 <br /> en_pulse_tx_f3 = 0x0 <br /> isel_f0 = 0x1 <br /> isel_f1 = 0x1 <br /> isel_f2 = 0x1 <br /> isel_f3 = 0x0 <br /> sel_rx_ac_f0 = 0x0 <br /> sel_rx_ac_f1 = 0x0 <br /> sel_rx_ac_f2 = 0x0 <br /> sel_rx_ac_f3 = 0x0 <br /> sel_rx_dc_f0 = 0x1 <br /> sel_rx_dc_f1 = 0x1 <br /> sel_rx_dc_f2 = 0x1 <br /> sel_rx_dc_f3 = 0x0 <br /> tx_ac_f0 = 0x0 <br /> tx_ac_f1 = 0x0 <br /> tx_ac_f2 = 0x0 <br /> tx_ac_f3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DQS0_ODT(n) = 0x01c00336<br /> dspd_f0 = 0x6 <br /> dspd_f1 = 0x3 <br /> dspd_f2 = 0x3 <br /> dspd_f3 = 0x0 <br /> zcpd_ovrr = 0x0 <br /> zcpd_val = 0x1c <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DQS0_ZDET_BIASEN(n) = 0x00060028<br /> bias_ena_f0 = 0x0 <br /> bias_ena_f1 = 0x1 <br /> bias_ena_f2 = 0x1 <br /> bias_ena_f3 = 0x0 <br /> disable_zdet_f0 = 0x0 <br /> disable_zdet_f1 = 0x0 <br /> disable_zdet_f2 = 0x0 <br /> disable_zdet_f3 = 0x0 <br /> sel_zdet_f0 = 0x0 <br /> sel_zdet_f1 = 0x2 <br /> sel_zdet_f2 = 0x2 <br /> sel_zdet_f3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amph_CFGH_DQS0_ODTCTRL(n) = 0x00000000<br /> dspu_f0 = 0x0 <br /> dspu_f1 = 0x0 <br /> dspu_f2 = 0x0 <br /> dspu_f3 = 0x0 <br /> odten_f0 = 0x0 <br /> odten_f1 = 0x0 <br /> odten_f2 = 0x0 <br /> odten_f3 = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amph_CFGH_DQS0_ODTCTRL(n) = 0x00000000<br /> dspu_f0 = 0x0 <br /> dspu_f1 = 0x0 <br /> dspu_f2 = 0x0 <br /> dspu_f3 = 0x0 <br /> odten_f0 = 0x0 <br /> odten_f1 = 0x0 <br /> odten_f2 = 0x0 <br /> odten_f3 = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amph_CFGH_DQS0_ODTCTRL(n) = 0x00000007<br /> dspu_f0 = 0x0 <br /> dspu_f1 = 0x0 <br /> dspu_f2 = 0x0 <br /> dspu_f3 = 0x0 <br /> odten_f0 = 0x1 <br /> odten_f1 = 0x1 <br /> odten_f2 = 0x1 <br /> odten_f3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DQS1_WKPUPD(n) = 0x00000782<br /> idle_active_en_f0 = 0x0 <br /> idle_active_en_f1 = 0x0 <br /> idle_active_en_f2 = 0x0 <br /> idle_active_en_f3 = 0x0 <br /> pdpwk_f0 = 0x1 <br /> pdpwk_f1 = 0x0 <br /> pdpwk_f2 = 0x0 <br /> pdpwk_f3 = 0x1 <br /> pupwk_f0 = 0x0 <br /> pupwk_f1 = 0x0 <br /> pupwk_f2 = 0x0 <br /> pupwk_f3 = 0x0 <br /> wkds = 0x7 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DQS1_DRIVE_STR(n) = 0x33838317<br /> dspd_f0 = 0x7 <br /> dspd_f1 = 0x3 <br /> dspd_f2 = 0x3 <br /> dspd_f3 = 0x3 <br /> dspu_f0 = 0x1 <br /> dspu_f1 = 0x8 <br /> dspu_f2 = 0x8 <br /> dspu_f3 = 0x3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DQS1_IOCTL(n) = 0x71500007<br /> en_pulse_tx_f0 = 0x1 <br /> en_pulse_tx_f1 = 0x1 <br /> en_pulse_tx_f2 = 0x1 <br /> en_pulse_tx_f3 = 0x0 <br /> isel_f0 = 0x1 <br /> isel_f1 = 0x1 <br /> isel_f2 = 0x1 <br /> isel_f3 = 0x0 <br /> sel_rx_ac_f0 = 0x0 <br /> sel_rx_ac_f1 = 0x0 <br /> sel_rx_ac_f2 = 0x0 <br /> sel_rx_ac_f3 = 0x0 <br /> sel_rx_dc_f0 = 0x1 <br /> sel_rx_dc_f1 = 0x1 <br /> sel_rx_dc_f2 = 0x1 <br /> sel_rx_dc_f3 = 0x0 <br /> tx_ac_f0 = 0x0 <br /> tx_ac_f1 = 0x0 <br /> tx_ac_f2 = 0x0 <br /> tx_ac_f3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DQS1_ODT(n) = 0x01c00336<br /> dspd_f0 = 0x6 <br /> dspd_f1 = 0x3 <br /> dspd_f2 = 0x3 <br /> dspd_f3 = 0x0 <br /> zcpd_ovrr = 0x0 <br /> zcpd_val = 0x1c <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DQS1_ZDET_BIASEN(n) = 0x00060028<br /> bias_ena_f0 = 0x0 <br /> bias_ena_f1 = 0x1 <br /> bias_ena_f2 = 0x1 <br /> bias_ena_f3 = 0x0 <br /> disable_zdet_f0 = 0x0 <br /> disable_zdet_f1 = 0x0 <br /> disable_zdet_f2 = 0x0 <br /> disable_zdet_f3 = 0x0 <br /> sel_zdet_f0 = 0x0 <br /> sel_zdet_f1 = 0x2 <br /> sel_zdet_f2 = 0x2 <br /> sel_zdet_f3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amph_CFGH_DQS1_ODTCTRL(n) = 0x00000000<br /> dspu_f0 = 0x0 <br /> dspu_f1 = 0x0 <br /> dspu_f2 = 0x0 <br /> dspu_f3 = 0x0 <br /> odten_f0 = 0x0 <br /> odten_f1 = 0x0 <br /> odten_f2 = 0x0 <br /> odten_f3 = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amph_CFGH_DQS1_ODTCTRL(n) = 0x00000000<br /> dspu_f0 = 0x0 <br /> dspu_f1 = 0x0 <br /> dspu_f2 = 0x0 <br /> dspu_f3 = 0x0 <br /> odten_f0 = 0x0 <br /> odten_f1 = 0x0 <br /> odten_f2 = 0x0 <br /> odten_f3 = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amph_CFGH_DQS1_ODTCTRL(n) = 0x00000007<br /> dspu_f0 = 0x0 <br /> dspu_f1 = 0x0 <br /> dspu_f2 = 0x0 <br /> dspu_f3 = 0x0 <br /> odten_f0 = 0x1 <br /> odten_f1 = 0x1 <br /> odten_f2 = 0x1 <br /> odten_f3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DBG_DBG_REG0(n) = 0x00000000<br /> cb_bias_ena = 0x0 <br /> cb_odte = 0x0 <br /> clk_en_sync_flop_rst = 0x0 <br /> mon_vdd_mem = 0x0 <br /> mon_vdd_soc = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_ZC_ZCAL_FSM1(n) = 0x00887f7f<br /> bias_ena_dly = 0x88 <br /> io_pd = 0x7f *read-only<br /> io_pu = 0x7f *read-only<br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_ZC_ZCAL_FSM0(n) = 0x000f031b<br /> zc_dly = 0x1b <br /> zc_dnbd = 0x0 <br /> zc_tap = 0x3 <br /> zc_upbd = 0xf <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DEBUG_SPARE0(n) = 0x00000016<br /> control = 0x16 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Assert init_done </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscagen_ampinit(n) = 0x00000001<br /> InitDone = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Assert init_done </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqgen_ampinit(n) = 0x00000001<br /> InitDone = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_DFICalTiming(n) = 0x06000504<br /> tCA2CAEntry = 0x4 <br /> tCA2CAExit = 0x0 <br /> tCKEHEntry = 0x5 <br /> tCKEHExit = 0x6 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWRdDqCaltVREF(n) = 0x08080808<br /> HWRdDqCaltVREF_f0 = 0x8 <br /> HWRdDqCaltVREF_f1 = 0x8 <br /> HWRdDqCaltVREF_f2 = 0x8 <br /> HWRdDqCaltVREF_f3 = 0x8 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
|
|
<h4>3. Self-Refresh Exit</h4>
|
|
<p>Prior to this step, the DRAM is assumed to be in the self-refresh state, and CKE has been kept low, either by retention circuitry in the PHY/IO, or, after SOC power is up and the reset is done, by the controller. This step will take DRAM out of the self-refresh mode. Software must guarantee that at least 50 us have passed since the de- assertion of AMC reset before self-refresh exit, in the resume-boot case.
|
|
The frequency change to 50MHz here is initiated by PMGR.
|
|
For ResumeBoot, the auto-refresh must be enabled before exiting self-refresh state.<br /> </p>
|
|
<table class="section">
|
|
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
|
|
</tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 5us after Impedance Calibration in Step2. This is to avoid McPhyPending preventing the SRFSM from exiting SR. </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > radar #8707478 has been fixed. SetSRExitRefCnt to 2. </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_arefparam(n) = 0x0d012019<br /> FreqChngWaitThr = 0x1 <br /> PhyUpdWaitRefresh = 0x1 <br /> PhyUpdWaitThr = 0x1 <br /> PhyUpdWaittXSR = 0x0 <br /> PreFreqChngWaitThr = 0x2 <br /> RefAssertCnt = 0xd <br /> SRExitRefCnt = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq3(n) = 0x03050005<br /> tRFCBaseCyc_freq3 = 0x5 <br /> tRFCCyc_freq3 = 0x5 <br /> tRFCpbCyc_freq3 = 0x3 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq3(n) = 0x01010001<br /> tRFCBaseCyc_freq3 = 0x1 <br /> tRFCCyc_freq3 = 0x1 <br /> tRFCpbCyc_freq3 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq3(n) = 0x03050005<br /> tRFCBaseCyc_freq3 = 0x5 <br /> tRFCCyc_freq3 = 0x5 <br /> tRFCpbCyc_freq3 = 0x3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq2(n) = 0x48900013<br /> tRFCBaseCyc_freq2 = 0x13 <br /> tRFCCyc_freq2 = 0x90 <br /> tRFCpbCyc_freq2 = 0x48 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq2(n) = 0x01010001<br /> tRFCBaseCyc_freq2 = 0x1 <br /> tRFCCyc_freq2 = 0x1 <br /> tRFCpbCyc_freq2 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq2(n) = 0x09120013<br /> tRFCBaseCyc_freq2 = 0x13 <br /> tRFCCyc_freq2 = 0x12 <br /> tRFCpbCyc_freq2 = 0x9 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq1(n) = 0x48900049<br /> tRFCBaseCyc_freq1 = 0x49 <br /> tRFCCyc_freq1 = 0x90 <br /> tRFCpbCyc_freq1 = 0x48 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq1(n) = 0x01010001<br /> tRFCBaseCyc_freq1 = 0x1 <br /> tRFCCyc_freq1 = 0x1 <br /> tRFCpbCyc_freq1 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq1(n) = 0x24480049<br /> tRFCBaseCyc_freq1 = 0x49 <br /> tRFCCyc_freq1 = 0x48 <br /> tRFCpbCyc_freq1 = 0x24 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq0(n) = 0x48900092<br /> tRFCBaseCyc_freq0 = 0x92 <br /> tRFCCyc_freq0 = 0x90 <br /> tRFCpbCyc_freq0 = 0x48 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq0(n) = 0x01010001<br /> tRFCBaseCyc_freq0 = 0x1 <br /> tRFCCyc_freq0 = 0x1 <br /> tRFCpbCyc_freq0 = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_freq0(n) = 0x48900092<br /> tRFCBaseCyc_freq0 = 0x92 <br /> tRFCCyc_freq0 = 0x90 <br /> tRFCpbCyc_freq0 = 0x48 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_params(n) = 0x0017005d<br /> tREFBWtRFCcnt = 0x17 <br /> tREFICyc = 0x5d <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_params(n) = 0x002f0013<br /> tREFBWtRFCcnt = 0x2f <br /> tREFICyc = 0x13 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramtim_autoref_params(n) = 0x0017005d<br /> tREFBWtRFCcnt = 0x17 <br /> tREFICyc = 0x5d <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable auto refresh derating by setting TempDrtEn to 1. However, we do not enable ODTS interval until the end of the init. Setting TempDrtEn to 1 allows the chip to be in the hi-temp state and become more conservative. </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramcfg_odtszqc(n) = 0x00000000<br /> DerateParamSRExit = 0x0 <br /> OdtsRdIntrvl = 0x0 <br /> SRExitZQCChnlQuiet = 0x0 <br /> ShareZQRes = 0x0 <br /> TempDrtEn = 0x0 <br /> ZQCChnlQuiet = 0x0 <br /> ZQCStack = 0x0 <br /> ZqCalIntrvl = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramcfg_odtszqc(n) = 0x00001000<br /> DerateParamSRExit = 0x0 <br /> OdtsRdIntrvl = 0x0 <br /> SRExitZQCChnlQuiet = 0x0 <br /> ShareZQRes = 0x0 <br /> TempDrtEn = 0x1 <br /> ZQCChnlQuiet = 0x0 <br /> ZQCStack = 0x0 <br /> ZqCalIntrvl = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > set SRExtraRefCnt to correct value (which is 1) and set LongSRCnt to be tREFW/4 (32ms/4=8ms) <br /> If RefCntrHiWaterMark is changed from its default value, then LongSRExitRefCnt needs to be programmed to the same value.<br /> Palladium: LongSRCnt=0x1004 because Palladium uses 1Gb device. </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_longsr(n) = 0x01022008<br /> LongSRCnt = 0x2008 <br /> LongSRExitRefCnt = 0x1 <br /> SRExtraRefCnt = 0x2 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_mcphyupdtparam(n) = 0x15030004<br /> FreqCSettleCyc = 0x5 <br /> McPhyTimeParamCyc = 0x3 <br /> PhyInitStartCyc = 0x0 <br /> PhyUpdMDLL = 0x1 <br /> UpdPhyLatCyc = 0x0 <br /> tPhyUpdGap = 0x4 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Call custom API provided by PMGR for changing mcu_clk to 55Mhz<br /> // TO BE COMPLETED<br /><br /><b>FPGA:</b> Skip this step<br /><br /> </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 5us to avoid a race condition between frequency change to bucket 3 & MCU being enabled </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn on enables for various AMC blocks MCU. </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_amcgen_amcctrl(n) = 0x00000003<br /> McuEn = 0x1 <br /> SchEn = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Run impedance calibration and optionally enable periodic auto impedance calibration<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaiocfg_impcalcmd(n) = 0x00000001<br /> RunImpCal = 0x1 <br /> RunImpCalType = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll ampscaiocfg impcalcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: ampscaiocfg_impcalcmd<br />
|
|
RunImpCal<br />
|
|
while((CSR(ampsca_ampscaiocfg_impcalcmd(n)) & 0x1) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_arefen_freq3(n) = 0x10100000<br /> ARpbEn_freq3 = 0x0 <br /> HiTempRefRnkAgeOut_freq3 = 0x1 <br /> RefCntrHiWaterMark_freq3 = 0x1 <br /> RefCntrLoWaterMark_freq3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_arefen_freq2(n) = 0x10000000<br /> ARpbEn_freq2 = 0x0 <br /> HiTempRefRnkAgeOut_freq2 = 0x0 <br /> RefCntrHiWaterMark_freq2 = 0x1 <br /> RefCntrLoWaterMark_freq2 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_arefen_freq1(n) = 0x10010000<br /> ARpbEn_freq1 = 0x1 <br /> HiTempRefRnkAgeOut_freq1 = 0x0 <br /> RefCntrHiWaterMark_freq1 = 0x1 <br /> RefCntrLoWaterMark_freq1 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn on auto refresh. </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_arefen_freq0(n) = 0x1011013f<br /> ARpbEn_freq0 = 0x1 <br /> AutoRefEn = 0x1 <br /> AutoRefSchEn = 0x1 <br /> DisableHiTempREFab = 0x1 <br /> EarlyCasAgeOut = 0x0 <br /> HiPriREFpbPch = 0x1 <br /> HiTempRefRnkAgeOut_freq0 = 0x1 <br /> REFpb2bank = 0x0 <br /> REFpbEarlyPch = 0x1 <br /> RefCntrHiWaterMark_freq0 = 0x1 <br /> RefCntrLoWaterMark_freq0 = 0x0 <br /> RefOpptEn = 0x1 <br /> tREFBWREFpb = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 200us for tINIT1 in real init, which we have cooked down to 200ns for simulation. </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 2 ms for tINIT3 in real init, which we have cooked down to 200ns for simulation. </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl(n) = 0x01010000<br /> freqchngfspop = 0x1 <br /> freqchngfspopupd = 0x0 <br /> freqchngmrwcnt_freq0 = 0x0 <br /> freqchngmrwcnt_freq1 = 0x0 <br /> freqchngmrwcnt_freq2 = 0x0 <br /> freqchngmrwcnt_freq3 = 0x0 <br /> freqchngrunsocupd = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcfg freqchngctl </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcfg_freqchngctl<br />
|
|
freqchngrunsocupd<br />
|
|
while((CSR(amcx_dramcfg_freqchngctl(n)) & 0x10000) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl(n) = 0x01000000<br /> freqchngfspop = 0x1 <br /> freqchngfspopupd = 0x0 <br /> freqchngmrwcnt_freq0 = 0x0 <br /> freqchngmrwcnt_freq1 = 0x0 <br /> freqchngmrwcnt_freq2 = 0x0 <br /> freqchngmrwcnt_freq3 = 0x0 <br /> freqchngrunsocupd = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 2us for the soc update to finish </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Assert MPC to Sending SR Exit during Resume Boot </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x00004000<br /> MRCmdAddr = 0x0 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x0 <br /> MRCmdIsMPC = 0x1 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x0 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Issue self-refresh exit command. One for each channel.<br /> SW needs to guarantee that at least 50usec has passed since removal of reset to AMC before issuing the self-refresh exit command, in case of resume boot. </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x00004001<br /> MRCmdAddr = 0x0 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x0 <br /> MRCmdIsMPC = 0x1 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x0 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunSRExit<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x1) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Assert MPC to Sending SR Exit during Resume Boot </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x00000000<br /> MRCmdAddr = 0x0 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x0 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x0 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Issue self-refresh exit command. One for each channel.<br /> SW needs to guarantee that at least 50usec has passed since removal of reset to AMC before issuing the self-refresh exit command, in case of resume boot. </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x00000001<br /> MRCmdAddr = 0x0 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x0 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x0 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunSRExit<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x1) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 2 us for tINIT5 in real init, which we have cooked down to 200ns for simulation. </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FOUR_CH_ONE_RANK)</td></tr>
|
|
<tr><td class="programming"> glbtimer_GlbTimer_ChEn = 0x0000000f<br /> ChEn = 0xf <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == EIGHT_CH_ONE_RANK)</td></tr>
|
|
<tr><td class="programming"> glbtimer_GlbTimer_ChEn = 0x000000ff<br /> ChEn = 0xff <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> glbtimer_GlbTimer_ChEn = 0x000000ff<br /> ChEn = 0xff <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
|
|
<h4> 4. DRAM Reset, ZQ Calibration & Configuration (Cold Boot Only).</h4>
|
|
<p> This step is only required for ColdBoot.
|
|
This step is to be repeated for each of the number of ranks per channel. The dramcmd.mrcmdch{N}.MRCmdCsCh{N} bit (Noted by letter R in the section) should be incremented in each loop.<br /> </p>
|
|
<table class="section">
|
|
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
|
|
</tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Issue DRAM ZQ calibration START MPC command MRINIT CMD registers.<br /> Note that the MPC command can be issued to different channels independently, as long as the system has separate ZQ reference resistor for eachchannel. TheZQcalibration MPC to each rank within the same channel must be issued in series. </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x4f004100<br /> MRCmdAddr = 0x0 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x4f <br /> MRCmdIsMPC = 0x1 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 1us for tZQCAL. </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Issue DRAM ZQ calibration LATCH MPC command MRINIT CMD registers </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x51004100<br /> MRCmdAddr = 0x0 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x51 <br /> MRCmdIsMPC = 0x1 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 20ns for tZQLAT. </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Configure DRAM MR2 register (latency) through MRR/MRW command registers. The example shows the nominal programming for LPDDR2-1066 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices. </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x00020100<br /> MRCmdAddr = 0x2 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x0 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Configure DRAM MR1 register through MRR/MRW command registers.<br /> This includes the following: WC=Wrap BT=Sequential BL=BL16.<br /> nWR, the example shows the nominal programming for LPDDR3- 1600 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices. </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x8e010100<br /> MRCmdAddr = 0x1 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x8e <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0xf3030100<br /> MRCmdAddr = 0x3 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0xf3 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x00160100<br /> MRCmdAddr = 0x16 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x0 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x000b0100<br /> MRCmdAddr = 0xb <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x0 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Perform this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program VRCG and modified refresh to 1 </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x180d0100<br /> MRCmdAddr = 0xd <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x18 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x590c0100<br /> MRCmdAddr = 0xc <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x59 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x590e0100<br /> MRCmdAddr = 0xe <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x59 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x80170100<br /> MRCmdAddr = 0x17 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x80 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program MR15/20 to match PatInvertMask of HW RdDQ calibration </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x550f4100<br /> MRCmdAddr = 0xf <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x55 <br /> MRCmdIsMPC = 0x1 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program MR15/20 to match PatInvertMask of HW RdDQ calibration </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x55144100<br /> MRCmdAddr = 0x14 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x55 <br /> MRCmdIsMPC = 0x1 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program MR32/40 to match the PatPRBS4 pattern for HW RdDQ calibration </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x5a204100<br /> MRCmdAddr = 0x20 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x5a <br /> MRCmdIsMPC = 0x1 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program MR32/40 to match the PatPRBS4 pattern for HW RdDQ calibration </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x3c284100<br /> MRCmdAddr = 0x28 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x3c <br /> MRCmdIsMPC = 0x1 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></table>
|
|
<h4>5. Topology-specific configuration.</h4>
|
|
<p>Here we perform MRR's to the memory to find out device density and program addrcfg, DramAccCtrl and mccchnldec registers<br /> </p>
|
|
<table class="section">
|
|
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
|
|
</tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA_LPDDR3)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_addrcfg = 0x00030201<br /> BnkAddrWid = 0x1 <br /> ColAddrWid = 0x2 <br /> CsWid = 0x0 <br /> RowAddrWid = 0x3 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == ONE_CH_ONE_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_addrcfg = 0x00030201<br /> BnkAddrWid = 0x1 <br /> ColAddrWid = 0x2 <br /> CsWid = 0x0 <br /> RowAddrWid = 0x3 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == ONE_CH_TWO_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_addrcfg = 0x01030201<br /> BnkAddrWid = 0x1 <br /> ColAddrWid = 0x2 <br /> CsWid = 0x1 <br /> RowAddrWid = 0x3 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FOUR_CH_ONE_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_addrcfg = 0x00030201<br /> BnkAddrWid = 0x1 <br /> ColAddrWid = 0x2 <br /> CsWid = 0x0 <br /> RowAddrWid = 0x3 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == TWO_CH_TWO_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_addrcfg = 0x01030201<br /> BnkAddrWid = 0x1 <br /> ColAddrWid = 0x2 <br /> CsWid = 0x1 <br /> RowAddrWid = 0x3 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_addrcfg = 0x00030201<br /> BnkAddrWid = 0x1 <br /> ColAddrWid = 0x2 <br /> CsWid = 0x0 <br /> RowAddrWid = 0x3 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FOUR_CH_TWO_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_addrcfg = 0x01030201<br /> BnkAddrWid = 0x1 <br /> ColAddrWid = 0x2 <br /> CsWid = 0x1 <br /> RowAddrWid = 0x3 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == EIGHT_CH_ONE_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_addrcfg = 0x00030201<br /> BnkAddrWid = 0x1 <br /> ColAddrWid = 0x2 <br /> CsWid = 0x0 <br /> RowAddrWid = 0x3 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == TWO_CH_ONE_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_addrcfg = 0x00030201<br /> BnkAddrWid = 0x1 <br /> ColAddrWid = 0x2 <br /> CsWid = 0x0 <br /> RowAddrWid = 0x3 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_addrcfg = 0x00030201<br /> BnkAddrWid = 0x1 <br /> ColAddrWid = 0x2 <br /> CsWid = 0x0 <br /> RowAddrWid = 0x3 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA_LPDDR3)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_DramAccCtrl = 0x00000007<br /> DramSize = 0x7 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == ONE_CH_ONE_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_DramAccCtrl = 0x00000003<br /> DramSize = 0x3 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == ONE_CH_TWO_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_DramAccCtrl = 0x00000007<br /> DramSize = 0x7 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FOUR_CH_ONE_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_DramAccCtrl = 0x00000007<br /> DramSize = 0x7 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == TWO_CH_TWO_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_DramAccCtrl = 0x00000007<br /> DramSize = 0x7 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_DramAccCtrl = 0x0000000f<br /> DramSize = 0xf <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FOUR_CH_TWO_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_DramAccCtrl = 0x0000000f<br /> DramSize = 0xf <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == EIGHT_CH_ONE_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_DramAccCtrl = 0x0000000f<br /> DramSize = 0xf <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == TWO_CH_ONE_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_DramAccCtrl = 0x00000007<br /> DramSize = 0x7 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_DramAccCtrl = 0x0000000f<br /> DramSize = 0xf <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > dram_Density_config(); </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA_LPDDR3)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00050120<br /> ChSelHiBits = 0x5 <br /> ChSelTyp = 0x0 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x2 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == ONE_CH_ONE_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00050101<br /> ChSelHiBits = 0x5 <br /> ChSelTyp = 0x1 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == ONE_CH_TWO_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00060101<br /> ChSelHiBits = 0x6 <br /> ChSelTyp = 0x1 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FOUR_CH_ONE_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00050110<br /> ChSelHiBits = 0x5 <br /> ChSelTyp = 0x0 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == TWO_CH_TWO_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00060100<br /> ChSelHiBits = 0x6 <br /> ChSelTyp = 0x0 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00050120<br /> ChSelHiBits = 0x5 <br /> ChSelTyp = 0x0 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x2 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == FOUR_CH_TWO_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00060110<br /> ChSelHiBits = 0x6 <br /> ChSelTyp = 0x0 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == EIGHT_CH_ONE_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00050120<br /> ChSelHiBits = 0x5 <br /> ChSelTyp = 0x0 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x2 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else if (platform == TWO_CH_ONE_RANK)</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00050100<br /> ChSelHiBits = 0x5 <br /> ChSelTyp = 0x0 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcc_MccLockRegion_mccchnldec = 0x00050120<br /> ChSelHiBits = 0x5 <br /> ChSelTyp = 0x0 <br /> ChnlStartBit = 0x1 <br /> NumMcuChnl = 0x2 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
|
|
<h4>6. Prepare for switch from boot-clock speed to normal operation speed</h4>
|
|
<p>The frequency change is initiated by PMGR.<br /> </p>
|
|
<table class="section">
|
|
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
|
|
</tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 5us before issuing a freq change to make sure all refreshes have been flushed. </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable AMC scheduler to allow normal transactions to be processed. <br /> Scheduler has to be enabled to let AMC issue self-refresh entry and allow frequency change. </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_amcgen_amcctrl(n) = 0x00000003<br /> McuEn = 0x1 <br /> SchEn = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
|
|
<h4>11. Setup registers for CA calibration for bucket 0</h4>
|
|
<p><br /> </p>
|
|
<table class="section">
|
|
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
|
|
</tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program FSP-WR to 1 and FSP-OP to 0 and set VRCG and modified refresh </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x580d0100<br /> MRCmdAddr = 0xd <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x58 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Configure DRAM MR2 register (latency) through MRR/MRW command registers. The example shows the nominal programming for LPDDR2-1066 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices.<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x2d020100<br /> MRCmdAddr = 0x2 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x2d <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Configure DRAM MR1 register through MRR/MRW command registers.<br /> This includes the following: WC=Wrap BT=Sequential BL=BL16.<br /> nWR, the example shows the nominal programming for LPDDR3- 1600 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices.<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0xde010100<br /> MRCmdAddr = 0x1 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0xde <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0xb3030100<br /> MRCmdAddr = 0x3 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0xb3 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x04160100<br /> MRCmdAddr = 0x16 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x4 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x440b0100<br /> MRCmdAddr = 0xb <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x44 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Perform this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x000b0100<br /> MRCmdAddr = 0xb <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x0 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Perform this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x110c0100<br /> MRCmdAddr = 0xc <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x11 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x110e0100<br /> MRCmdAddr = 0xe <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x11 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscawrlvl_ampcawrlvlsdllcode(n) = 0x00000200<br /> WrLvlMaxWrDqsSDLLCode = 0x0 <br /> WrLvlRunUpdOverride = 0x0 <br /> WrLvlRunUpdWrResult = 0x1 <br /> WrLvlSDLLCode = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll ampscawrlvl ampcawrlvlsdllcode </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: ampscawrlvl_ampcawrlvlsdllcode<br />
|
|
WrLvlRunUpdWrResult<br />
|
|
while((CSR(ampsca_ampscawrlvl_ampcawrlvlsdllcode(n)) & 0x200) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></table>
|
|
<h4>12. AMP Dynamic Address Timing Calibration</h4>
|
|
<p><br /> </p>
|
|
<table class="section">
|
|
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
|
|
</tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > step12Calibration(0, LPDDR3, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, CA_CALIB, 0, 0, 0, 0, 0, 0, 0, 28, 14);<br /> </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL Init and Incr lock timers based on 24 MHz value<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscadllctl_dlllocktim(n) = 0x00130013<br /> DllIncLockTim = 0x13 <br /> DllInitLockTim = 0x13 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL Init and Incr lock timers based on 24 MHz value<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqdllctl_dlllocktim(n) = 0x00130013<br /> DllIncLockTim = 0x13 <br /> DllInitLockTim = 0x13 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Disable AMP Clock Gating for RunDllUpdt to go through<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscagen_ampclk(n) = 0x00100001<br /> FMClkIdleDetectEn = 0x0 <br /> ForceDRAMClkEn = 0x0 <br /> ForceDiv2MClkTopGaterOn = 0x1 <br /> ForceFMClkWakeUp = 0x0 <br /> ForceMClkWakeUp = 0x0 <br /> TopClkGateDis = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Defer SDLL update until frequency change </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscasdllctrl_SDLLUpdateDeferEn(n) = 0x00000001<br /> DeferEn = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Defer SDLL update until frequency change </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqsdllctrl_SDLLUpdateDeferEn(n) = 0x00000001<br /> DeferEn = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Set MDLL override to 0 </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqdllctl_MDLLOverride(n) = 0x00010000<br /> MDLLOvrCode = 0x0 <br /> MDLLOvrSel = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Run MDLL update </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqdllctl_dllupdtcmd(n) = 0x00000001<br /> RunDllUpdt = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll ampsdqdllctl dllupdtcmd </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: ampsdqdllctl_dllupdtcmd<br />
|
|
RunDllUpdt<br />
|
|
while((CSR(ampsdq_ampsdqdllctl_dllupdtcmd(n)) & 0x1) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable back AMP Clock Gating for RunDllUpdt to go through<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscagen_ampclk(n) = 0x00000000<br /> FMClkIdleDetectEn = 0x0 <br /> ForceDRAMClkEn = 0x0 <br /> ForceDiv2MClkTopGaterOn = 0x0 <br /> ForceFMClkWakeUp = 0x0 <br /> ForceMClkWakeUp = 0x0 <br /> TopClkGateDis = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL Init and Incr lock timers based on 24 MHz value<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscadllctl_dlllocktim(n) = 0x012c012c<br /> DllIncLockTim = 0x12c <br /> DllInitLockTim = 0x12c <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL Init and Incr lock timers based on 24 MHz value<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqdllctl_dlllocktim(n) = 0x012c012c<br /> DllIncLockTim = 0x12c <br /> DllInitLockTim = 0x12c <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl1_freq0(n) = 0x110c110e<br /> freqchngmrw2_addr_freq0 = 0xe <br /> freqchngmrw2_ctrl_freq0 = 0x0 <br /> freqchngmrw2_data_freq0 = 0x11 <br /> freqchngmrw3_addr_freq0 = 0xc <br /> freqchngmrw3_ctrl_freq0 = 0x0 <br /> freqchngmrw3_data_freq0 = 0x11 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > HWRdWrDqCalFullScanEnable<br /><br /> <b>PALLADIUM</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWRdWrDqCalFullScanEnable(n) = 0x00000003<br /> HWRdDqCalFullScanEnable = 0x1 <br /> HWRdDqCalFullScanEnable16bit = 0x0 <br /> HWWrDqCalFullScanEnable = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></table>
|
|
<h4>13. Setup registers for DQ calibration for bucket 0</h4>
|
|
<p><br /> </p>
|
|
<table class="section">
|
|
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
|
|
</tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program FSP-WR to 0, FSP-OP to 1 and set VRCG and modified refresh<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x980d0100<br /> MRCmdAddr = 0xd <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x98 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 1us for FSP setting to take affect. </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program AutoSR </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_pwrmngten(n) = 0x00000132<br /> AutoSR = 0x1 <br /> DynPwrDnEn = 0x0 <br /> McPhyUpdDramClkOff = 0x0 <br /> PwrDnClkOff = 0x1 <br /> SRClkOff = 0x1 <br /> SRExitOpt = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program FreqChngMRW Cnt </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl(n) = 0x02009999<br /> freqchngfspop = 0x0 <br /> freqchngfspopupd = 0x1 <br /> freqchngmrwcnt_freq0 = 0x9 <br /> freqchngmrwcnt_freq1 = 0x9 <br /> freqchngmrwcnt_freq2 = 0x9 <br /> freqchngmrwcnt_freq3 = 0x9 <br /> freqchngrunsocupd = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > WrDqDqsSDLLCtrl </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n) = 0xff000008<br /> WrDqDqsRunSDLLUpd = 0x0 <br /> WrDqDqsRunSDLLUpdOverride = 0x0 <br /> WrDqDqsRunSDLLUpdWrResult = 0x0 <br /> WrDqDqsWrLvlReBalanceEn = 0x1 <br /> WrDqSDLLAddHalfClk_f0 = 0x0 <br /> WrDqSDLLAddHalfClk_f1 = 0x0 <br /> WrDqSDLLAddHalfClk_f2 = 0x0 <br /> WrDqSDLLAddHalfClk_f3 = 0x0 <br /> WrDqSDLLHalfClkEn = 0x0 <br /> WrDqSDLLHalfClkOvrVal = 0x0 <br /> WrDqSDLLHalfClkStatus = 0x0 *read-only<br /> WrDqSDLLOvrVal = 0x0 <br /> WrDqsSDLLOvrVal = 0xff <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Re-enable SDLL updates </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscasdllctrl_SDLLUpdateDeferEn(n) = 0x00000000<br /> DeferEn = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Re-enable SDLL updates </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqsdllctrl_SDLLUpdateDeferEn(n) = 0x00000000<br /> DeferEn = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Disable MDLL override </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqdllctl_MDLLOverride(n) = 0x00000000<br /> MDLLOvrCode = 0x0 <br /> MDLLOvrSel = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Call custom API provided by PMGR for changing mcu_clk to 1600Mhz<br /> // TO BE COMPLETED<br /><br /><b>FPGA:</b> Skip this step<br /><br /> </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl(n) = 0x00010000<br /> freqchngfspop = 0x0 <br /> freqchngfspopupd = 0x0 <br /> freqchngmrwcnt_freq0 = 0x0 <br /> freqchngmrwcnt_freq1 = 0x0 <br /> freqchngmrwcnt_freq2 = 0x0 <br /> freqchngmrwcnt_freq3 = 0x0 <br /> freqchngrunsocupd = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcfg freqchngctl </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcfg_freqchngctl<br />
|
|
freqchngrunsocupd<br />
|
|
while((CSR(amcx_dramcfg_freqchngctl(n)) & 0x10000) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl(n) = 0x00000000<br /> freqchngfspop = 0x0 <br /> freqchngfspopupd = 0x0 <br /> freqchngmrwcnt_freq0 = 0x0 <br /> freqchngmrwcnt_freq1 = 0x0 <br /> freqchngmrwcnt_freq2 = 0x0 <br /> freqchngmrwcnt_freq3 = 0x0 <br /> freqchngrunsocupd = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 2us for the soc update to finish </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
|
|
<h4>14. AMP Dynamic DQ Calibration</h4>
|
|
<p><br /> </p>
|
|
<table class="section">
|
|
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
|
|
</tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > step14Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, WRLVL, 0, 0, 0, 0, 0, 28, 14);<br /> </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DQS0_WKPUPD(n) = 0x00010782<br /> idle_active_en_f0 = 0x1 <br /> idle_active_en_f1 = 0x0 <br /> idle_active_en_f2 = 0x0 <br /> idle_active_en_f3 = 0x0 <br /> pdpwk_f0 = 0x1 <br /> pdpwk_f1 = 0x0 <br /> pdpwk_f2 = 0x0 <br /> pdpwk_f3 = 0x1 <br /> pupwk_f0 = 0x0 <br /> pupwk_f1 = 0x0 <br /> pupwk_f2 = 0x0 <br /> pupwk_f3 = 0x0 <br /> wkds = 0x7 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_DQS1_WKPUPD(n) = 0x00010782<br /> idle_active_en_f0 = 0x1 <br /> idle_active_en_f1 = 0x0 <br /> idle_active_en_f2 = 0x0 <br /> idle_active_en_f3 = 0x0 <br /> pdpwk_f0 = 0x1 <br /> pdpwk_f1 = 0x0 <br /> pdpwk_f2 = 0x0 <br /> pdpwk_f3 = 0x1 <br /> pupwk_f0 = 0x0 <br /> pupwk_f1 = 0x0 <br /> pupwk_f2 = 0x0 <br /> pupwk_f3 = 0x0 <br /> wkds = 0x7 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > step14Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, RD_DQ_CAL, 0, 0, 0, 0, 0, 28, 14);<br /> </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > step14Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, WR_DQ_CAL, 0, 0, 0, 0, 0, 28, 14);<br /> </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
|
|
<h4>15. Setup registers for boot.</h4>
|
|
<p><br /> </p>
|
|
<table class="section">
|
|
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
|
|
</tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program FSP-WR to 0 and FSP-OP to 1 and reset VRCG<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x900d0100<br /> MRCmdAddr = 0xd <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x90 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program FSP-WR to 1 and FSP-OP to 0 and reset VRCG<br /><br /> <b>FPGA</b>: Perform this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x500d0100<br /> MRCmdAddr = 0xd <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x50 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x0 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Perform this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
|
|
RunMRCmd<br />
|
|
while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 1us for FSP setting to take affect. </td>
|
|
<td><table class="platform">
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program FreqChngMRW Cnt </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_freqchngctl(n) = 0x00009999<br /> freqchngfspop = 0x0 <br /> freqchngfspopupd = 0x0 <br /> freqchngmrwcnt_freq0 = 0x9 <br /> freqchngmrwcnt_freq1 = 0x9 <br /> freqchngmrwcnt_freq2 = 0x9 <br /> freqchngmrwcnt_freq3 = 0x9 <br /> freqchngrunsocupd = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n) = 0xff000008<br /> WrDqDqsRunSDLLUpd = 0x0 <br /> WrDqDqsRunSDLLUpdOverride = 0x0 <br /> WrDqDqsRunSDLLUpdWrResult = 0x0 <br /> WrDqDqsWrLvlReBalanceEn = 0x1 <br /> WrDqSDLLAddHalfClk_f0 = 0x0 <br /> WrDqSDLLAddHalfClk_f1 = 0x0 <br /> WrDqSDLLAddHalfClk_f2 = 0x0 <br /> WrDqSDLLAddHalfClk_f3 = 0x0 <br /> WrDqSDLLHalfClkEn = 0x0 <br /> WrDqSDLLHalfClkOvrVal = 0x0 <br /> WrDqSDLLHalfClkStatus = 0x0 *read-only<br /> WrDqSDLLOvrVal = 0x0 <br /> WrDqsSDLLOvrVal = 0xff <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > RdDqSDLLDelaySel<br /><br /> <b>DO_CALIBRATION</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqsdllctrl_RdDqSDLLDelaySel(n) = 0x00000000<br /> RdDqSDLLDelaySel = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > rd0sdllctrl<br /><br /> <b>DO_CALIBRATION</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqsdllctrl_rd0sdllctrl(n) = 0x00140004<br /> Rd0RunSDLLUpd = 0x0 <br /> Rd0RunSDLLUpdOverride = 0x0 <br /> Rd0RunSDLLUpdWrResult = 0x1 <br /> Rd0SDLLOvrVal = 0x14 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll ampsdqsdllctrl rd0sdllctrl<br /><br /> <b>DO_CALIBRATION</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> Poll: ampsdqsdllctrl_rd0sdllctrl<br />
|
|
Rd0RunSDLLUpdWrResult<br />
|
|
while((CSR(ampsdq_ampsdqsdllctrl_rd0sdllctrl(n)) & 0x4) != 0x0) <br />
|
|
</td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Skip this step <br /><br /> <b>PALLADIUM</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWRdWrDqCalFullScanEnable(n) = 0x00000000<br /> HWRdDqCalFullScanEnable = 0x0 <br /> HWRdDqCalFullScanEnable16bit = 0x0 <br /> HWWrDqCalFullScanEnable = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Skip this step <br /><br /> <b>PALLADIUM</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWRdWrDqCalFullScanEnable(n) = 0x00000003<br /> HWRdDqCalFullScanEnable = 0x1 <br /> HWRdDqCalFullScanEnable16bit = 0x0 <br /> HWWrDqCalFullScanEnable = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWRdDqCalVREFControl(n) = 0x02d0b061<br /> HWRdDqCalVREFEnable = 0x1 <br /> HWRdDqCalVREFMax = 0xd0 <br /> HWRdDqCalVREFMaxOffsetScaleFactor = 0x2 <br /> HWRdDqCalVREFMaxScoreSel = 0x0 <br /> HWRdDqCalVREFMin = 0xb0 <br /> HWRdDqCalVREFNumPoints = 0x6 <br /> HWRdDqCalVREFScoreMinSel = 0x0 <br /> HWRdDqCalVREFStaticSel = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscaRdWrDqCal_HWWrDqCalVREFControl(n) = 0x02200061<br /> HWWrDqCalVREFEnable = 0x1 <br /> HWWrDqCalVREFMax = 0x20 <br /> HWWrDqCalVREFMaxOffsetScaleFactor = 0x2 <br /> HWWrDqCalVREFMaxScoreSel = 0x0 <br /> HWWrDqCalVREFMin = 0x0 <br /> HWWrDqCalVREFNumPoints = 0x6 <br /> HWWrDqCalVREFScoreMinSel = 0x0 <br /> HWWrDqCalVREFStaticSel = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
|
|
<h4>16. Enable other features</h4>
|
|
<p><br /> </p>
|
|
<table class="section">
|
|
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
|
|
</tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn on the freq change waiting for refresh and self-refresh exit feature </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_arefparam(n) = 0x0d012019<br /> FreqChngWaitThr = 0x1 <br /> PhyUpdWaitRefresh = 0x1 <br /> PhyUpdWaitThr = 0x1 <br /> PhyUpdWaittXSR = 0x0 <br /> PreFreqChngWaitThr = 0x2 <br /> RefAssertCnt = 0xd <br /> SRExitRefCnt = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable periodic ZQC. (Optional) <br /> Note the ZqCalIntrvl setting shown here is based on tREFI=3.9us and the target interval is ~128ms (max supported value). The actual setting may vary depending on the DRAM and the system. </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramcfg_odtszqc(n) = 0xc0000000<br /> DerateParamSRExit = 0x0 <br /> OdtsRdIntrvl = 0x0 <br /> SRExitZQCChnlQuiet = 0x1 <br /> ShareZQRes = 0x0 <br /> TempDrtEn = 0x0 <br /> ZQCChnlQuiet = 0x0 <br /> ZQCStack = 0x1 <br /> ZqCalIntrvl = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramcfg_odtszqc(n) = 0xc0001000<br /> DerateParamSRExit = 0x0 <br /> OdtsRdIntrvl = 0x0 <br /> SRExitZQCChnlQuiet = 0x1 <br /> ShareZQRes = 0x0 <br /> TempDrtEn = 0x1 <br /> ZQCChnlQuiet = 0x0 <br /> ZQCStack = 0x1 <br /> ZqCalIntrvl = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn on the QBR enables. </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_mcusch_qbren(n) = 0x0000000d<br /> ErlyQbrEn = 0x1 <br /> LateQbrEn = 0x1 <br /> MifQbrEn = 0x1 <br /> PredictiveM2AReq = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_arefen_freq3(n) = 0x10100000<br /> ARpbEn_freq3 = 0x0 <br /> HiTempRefRnkAgeOut_freq3 = 0x1 <br /> RefCntrHiWaterMark_freq3 = 0x1 <br /> RefCntrLoWaterMark_freq3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_arefen_freq2(n) = 0x10000000<br /> ARpbEn_freq2 = 0x0 <br /> HiTempRefRnkAgeOut_freq2 = 0x0 <br /> RefCntrHiWaterMark_freq2 = 0x1 <br /> RefCntrLoWaterMark_freq2 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_arefen_freq1(n) = 0x10010000<br /> ARpbEn_freq1 = 0x1 <br /> HiTempRefRnkAgeOut_freq1 = 0x0 <br /> RefCntrHiWaterMark_freq1 = 0x1 <br /> RefCntrLoWaterMark_freq1 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn on auto refresh. </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcx_dramcfg_arefen_freq0(n) = 0x1011013f<br /> ARpbEn_freq0 = 0x1 <br /> AutoRefEn = 0x1 <br /> AutoRefSchEn = 0x1 <br /> DisableHiTempREFab = 0x1 <br /> EarlyCasAgeOut = 0x0 <br /> HiPriREFpbPch = 0x1 <br /> HiTempRefRnkAgeOut_freq0 = 0x1 <br /> REFpb2bank = 0x0 <br /> REFpbEarlyPch = 0x1 <br /> RefCntrHiWaterMark_freq0 = 0x1 <br /> RefCntrLoWaterMark_freq0 = 0x0 <br /> RefOpptEn = 0x1 <br /> tREFBWREFpb = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_B0_DYN_ISEL_ASRTIME(n) = 0x00000019<br /> rcvr_minisel_assrttime_f0 = 0x19 <br /> rcvr_minisel_assrttime_f1 = 0x0 <br /> rcvr_minisel_assrttime_f2 = 0x0 <br /> rcvr_minisel_assrttime_f3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amph_CFGH_B0_DYN_ISEL(n) = 0x00000001<br /> dyn_isel_ctrl_en_f0 = 0x1 <br /> dyn_isel_ctrl_en_f1 = 0x0 <br /> dyn_isel_ctrl_en_f2 = 0x0 <br /> dyn_isel_ctrl_en_f3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
|
|
<h4>17. Enable the Fast Critical Word Forwarding feature (optional)</h4>
|
|
<p><br /> </p>
|
|
<table class="section">
|
|
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
|
|
</tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Configure the MIF FCWF pull- in cycles. <br /> (Here we just use 0x8 as an example, please refer to register description for the valid programming range and refer to performance simulation results) </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_mcusch_qbrparam(n) = 0x00000000<br /> RdCwfEarlyCyc_freq0 = 0x0 <br /> RdCwfEarlyCyc_freq1 = 0x0 <br /> RdCwfEarlyCyc_freq2 = 0x0 <br /> RdCwfEarlyCyc_freq3 = 0x0 <br /> RdRemEarlyCyc_freq0 = 0x0 <br /> RdRemEarlyCyc_freq1 = 0x0 <br /> RdRemEarlyCyc_freq2 = 0x0 <br /> RdRemEarlyCyc_freq3 = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_mcusch_qbrparam(n) = 0x000000a8<br /> RdCwfEarlyCyc_freq0 = 0x8 <br /> RdCwfEarlyCyc_freq1 = 0x0 <br /> RdCwfEarlyCyc_freq2 = 0x0 <br /> RdCwfEarlyCyc_freq3 = 0x0 <br /> RdRemEarlyCyc_freq0 = 0xa <br /> RdRemEarlyCyc_freq1 = 0x0 <br /> RdRemEarlyCyc_freq2 = 0x0 <br /> RdRemEarlyCyc_freq3 = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn on the PredictiveM2AReq feature in MIF. (The other Qbr enables are turned on here, but not related to CWF feature) </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
|
|
<tr><td class="programming"> amcx_mcusch_qbren(n) = 0x0000000d<br /> ErlyQbrEn = 0x1 <br /> LateQbrEn = 0x1 <br /> MifQbrEn = 0x1 <br /> PredictiveM2AReq = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_mcusch_qbren(n) = 0x0000000f<br /> ErlyQbrEn = 0x1 <br /> LateQbrEn = 0x1 <br /> MifQbrEn = 0x1 <br /> PredictiveM2AReq = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcc_mcccfg_MccGen = 0x00000126<br /> DramAccessEn = 0x1 <br /> EccEn = 0x1 *read-only<br /> HitBypassEcc = 0x0 *read-only<br /> MccEn = 0x0 *read-only<br /> MccRamEn = 0x1 <br /> MccRamEnLock = 0x0 <br /> MccStop = 0x0 <br /> SpecRdEn = 0x0 <br /> SpecRdNum = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcc_amccperfcntr_Mcc0QPropCtrl = 0x300011a2<br /> Mcc0AfCacheRdPropQCmd = 0x1 *read-only<br /> Mcc0AfCacheRdPropQTrakEnbl = 0x0 *read-only<br /> Mcc0AfDramRdPropQCmd = 0x1 <br /> Mcc0AfDramRdPropQTrakEnbl = 0x0 <br /> Mcc0DpPropQCfg = 0x0 <br /> Mcc0DpPropQCmd = 0x1 <br /> Mcc0DpPropQTrakEnbl = 0x0 <br /> Mcc0MsqQPropCfg = 0x0 <br /> Mcc0MsqQPropQCmd = 0x0 <br /> Mcc0MsqQPropTrakEnbl = 0x0 <br /> Mcc0QpropOutSel = 0x3 <br /> Mcc0TpPropQCmd = 0x0 <br /> Mcc0TpPropQTrakEnbl = 0x1 <br /> Mcc0TpQPropSel = 0x4 <br /> Mcc0TpQpropMask = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcc_amccperfcntr_Mcc1QPropCtrl = 0x300011a2<br /> Mcc1AfCacheRdPropQCmd = 0x1 *read-only<br /> Mcc1AfCacheRdPropQTrakEnbl = 0x0 *read-only<br /> Mcc1AfDramRdPropQCmd = 0x1 <br /> Mcc1AfDramRdPropQTrakEnbl = 0x0 <br /> Mcc1DpPropQCfg = 0x0 <br /> Mcc1DpPropQCmd = 0x1 <br /> Mcc1DpPropQTrakEnbl = 0x0 <br /> Mcc1MsqQPropCfg = 0x0 <br /> Mcc1MsqQPropQCmd = 0x0 <br /> Mcc1MsqQPropTrakEnbl = 0x0 <br /> Mcc1QpropOutSel = 0x3 <br /> Mcc1TpPropQCmd = 0x0 <br /> Mcc1TpPropQTrakEnbl = 0x1 <br /> Mcc1TpQPropSel = 0x4 <br /> Mcc1TpQpropMask = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
|
|
<h4>18. Enable Power & ClockGating features and Configure the MCC and Global Timer</h4>
|
|
<p><br /> </p>
|
|
<table class="section">
|
|
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
|
|
</tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable AMPCA Fixed MCLK Clock Gating </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsca_ampscagen_ampclk(n) = 0x00000000<br /> FMClkIdleDetectEn = 0x0 <br /> ForceDRAMClkEn = 0x0 <br /> ForceDiv2MClkTopGaterOn = 0x0 <br /> ForceFMClkWakeUp = 0x0 <br /> ForceMClkWakeUp = 0x0 <br /> TopClkGateDis = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable AMPDQ Fixed MCLK Clock Gating </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> ampsdq_ampsdqgen_ampclk(n) = 0x00000000<br /> FMClkIdleDetectEn = 0x0 <br /> ForceDRAMClkEn = 0x0 <br /> ForceDiv2MClkTopGaterOn = 0x0 <br /> ForceFMClkWakeUp = 0x0 <br /> ForceMClkWakeUp = 0x0 <br /> TopClkGateDis = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> spllctrl_SpllCtrl_MDLLPwrDnCfg0(n) = 0x00000001<br /> Freq3_en = 0x1 <br /> powergating_en = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > disable dynamic power-down. </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramcfg_pwrmngten(n) = 0x00000132<br /> AutoSR = 0x1 <br /> DynPwrDnEn = 0x0 <br /> McPhyUpdDramClkOff = 0x0 <br /> PwrDnClkOff = 0x1 <br /> SRClkOff = 0x1 <br /> SRExitOpt = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramcfg_pwrmngten(n) = 0x00000132<br /> AutoSR = 0x1 <br /> DynPwrDnEn = 0x0 <br /> McPhyUpdDramClkOff = 0x0 <br /> PwrDnClkOff = 0x1 <br /> SRClkOff = 0x1 <br /> SRExitOpt = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > enable dynamic power-down for cold boot. </td>
|
|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramcfg_pwrmngten(n) = 0x00000132<br /> AutoSR = 0x1 <br /> DynPwrDnEn = 0x0 <br /> McPhyUpdDramClkOff = 0x0 <br /> PwrDnClkOff = 0x1 <br /> SRClkOff = 0x1 <br /> SRExitOpt = 0x1 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramcfg_pwrmngten(n) = 0x00000133<br /> AutoSR = 0x1 <br /> DynPwrDnEn = 0x1 <br /> McPhyUpdDramClkOff = 0x0 <br /> PwrDnClkOff = 0x1 <br /> SRClkOff = 0x1 <br /> SRExitOpt = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable wakeups from glbl timer to pmgr </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_PmgrWakeUpCfg = 0x000001ff<br /> DccEn = 0x1 <br /> FreqChngEn = 0x1 <br /> IdtEn = 0x1 <br /> ImpCalEn = 0x1 <br /> MdllEn = 0x1 <br /> RdCalEn = 0x1 <br /> VoltRampEn = 0x1 <br /> WrCalEn = 0x1 <br /> ZQCalEn = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">No</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_PreFreq2AllBankDly0 = 0x00f000f0<br /> PreFreqChng2AllBankDly_f0 = 0xf0 <br /> PreFreqChng2AllBankDly_f1 = 0xf0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_PreFreq2AllBankDly1 = 0x00f000f0<br /> PreFreqChng2AllBankDly_f2 = 0xf0 <br /> PreFreqChng2AllBankDly_f3 = 0xf0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_PreFreqChng2FreqChngDly0 = 0x02400240<br /> PreFreqChng2FreqChngDly_f0 = 0x240 <br /> PreFreqChng2FreqChngDly_f1 = 0x240 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_PreFreqChng2FreqChngDly1 = 0x02400240<br /> PreFreqChng2FreqChngDly_f2 = 0x240 <br /> PreFreqChng2FreqChngDly_f3 = 0x240 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_CalSeg2AllBank0 = 0x00fa0120<br /> CalSeg2AllBank_f0 = 0x120 <br /> CalSeg2AllBank_f1 = 0xfa <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_AllBank2CalSeg0 = 0x00fa0120<br /> AllBank2CalSeg_f0 = 0x120 <br /> AllBank2CalSeg_f1 = 0xfa <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>PALLADIUM</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_MdllTimer = 0x00000bb8<br /> MdllTimerCnt = 0xbb8 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>PALLADIUM</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_DCCTimer = 0x00000bb8<br /> DCCTimerCnt = 0xbb8 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>PALLADIUM</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_MdllVoltRampTimer = 0x0000004b<br /> MdllVoltRampTimerCnt = 0x4b <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>PALLADIUM</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_CtrlUpdMaskTimer = 0x0000000f<br /> CtrlUpdMaskTimerCnt = 0xf <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>PALLADIUM</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_RdCalTimer = 0x002dc6bb<br /> RdCalTimerCnt = 0x2dc6bb <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>PALLADIUM</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_WrCalTimer = 0x002dc6c0<br /> WrCalTimerCnt = 0x2dc6c0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>PALLADIUM</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_ZQCTimer = 0x003d0900<br /> ZQCTimerCnt = 0x3d0900 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>PALLADIUM</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_PerCal_FreqChngTimer = 0x00000001<br /> PerCal_FreqChngTimerCnt = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>PALLADIUM</b>: Skip this step </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> glbtimer_GlbTimer_ImpCalTimer = 0x00002ee0<br /> ImpCalTimerCnt = 0x2ee0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Dynamic clk pwr gating reg </td>
|
|
<td><table class="platform">
|
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<tr><td class="programming"> amcx_amcgen_amcclkpwrgate(n) = 0x050a0000<br /> ClkPwrWaitCyc = 0xa <br /> MCUBCGClkGateEn = 0x0 <br /> MCUBCGPwrGateEn = 0x0 <br /> PwrRstCyc = 0x5 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
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<h4>19. Do a ODTS read and set ODTS interval so MR4 on-die temperature sensor read occurs periodically.</h4>
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<p><br /> </p>
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<table class="section">
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<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
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</tr>
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<tr>
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<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Perform an MRR to DRAM mode register MR4 to establish a base value for ODTS reading.<br /> Another intention is to bring DRAM out of self-refresh. Done in both cold boot and resume boot. </td>
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<td><table class="platform">
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|
<tr><td class="programming"> amcx_dramcmd_mrinitcmd(n) = 0x50041100<br /> MRCmdAddr = 0x4 <br /> MRCmdCs = 0x0 <br /> MRCmdData = 0x50 <br /> MRCmdIsMPC = 0x0 <br /> MRCmdIsRd = 0x1 <br /> RunMRCmd = 0x1 <br /> RunRdLvl = 0x0 <br /> RunSRExit = 0x0 <br /> </td></tr>
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</table></td>
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<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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<tr>
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<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
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<td><table class="platform">
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|
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
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|
RunMRCmd<br />
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while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
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</td></tr>
|
|
</table></td>
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|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
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|
<tr>
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|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable periodic ODTS and temperature based refresh rate modulation. (Optional) <br /> Note the OdtsRdIntrvl setting shown here is based on tREFI=3.9us and the target interval is ~100. The actual setting may vary depending on the DRAM and the system. <br /> Palladium: this step is skipped, ODTS is not supported<br /><br /> <b>PALLADIUM</b>: Skip this step </td>
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|
<td><table class="platform">
|
|
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
|
|
<tr><td class="programming"> amcx_dramcfg_odtszqc(n) = 0xc0002320<br /> DerateParamSRExit = 0x1 <br /> OdtsRdIntrvl = 0x320 <br /> SRExitZQCChnlQuiet = 0x1 <br /> ShareZQRes = 0x0 <br /> TempDrtEn = 0x0 <br /> ZQCChnlQuiet = 0x0 <br /> ZQCStack = 0x1 <br /> ZqCalIntrvl = 0x0 <br /> </td></tr>
|
|
<tr><td style="font-weight: bold">else</td></tr>
|
|
<tr><td class="programming"> amcx_dramcfg_odtszqc(n) = 0xc0003320<br /> DerateParamSRExit = 0x1 <br /> OdtsRdIntrvl = 0x320 <br /> SRExitZQCChnlQuiet = 0x1 <br /> ShareZQRes = 0x0 <br /> TempDrtEn = 0x1 <br /> ZQCChnlQuiet = 0x0 <br /> ZQCStack = 0x1 <br /> ZqCalIntrvl = 0x0 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
|
|
<h4>Mcc Cache Initialization. This section is not part of the essential init sequence. This should be run when the system is done using the CacheAsRam</h4>
|
|
<p><br /> </p>
|
|
<table class="section">
|
|
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
|
|
</tr>
|
|
<tr>
|
|
<td class="description" valign="top" > </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcc_mcccfg_MccGen = 0x00000124<br /> DramAccessEn = 0x1 <br /> EccEn = 0x1 *read-only<br /> HitBypassEcc = 0x0 *read-only<br /> MccEn = 0x0 *read-only<br /> MccRamEn = 0x0 <br /> MccRamEnLock = 0x0 <br /> MccStop = 0x0 <br /> SpecRdEn = 0x0 <br /> SpecRdNum = 0x1 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program AF Allocation Hints, allocation does not happen unless there is a hint as the generic allocation policy </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcc_mcccfg_MccAlcHint = 0x00001110<br /> MccAlcHintEn = 0x1 *read-only<br /> MccGenericAlc = 0x0 *read-only<br /> MccSclDtyEn = 0x1 *read-only<br /> MccStickyEn = 0x1 *read-only<br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
|
|
<tr>
|
|
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > program mccgen </td>
|
|
<td><table class="platform">
|
|
<tr><td class="programming"> amcc_mcccfg_MccGen = 0x00000194<br /> DramAccessEn = 0x1 <br /> EccEn = 0x1 *read-only<br /> HitBypassEcc = 0x0 *read-only<br /> MccEn = 0x0 *read-only<br /> MccRamEn = 0x0 <br /> MccRamEnLock = 0x0 <br /> MccStop = 0x0 <br /> SpecRdEn = 0x1 <br /> SpecRdNum = 0x4 <br /> </td></tr>
|
|
</table></td>
|
|
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td>
|
|
|