66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
#ifndef PCI_PRIVATE_H
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#define PCI_PRIVATE_H
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#include <drivers/pci.h>
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struct pci_device {
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char name[16];
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uint32_t refcount;
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// This device's number on its bus
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uint8_t device_num;
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// Cached copies of config space registers
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uint16_t vendor_id;
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uint16_t device_id;
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uint32_t class_code;
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uint8_t revision_id;
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uint8_t header_type;
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bool multifunction;
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// cached copied of pcie-specific registers
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uint8_t pcie_device_port_type; // from PCIe r3 7.8.2
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// Populated in pci_bridge_probe by probing the BARs
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uint8_t num_bars;
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uint64_t bar_size[6];
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bool bar_64bit[6];
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uint64_t bar_pci_addr[6];
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uintptr_t bar_host_addr[6];
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uint16_t first_cap_offset;
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uint16_t pcie_cap_offset;
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uint16_t pm_cap_offset;
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// The bridge upstream from this device, NULL for the host bridge
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pci_device_t bridge;
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////////// bridge-specific stuff
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// Provided by the platform driver to support config reads/writes
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pci_config_read_cb_t config_read;
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pci_config_write_cb_t config_write;
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void *bridge_priv;
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// Caches of the bridge numbering config space registers. For host bridges,
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// primary_bus is ignored and secondary/subordinate_bus just track which
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// bus numbers have been vended (since host bridges don't have config space)
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uint8_t primary_bus;
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uint8_t secondary_bus;
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uint8_t subordinate_bus;
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// Tracks 32-bit memory space allocations. For now the driver will just support
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// 32-bit addresses. 64-bit addresses would be tracked in a separate range, so
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// making the type 32-bit is safe
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uint32_t memory_base;
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uint32_t memory_size;
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uint32_t memory_allocated;
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// Keep track of any devices on this bridge's bus
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struct pci_device *devices[32];
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// And of how many we've allocated
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uint32_t num_children;
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};
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#endif
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