505 lines
15 KiB
C
505 lines
15 KiB
C
/*
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* Copyright (C) 2011-2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <platform.h>
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#include <lib/libc.h>
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#include <platform/clocks.h>
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#include <platform/timer.h>
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#include <platform/soc/clocks.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/soc/chipid.h>
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#include <sys.h>
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#include <sys/boot.h>
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#include <sys/menu.h>
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#include <drivers/power.h>
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#define PLL_FREQ_TARGET(pllx) (1ULL * pllx##_O * pllx##_M / pllx##_P / (1 << pllx##_S))
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#define PRESCALE_EN(x) ((x) == 1 ? 0 : 1)
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#define CLK_DIV_N(x) ((x) == 1 ? 0 : ((x)/2)-1)
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#if APPLICATION_IBOOT
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//PLL0 @ 800MHz
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#define PLL0 0
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#define PLL0_O OSC_FREQ
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#define PLL0_P 12
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#define PLL0_M 400
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#define PLL0_S 0
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#define PLL0_VSEL 1 // High if 600MHz < Fvco < 864MHz (Fvco = Fin * M / P)
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#define PLL0_T PLL_FREQ_TARGET(PLL0)
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// PLL1 @ 330MHz
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#define PLL1 1
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#define PLL1_O OSC_FREQ
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#define PLL1_P 4
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#define PLL1_M 110
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#define PLL1_S 1
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#define PLL1_VSEL 1 // High if 600MHz < Fvco < 864MHz (Fvco = Fin * M / P)
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#define PLL1_T PLL_FREQ_TARGET(PLL1)
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// PLL2 @ 432MHz
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#define PLL2 2
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#define PLL2_O OSC_FREQ
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#define PLL2_P 5
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#define PLL2_M 180
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#define PLL2_S 1
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#define PLL2_VSEL 1 // High if 600MHz < Fvco < 864MHz (Fvco = Fin * M / P)
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#define PLL2_T PLL_FREQ_TARGET(PLL2432/)
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#define LOW_PERF_DIV_N (11)
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#define MEDIUM_PERF_DIV_N (5)
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#define MEMORY_PERF_DIV_N (2)
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// With PLL0 @ 800MHz for B0, SCLK_DIV_VAL needs to be at least 2!
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#define HIGH_PERF_DIV_N (2)
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#endif /* APPLICATION_IBOOT */
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#if APPLICATION_SECUREROM
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#define PLL0 0
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#define PLL0_O OSC_FREQ
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#define PLL0_P 6
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#define PLL0_M 133
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#define PLL0_S 2
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#define PLL0_VSEL 0
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#define PLL0_T PLL_FREQ_TARGET(PLL0)
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#define LOW_PERF_DIV_N (1)
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#define MEDIUM_PERF_DIV_N (1)
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#define MEMORY_PERF_DIV_N (2)
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#define HIGH_PERF_DIV_N (1)
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#endif /* APPLICATION_SECUREROM */
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#define SCLK_PLL 0
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#define FCLK_DIV_N (1)
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#define DCLK_DIV_N (1)
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#define ACLK_DIV_N (MEMORY_PERF_DIV_N)
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#define HCLK_DIV_N (MEMORY_PERF_DIV_N)
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#define PCLK_DIV_N (MEMORY_PERF_DIV_N)
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#define NCLK_DIV_N (1)
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/* current clock speeds */
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static u_int32_t clks[CLKGEN_CLK_COUNT];
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static u_int32_t *plls = &clks[CLKGEN_CLK_PLL0];
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static u_int32_t perf_level;
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static u_int32_t perf_div;
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static u_int32_t get_pll(int pll);
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int clocks_init(void)
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{
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#if APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC)
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#if SUPPORT_FPGA
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clks[CLKGEN_CLK_SCLK] = 10000000;
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clks[CLKGEN_CLK_FCLK] = 10000000;
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clks[CLKGEN_CLK_DCLK] = 10000000;
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clks[CLKGEN_CLK_ACLK] = 10000000;
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clks[CLKGEN_CLK_HCLK] = 10000000;
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clks[CLKGEN_CLK_PCLK] = 10000000;
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clks[CLKGEN_CLK_NCLK] = 10000000;
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clks[CLKGEN_CLK_USBPHY] = 12000000;
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perf_div = 1;
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perf_level = kPerformanceHigh;
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#else
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#error "The calculations of vclk0 and vclk1 need to be scrubbed"
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int cnt;
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int sclk_pll = ((rCLKCON0 >> 12) & 3) - 1;
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int sclk_div_n = ((rCLKCON0 >> 0) & 0xF) + 1;
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int fclk_div_n = ((rCLKCON1 >> 29) & 1) ? ((((rCLKCON1 >> 24) & 0x1F) + 1) * 2) : 1;
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int dclk_div_n = ((rCLKCON1 >> 23) & 1) ? ((((rCLKCON1 >> 18) & 0x1F) + 1) * 2) : 1;
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int hclk_div_n = ((rCLKCON1 >> 17) & 1) ? ((((rCLKCON1 >> 12) & 0x1F) + 1) * 2) : 1;
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int pclk_div_n = ((rCLKCON1 >> 11) & 1) ? ((((rCLKCON1 >> 6) & 0x1F) + 1) * 2) : 1;
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int aclk_div_n = ((rCLKCON1 >> 5) & 1) ? ((((rCLKCON1 >> 0) & 0x1F) + 1) * 2) : 1;
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int vclk0_pll = ((rCLKCON2 >> 28) & 3) - 1;
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int vclk0_div_n = ((rCLKCON2 >> 16) & 0xF) + 1;
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int vclk1_pll = ((rCLKCON2 >> 12) & 3) - 1;
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int vclk1_div_n = (((rCLKCON2 >> 0) & 0xF) + 1) * (((rCLKCON2 >> 4) & 0xF) + 1);
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plls[-1] = OSC_FREQ;
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for (cnt = 0; cnt < 3; cnt++) plls[cnt] = get_pll(cnt);
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perf_div = sclk_div_n;
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switch (perf_div) {
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default :
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case HIGH_PERF_DIV_N : perf_level = kPerformanceHigh; break;
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case MEDIUM_PERF_DIV_N : perf_level = kPerformanceMedium; break;
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case LOW_PERF_DIV_N : perf_level = kPerformanceLow; break;
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}
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clks[CLKGEN_CLK_SCLK] = plls[sclk_pll] / HIGH_PERF_DIV_N;
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clks[CLKGEN_CLK_FCLK] = clks[CLKGEN_CLK_SCLK] / fclk_div_n;
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clks[CLKGEN_CLK_DCLK] = clks[CLKGEN_CLK_SCLK] / dclk_div_n;
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clks[CLKGEN_CLK_ACLK] = clks[CLKGEN_CLK_SCLK] / aclk_div_n;
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clks[CLKGEN_CLK_HCLK] = clks[CLKGEN_CLK_SCLK] / hclk_div_n;
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clks[CLKGEN_CLK_PCLK] = clks[CLKGEN_CLK_SCLK] / pclk_div_n;
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clks[CLKGEN_CLK_VCLK0] = plls[vclk0_pll] / vclk0_div_n;
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clks[CLKGEN_CLK_VCLK1] = plls[vclk1_pll] / vclk1_div_n;
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clks[CLKGEN_CLK_NCLK] = OSC_FREQ;
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clks[CLKGEN_CLK_USBPHY] = OSC_FREQ;
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#endif
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#endif /* APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC) */
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return 0;
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}
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static u_int32_t get_pll(int pll)
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{
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volatile u_int32_t *pllpms;
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u_int32_t pllcon, pms;
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u_int64_t freq;
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pllcon = rPLLCON;
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if (((pllcon >> pll) & 1) == 0) return OSC_FREQ;
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switch (pll) {
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case 0:
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pllpms = &rPLL0PMS;
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break;
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case 1:
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pllpms = &rPLL1PMS;
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break;
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case 2:
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pllpms = &rPLL2PMS;
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break;
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case 3:
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pllpms = &rPLL3PMS;
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break;
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default:
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return 0;
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break;
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}
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freq = OSC_FREQ;
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pms = *pllpms;
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freq *= (pms >> 8) & 0x3FF; // *M
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freq /= (pms >> 24) & 0x3F; // /P
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freq /= 1 << (pms & 0x07); // /2^S
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return freq;
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}
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static void set_pll(int pll, u_int32_t p, u_int32_t m, u_int32_t s, u_int32_t vsel)
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{
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volatile u_int32_t *pllpms;
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volatile u_int32_t *plllcnt;
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switch (pll) {
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case 0:
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pllpms = &rPLL0PMS;
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plllcnt = &rPLL0LCNT;
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break;
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case 1:
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pllpms = &rPLL1PMS;
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plllcnt = &rPLL1LCNT;
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break;
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case 2:
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pllpms = &rPLL2PMS;
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plllcnt = &rPLL2LCNT;
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break;
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case 3:
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pllpms = &rPLL3PMS;
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plllcnt = &rPLL3LCNT;
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break;
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default:
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return;
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}
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*pllpms = (vsel << 30) | (p << 24) | (m << 8) | (s << 0); // set p/m/s values
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*plllcnt = 300 * 24; // set lock counter for 300us
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rPLLCON |= (1<<(0+pll)); // pll power up
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#if !SUPPORT_FPGA
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while ((rPLLLOCK & (1 << pll)) == 0); // wait for pll to lock
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#endif /* ! SUPPORT_FPGA */
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*pllpms = (vsel << 30) | (p << 24) | (m << 8) | (s << 0); // set p/m/s values again
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rPLLCON |= (1<<(16+pll)); // pll select output
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}
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int clocks_set_default(void)
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{
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uint32_t cnt;
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/* Change all the clocks to something safe */
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clocks_quiesce();
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/* set up the clock tree to our default setting */
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clks[CLKGEN_CLK_OSC] = OSC_FREQ;
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#ifdef PLL0_T
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set_pll(0, PLL0_P, PLL0_M, PLL0_S, PLL0_VSEL);
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#endif
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#ifdef PLL1_T
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set_pll(1, PLL1_P, PLL1_M, PLL1_S, PLL2_VSEL);
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#endif
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#ifdef PLL2_T
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set_pll(2, PLL2_P, PLL2_M, PLL2_S, PLL2_VSEL);
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#endif
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#ifdef PLL3_T
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set_pll(3, PLL3_P, PLL3_M, PLL3_S, PLL3_VSEL);
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#endif
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// Use get_pll() to establish the frequencies (unconfigured PLLs will bypass OSC)
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for (cnt = 0; cnt < 4; cnt++) plls[cnt] = get_pll(cnt);
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perf_level = kPerformanceHigh;
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perf_div = HIGH_PERF_DIV_N;
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clks[CLKGEN_CLK_SCLK] = plls[SCLK_PLL] / perf_div;
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clks[CLKGEN_CLK_FCLK] = clks[CLKGEN_CLK_SCLK] / FCLK_DIV_N;
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clks[CLKGEN_CLK_DCLK] = clks[CLKGEN_CLK_SCLK] / DCLK_DIV_N;
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clks[CLKGEN_CLK_ACLK] = clks[CLKGEN_CLK_SCLK] / ACLK_DIV_N;
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clks[CLKGEN_CLK_HCLK] = clks[CLKGEN_CLK_SCLK] / HCLK_DIV_N;
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clks[CLKGEN_CLK_PCLK] = clks[CLKGEN_CLK_SCLK] / PCLK_DIV_N;
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clks[CLKGEN_CLK_NCLK] = clks[CLKGEN_CLK_OSC] / NCLK_DIV_N;
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clks[CLKGEN_CLK_USBPHY] = clks[CLKGEN_CLK_OSC];
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// switch the useful clocks back to their plls
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rCLKCON1 =
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(PRESCALE_EN(FCLK_DIV_N)<<29)|(CLK_DIV_N(FCLK_DIV_N)<<24) | // FCLK
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(PRESCALE_EN(DCLK_DIV_N)<<23)|(CLK_DIV_N(DCLK_DIV_N)<<18) | // DCLK
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(PRESCALE_EN(HCLK_DIV_N)<<17)|(CLK_DIV_N(HCLK_DIV_N)<<12) | // HCLK
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(PRESCALE_EN(PCLK_DIV_N)<<11)|(CLK_DIV_N(PCLK_DIV_N)<< 6) | // PCLK
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(PRESCALE_EN(ACLK_DIV_N)<< 5)|(CLK_DIV_N(ACLK_DIV_N)<< 0); // ACLK
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// must set divider before switching to PLL because of delay in divider taking effect
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// <rdar://problem/11951206> Race condition in CLKCON register setting causes unpredictable behavior
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rCLKCON0 = ((perf_div-1)<<0);
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rCLKCON0 |= ((SCLK_PLL+1)<<12);
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rCLKCON2 = (0<<15)|(1<<31); // CLK_OUT0 enable, CLK_OUT1 disable
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rCLKCON3 = (1<<31)|(2<<28)|(7<<16) // VCLK_DAC source PLL2, div 7+1, disable
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| (1<<15)|(3<<12)|(0<<4)|(0<<0); // RGBOUT_CLK source PLL3, div 1, disable
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rCLKCON4 = (1<<31)|(0<<28)|(0<<16) // MCLK1 source OSC, div 1, disable
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|(1<<15)|(3<<12)|(0<<4)|(0<<0); // MCLK0 source PLL3, div 1, disable
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rCLKCON5 = (1<<31)|(0<<28)|(0<<16) // MCLK3 source OSC, div 1, disable
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|(1<<15)|(0<<12)|(0<<0); // MCLK2 source OSC, div 1, disable
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rCLKCON6 = (0<<28)|((NCLK_DIV_N-1)<<16) // NCLK source OSC, enable
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|(1<<15)|(2<<12); // MFC_CLK source PLL1, div 0+1, disable
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rCLKCON7 = (0x1F<<27)|(1<<24)|(3<<16) // VMHCLKx source PLL0, div 3+1, disable
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|(1<<15)|(1<<12)|(2<<0); // SCALER source PLL0, div 2+1, disable
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#if SUPPORT_FPGA
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clks[CLKGEN_CLK_SCLK] = 10000000;
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clks[CLKGEN_CLK_FCLK] = 10000000;
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clks[CLKGEN_CLK_DCLK] = 10000000;
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clks[CLKGEN_CLK_ACLK] = 10000000;
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clks[CLKGEN_CLK_HCLK] = 10000000;
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clks[CLKGEN_CLK_PCLK] = 10000000;
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clks[CLKGEN_CLK_NCLK] = 10000000;
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clks[CLKGEN_CLK_USBPHY] = 12000000;
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#endif
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return 0;
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}
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void clocks_quiesce(void)
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{
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// Turn off non-critical device clocks
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rCGCON0 = 0x00001CBF; // HCLK to VROM
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rCGCON1 = 0x3FC5EFFF; // PCLKs to DREX, Timer64, Cortex-A5 Debug and Sys, AXI, and GPIO
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rCGCON2 = 0x0000001F;
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rCGCON3 = 0x00000000; // ACLKs to AXI, XMC, and SRAM
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rCGCON4 = 0x003DFEFF; // NCLK to DREX and Timer64 on
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// Set OSC to select the 12/24MHz clock
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//rPLLCON &= ~(1 << 8); // FIXME
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// Set all of the clocks to use OSC bypass.
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// Disable the clocks that will not be used.
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rCLKCON0 &= ~(0x3<<12); // Use OSC bypass for SCLK ahead of turning off divider
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rCLKCON0 = (1<<30); // MCLK disable, SCLK enable, use OSC bypass, disable prescalar
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rCLKCON1 = 0; // FCLK/HCLK/PCLK/ACLK enable, use OSC bypass, disable prescalar
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rCLKCON2 = (1<<31)|(1<<15); // CLK_OUT1/CLK_OUT0 disable
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rCLKCON3 = (1<<31)|(1<<15); // VCLK_DAC/RGBOUT_VCLK disable
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rCLKCON4 = (1<<31)|(1<<15); // MCLK1/MCLK0 disable
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rCLKCON5 = (1<<31)|(1<<15); // MCLK3/MCLK2 disable
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rCLKCON6 = (1<<15); // NCLK enable, MFC_CLK disable
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rCLKCON7 = (0x1F<<27)|(1<<15); // VMHCLKx/SCALER disable
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// Bypass and shut down all PLLs
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rPLLCON &= ~0xF0000;
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rPLLCON &= ~0x0000F;
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}
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u_int32_t clocks_get_performance_divider(void)
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{
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return perf_div;
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}
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u_int32_t clocks_set_performance(u_int32_t performance_level)
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{
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u_int32_t old_perf_level = perf_level;
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switch (performance_level) {
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default : performance_level = kPerformanceHigh;
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case kPerformanceHigh: perf_div = HIGH_PERF_DIV_N; break;
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case kPerformanceMedium: perf_div = MEDIUM_PERF_DIV_N; break;
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case kPerformanceLow: perf_div = LOW_PERF_DIV_N; break;
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case kPerformanceMemory :
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if (old_perf_level == kPerformanceHigh) goto done;
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perf_div = MEMORY_PERF_DIV_N;
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break;
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}
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perf_level = performance_level;
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if (old_perf_level == kPerformanceMemory) {
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rCLKCON1 =
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(PRESCALE_EN(HCLK_DIV_N)<<22)|(CLK_DIV_N(HCLK_DIV_N)<<17) | // HCLK
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(PRESCALE_EN(PCLK_DIV_N)<<14)|(CLK_DIV_N(PCLK_DIV_N)<< 9) | // PCLK
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(PRESCALE_EN(ACLK_DIV_N)<< 6)|(CLK_DIV_N(ACLK_DIV_N)<< 1); // ACLK
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}
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rCLKCON0 = (rCLKCON0 & ~0xF) | ((perf_div - 1) & 0xF);
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if (perf_level == kPerformanceMemory) {
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rCLKCON1 =
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(PRESCALE_EN(1)<<22)|(CLK_DIV_N(1)<<17) | // HCLK
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(PRESCALE_EN(1)<<14)|(CLK_DIV_N(1)<< 9) | // PCLK
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(PRESCALE_EN(1)<< 6)|(CLK_DIV_N(1)<< 1); // ACLK
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}
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done:
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return old_perf_level;
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}
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u_int32_t clock_get_frequency(int clock)
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{
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switch (clock) {
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case CLK_CPU:
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case CLK_FCLK:
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return clks[CLKGEN_CLK_FCLK];
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case CLK_DCLK:
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case CLK_MEM:
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return clks[CLKGEN_CLK_DCLK];
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case CLK_ACLK:
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return clks[CLKGEN_CLK_ACLK];
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case CLK_HCLK:
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case CLK_BUS:
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return clks[CLKGEN_CLK_HCLK];
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case CLK_PERIPH:
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case CLK_PCLK:
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return clks[CLKGEN_CLK_PCLK];
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case CLK_NCLK:
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case CLK_FIXED:
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return clks[CLKGEN_CLK_NCLK];
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case CLK_TIMEBASE:
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#if SUPPORT_FPGA
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// <rdar://problem/10442644> Rig clock frequency data for G1 FPGA
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return clks[CLKGEN_CLK_NCLK] / 2;
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#else
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return clks[CLKGEN_CLK_NCLK];
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#endif
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|
case CLK_USBPHYCLK:
|
|
return clks[CLKGEN_CLK_USBPHY];
|
|
case CLK_MCLK:
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
void platform_reset(bool panic)
|
|
{
|
|
#if WITH_BOOT_STAGE
|
|
if (!panic) boot_set_stage(kPowerNVRAMiBootStageOff);
|
|
#endif
|
|
|
|
/* reset ourselves */
|
|
wdt_chip_reset();
|
|
|
|
while (1);
|
|
}
|
|
|
|
|
|
void platform_system_reset(bool panic)
|
|
{
|
|
dprintf(DEBUG_INFO, "no platform system reset, using normal reset\n");
|
|
platform_reset(panic);
|
|
}
|
|
|
|
struct clock_gate_entry {
|
|
u_int32_t gccon0_mask;
|
|
u_int32_t gccon1_mask;
|
|
u_int32_t gccon2_mask;
|
|
u_int32_t gccon3_mask;
|
|
u_int32_t gccon4_mask;
|
|
};
|
|
|
|
static const struct clock_gate_entry clock_gate_map[] =
|
|
{
|
|
[CLK_AES] = { 0x00000080, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
|
[CLK_CHIPID] = { 0x00000000, 0x00020000, 0x00000000, 0x00000000, 0x00000000 },
|
|
[CLK_DMAC0] = { 0x00000800, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
|
[CLK_DMAC1] = { 0x00001000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
|
[CLK_GPIO] = { 0x00000000, 0x00001000, 0x00000000, 0x00000000, 0x00000000 },
|
|
[CLK_IIC0] = { 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00001000 },
|
|
[CLK_IIC1] = { 0x00000000, 0x00000020, 0x00000000, 0x00000000, 0x00002000 },
|
|
[CLK_IIC2] = { 0x00000000, 0x00000040, 0x00000000, 0x00000000, 0x00004000 },
|
|
[CLK_PKE] = { 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000 },
|
|
[CLK_SHA1] = { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
|
[CLK_SPI0] = { 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00008000 },
|
|
[CLK_SPI1] = { 0x00000000, 0x00000008, 0x00000000, 0x00000000, 0x00010000 },
|
|
[CLK_TIMER] = { 0x00000000, 0x7FC00000, 0x00000000, 0x00000000, 0x000001FF },
|
|
[CLK_UART0] = { 0x00000000, 0x00002000, 0x00000000, 0x00000000, 0x00000200 },
|
|
[CLK_UART1] = { 0x00000000, 0x00004000, 0x00000000, 0x00000000, 0x00000400 },
|
|
[CLK_UART2] = { 0x00000000, 0x00008000, 0x00000000, 0x00000000, 0x00000800 },
|
|
[CLK_USBOTG0] = { 0x00000004, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
|
[CLK_USBOTG1] = { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
|
[CLK_USBPHY] = { 0x00000020, 0x00000800, 0x00000000, 0x00000000, 0x00000000 },
|
|
[CLK_ROSC] = { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 },
|
|
};
|
|
#define CLOCK_GATE_MAP_COUNT (sizeof(clock_gate_map) / sizeof(struct clock_gate_entry))
|
|
|
|
void clock_gate(int device, bool enable)
|
|
{
|
|
const struct clock_gate_entry *entry = 0;
|
|
|
|
if (device > (int)CLOCK_GATE_MAP_COUNT)
|
|
panic("Invalid clock gate");
|
|
|
|
entry = &clock_gate_map[device];
|
|
|
|
if (enable) {
|
|
rCGCON0 &= ~entry->gccon0_mask;
|
|
rCGCON1 &= ~entry->gccon1_mask;
|
|
rCGCON2 &= ~entry->gccon2_mask;
|
|
rCGCON3 &= ~entry->gccon3_mask;
|
|
rCGCON4 &= ~entry->gccon4_mask;
|
|
} else {
|
|
rCGCON0 |= entry->gccon0_mask;
|
|
rCGCON1 |= entry->gccon1_mask;
|
|
rCGCON2 |= entry->gccon2_mask;
|
|
rCGCON3 |= entry->gccon3_mask;
|
|
rCGCON4 |= entry->gccon4_mask;
|
|
}
|
|
}
|
|
|