136 lines
3.1 KiB
C
136 lines
3.1 KiB
C
/*
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* Copyright (C) 2010-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <drivers/amc/amc.h>
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#include <drivers/amc/amc_phy.h>
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#include <drivers/amc/amc_regs.h>
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#include <drivers/dram.h>
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#include <drivers/miu.h>
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#include <sys.h>
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int mcu_initialize_dram (bool resume)
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{
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return amc_init(resume);
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}
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void mcu_bypass_prep (int step)
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{
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amc_phy_bypass_prep(step);
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}
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uint64_t mcu_get_memory_size (void)
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{
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return amc_get_memory_size();
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}
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void amc_configure_address_decoding_and_mapping (void)
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{
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amc_configure_default_address_decoding_and_mapping();
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}
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void amc_enable_slow_boot (bool enable)
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{
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int slow_freqsel;
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if (enable) {
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if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
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rAMC_FREQSEL = amc_params.freqsel;
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return;
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}
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slow_freqsel = 3;
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rAMC_BOOTCLK = (amc_params.bootclkdivsr << 8) | 1;
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spin(5);
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rAMC_FREQSEL = slow_freqsel;
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amc_phy_scale_dll(slow_freqsel, amc_params.bootclkdivsr);
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} else {
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if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
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return;
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}
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rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_small;
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spin(2);
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rAMC_BOOTCLK &= ~1;
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spin(5);
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rAMC_FREQSEL = amc_params.freqsel;
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amc_phy_scale_dll(amc_params.freqsel, 1);
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rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_guided;
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}
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}
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void amc_finalize (bool resume)
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{
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uint8_t odts;
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#if SUPPORT_FPGA
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rAMC_PWRMNGTEN |= 0x00000001; // Sharing clocks between channels so do not enable clock stopping for PD or SR
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#else
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rAMC_PWRMNGTEN |= 0x00011011;
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#endif
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rAMC_AREFPARAM |= (0x00001000); // Turn on freq change waiting for refresh and self-refresh exit
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amc_mrcmd(MR_READ, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x4, (uintptr_t)&odts);
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rAMC_ODTS = 0x00010320; // [16] => TempDrtEn, [9:0] RdIntrvl XXX based on tREFI
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if (!resume) {
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amc_enable_autorefresh();
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}
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#if SUPPORT_FPGA
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rAMC_FREQSEL = amc_params.freqsel;
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#endif
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#if !SUPPORT_FPGA
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// Turn of Fast Critical Word Forwarding feature and AIU CWF feature
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// Disabled for NRT <rdar://problem/9416881>
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rAMC_AIUPRT_RD_CWF = 0x00161600;
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rAMC_QBRPARAM = 0x00810000;
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rAMC_QBREN = 0x00111001;
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#endif
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}
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void amc_dram_workarounds (bool resume)
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{
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// XXX - Possibly look in s5l8950x amc.c to see possible workarounds.
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return;
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}
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// Shift dq offset as needed.
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// In the future, it's possible the shift value changes based on SOC or DRAM vendor.
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// Thus, we need to have this function per SOC.
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void amc_dram_shift_dq_offset (int8_t *dq_offset, uint8_t num_bytes) {
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int8_t shift_val;
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uint8_t i;
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const struct amc_memory_device_info *dev_info;
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dev_info = amc_get_memory_device_info();
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switch (dev_info->vendor_id) {
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case JEDEC_MANUF_ID_HYNIX:
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case JEDEC_MANUF_ID_SAMSUNG:
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case JEDEC_MANUF_ID_ELPIDA:
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// shift 2 steps
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shift_val = -2;
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break;
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default:
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shift_val = 0;
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break;
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}
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for (i = 0; i < num_bytes; i++)
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dq_offset[i] += shift_val;
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}
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