232 lines
6.2 KiB
C
232 lines
6.2 KiB
C
/*
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* Copyright (C) 2009-2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <lib/env.h>
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#include <platform.h>
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#include <platform/soc/chipid.h>
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#include <platform/soc/hwclocks.h>
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#if SUPPORT_FPGA
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#define _rCFG_FUSE0 (*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x00))
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#undef rCFG_FUSE0
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// XXX ECID (1 << 7)?
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// XXX double-check memory values
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#define rCFG_FUSE0 ((0 << 31) | (3 << 28) | (0xE << 24) | (2 << 22) | \
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(0 << 9) | (1 << 8) | (3 << 4) | (kPlatformSecurityDomainDarwin << 2) | (0 << 1) | (0 << 0) | \
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_rCFG_FUSE0)
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#endif
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#if SUB_PLATFORM_S5L8945X
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#define DEFAULT_SOC_VOLTAGE_LOW 1000
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#define DEFAULT_SOC_VOLTAGE_MED 1100
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#define DEFAULT_SOC_VOLTAGE_HIGH 1200
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#define DEFAULT_CPU_VOLTAGE_LOW 1000
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#define DEFAULT_CPU_VOLTAGE_MED 1150
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#define DEFAULT_CPU_VOLTAGE_HIGH 1250
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#define BASE_SOC_VOLTAGE_LOW 875
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#define BASE_SOC_VOLTAGE_MED 975
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#define BASE_SOC_VOLTAGE_HIGH 1075
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#define BASE_CPU_VOLTAGE_LOW 875
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#define BASE_CPU_VOLTAGE_MED 975
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#define BASE_CPU_VOLTAGE_HIGH 1075
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#endif
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bool chipid_get_production_mode(void)
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{
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return ((rCFG_FUSE0 >> 0) & 1) != 0;
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}
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void chipid_clear_production_mode(void)
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{
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#if SUPPORT_FPGA
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_rCFG_FUSE0 &= ~1;
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#else
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rCFG_FUSE0 &= ~1;
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#endif
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}
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bool chipid_get_secure_mode(void)
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{
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return ((rCFG_FUSE0 >> 1) & 1) != 0;
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}
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u_int32_t chipid_get_security_domain(void)
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{
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return (rCFG_FUSE0 >> 2) & 3;
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}
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u_int32_t chipid_get_board_id(void)
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{
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return (rCFG_FUSE0 >> 4) & 3;
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}
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bool chipid_get_ecid_image_personalization_required(void)
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{
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return ((rCFG_FUSE0 >> 7) & 1) != 0;
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}
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u_int32_t chipid_get_minimum_epoch(void)
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{
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return (rCFG_FUSE0 >> 9) & 0x7F;
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}
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u_int32_t chipid_get_chip_id(void)
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{
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#if SUB_PLATFORM_S5L8945X
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return 0x8945;
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#endif
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}
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u_int32_t chipid_get_chip_revision(void)
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{
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return (((rECIDHI >> 13) & 0x7) << 4) | (((rECIDHI >> 10) & 0x7) << 0);
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}
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u_int32_t chipid_get_osc_frequency(void)
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{
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return OSC_FREQ;
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}
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u_int64_t chipid_get_ecid_id(void)
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{
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u_int64_t ecid = 0;
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#if SUPPORT_FPGA
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ecid = 0x000012345678ABCDULL;
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#else
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ecid |= ((rECIDLO >> 0)) & ((1ULL << (21 - 0)) - 1); // LOT_ID
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ecid <<= (26 - 21);
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ecid |= ((rECIDLO >> 21)) & ((1ULL << (26 - 21)) - 1); // WAFER_NUM
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ecid <<= (10 - 2);
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ecid |= ((rECIDHI >> 2)) & ((1ULL << (10 - 2)) - 1); // Y_POS
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ecid <<= (32 - 26);
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ecid |= ((rECIDLO >> 26)) & ((1ULL << (32 - 26)) - 1); // X_POS_H
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ecid <<= ( 2 - 0);
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ecid |= ((rECIDHI >> 0)) & ((1ULL << ( 2 - 0)) - 1); // X_POS_L
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#endif
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return ecid;
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}
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u_int64_t chipid_get_die_id(void)
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{
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return ((u_int64_t)rECIDHI << 32) | rECIDLO;
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}
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u_int32_t chipid_get_fused_thermal_70C(void)
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{
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return (rCFG_FUSE6 >> 8) & 0xff;
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}
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u_int32_t chipid_get_fused_thermal_25C(void)
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{
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return rCFG_FUSE6 & 0xff;
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}
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u_int32_t chipid_get_fuse_revision(void)
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{
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return (rCFG_FUSE1 >> 25) & 0xf;
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}
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u_int32_t chipid_get_soc_voltage(u_int32_t index)
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{
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u_int32_t soc_voltage = 0;
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u_int32_t soc_bin_offset_data = 0, soc_bin_data = (rCFG_FUSE1 >> 5) & 0x1FF;
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int32_t soc_bin_offset;
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#if DEBUG_BUILD && WITH_ENV
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soc_bin_offset_data = env_get_uint("soc-bin-offset", 0);
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switch (index) {
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case CHIPID_SOC_VOLTAGE_LOW : soc_bin_offset_data = (soc_bin_offset_data >> 0) & 0xff; break;
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case CHIPID_SOC_VOLTAGE_MED : soc_bin_offset_data = (soc_bin_offset_data >> 8) & 0xff; break;
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case CHIPID_SOC_VOLTAGE_HIGH : soc_bin_offset_data = (soc_bin_offset_data >> 16) & 0xff; break;
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default : break;
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}
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#endif
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// if bin data is all zeros, bin data is not valid
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if (soc_bin_data == 0) {
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switch (index) {
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case CHIPID_SOC_VOLTAGE_LOW : soc_voltage = DEFAULT_SOC_VOLTAGE_LOW; break;
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case CHIPID_SOC_VOLTAGE_MED : soc_voltage = DEFAULT_SOC_VOLTAGE_MED; break;
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case CHIPID_SOC_VOLTAGE_HIGH : soc_voltage = DEFAULT_SOC_VOLTAGE_HIGH; break;
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default : break;
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}
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} else {
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switch (index) {
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case CHIPID_SOC_VOLTAGE_LOW : soc_voltage = BASE_SOC_VOLTAGE_LOW + 25 * ((soc_bin_data>>6)&7); break;
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case CHIPID_SOC_VOLTAGE_MED : soc_voltage = BASE_SOC_VOLTAGE_MED + 25 * ((soc_bin_data>>3)&7); break;
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case CHIPID_SOC_VOLTAGE_HIGH : soc_voltage = BASE_SOC_VOLTAGE_HIGH + 25 * ((soc_bin_data>>0)&7); break;
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default : break;
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}
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}
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soc_bin_offset = soc_bin_offset_data | (((soc_bin_offset_data & 0x80) == 0) ? 0 : 0xffffff00);
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soc_bin_offset *= 25;
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return soc_voltage + soc_bin_offset;
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}
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u_int32_t chipid_get_cpu_voltage(u_int32_t index)
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{
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u_int32_t cpu_voltage = 0;
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u_int32_t cpu_bin_offset_data = 0, cpu_bin_data = ((((u_int64_t)rCFG_FUSE1 << 32) | rCFG_FUSE0) >> 28) & 0x1FF;
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int32_t cpu_bin_offset;
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#if DEBUG_BUILD && WITH_ENV
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cpu_bin_offset_data = env_get_uint("core-bin-offset", 0);
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switch (index) {
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case CHIPID_CPU_VOLTAGE_LOW : cpu_bin_offset_data = (cpu_bin_offset_data >> 0) & 0xff; break;
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case CHIPID_CPU_VOLTAGE_MED : cpu_bin_offset_data = (cpu_bin_offset_data >> 8) & 0xff; break;
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case CHIPID_CPU_VOLTAGE_HIGH : cpu_bin_offset_data = (cpu_bin_offset_data >> 16) & 0xff; break;
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default : break;
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}
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#endif
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// if bin data is all zeros, bin data is not valid
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if (cpu_bin_data == 0) {
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switch (index) {
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case CHIPID_CPU_VOLTAGE_LOW : cpu_voltage = DEFAULT_CPU_VOLTAGE_LOW; break;
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case CHIPID_CPU_VOLTAGE_MED : cpu_voltage = DEFAULT_CPU_VOLTAGE_MED; break;
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case CHIPID_CPU_VOLTAGE_HIGH : cpu_voltage = DEFAULT_CPU_VOLTAGE_HIGH; break;
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default : break;
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}
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} else {
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switch (index) {
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case CHIPID_CPU_VOLTAGE_LOW : cpu_voltage = BASE_CPU_VOLTAGE_LOW + 25 * ((cpu_bin_data>>6)&7); break;
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case CHIPID_CPU_VOLTAGE_MED : cpu_voltage = BASE_CPU_VOLTAGE_MED + 25 * ((cpu_bin_data>>3)&7); break;
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case CHIPID_CPU_VOLTAGE_HIGH : cpu_voltage = BASE_CPU_VOLTAGE_HIGH + 25 * ((cpu_bin_data>>0)&7); break;
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default : break;
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}
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}
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cpu_bin_offset = cpu_bin_offset_data | (((cpu_bin_offset_data & 0x80) == 0) ? 0 : 0xffffff00);
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cpu_bin_offset *= 25;
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return cpu_voltage + cpu_bin_offset;
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}
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bool chipid_get_fuse_lock(void)
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{
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return (rCFG_FUSE1 & (1 << 31)) != 0;
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}
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void chipid_set_fuse_lock(bool locked)
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{
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if (locked) rCFG_FUSE1 |= 1 << 31;
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}
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