155 lines
5.7 KiB
C
155 lines
5.7 KiB
C
/*
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* Copyright (C) 2009-2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#if WITH_TARGET_AMC_PARAMS
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#include <target/amcconfig.h>
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#else
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static const struct amc_param amc_params = {
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.flags = (FLAG_AMC_PARAM_BUSTAT23 | FLAG_AMC_PARAM_RECONFIG | FLAG_AMC_PARAM_SLOW_BOOT | FLAG_AMC_PARAM_ENABLE_AIU),
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.freqsel = 0,
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.tREFi = 0x5d,
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.longsrcnt = 0x2008,
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.srextrarefcnt = 0x00010000,
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.tREFi_1Gb = 0xbb,
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.longsrcnt_1Gb = 0x1004,
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.rdlat = 6,
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.wrlat = 3,
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.phyrdlat = 8, // rdlat + 2
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.phywrlat = 3,
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.pdn = 0x33000303,
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.read = 0x00000103,
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.bustat = 0x00222212,
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.bustat2 = 0x00222212,
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.derate = 0x28831258,
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.mcphyupdate = 0x05010009,
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.pwrmngtparam_small = 0x00013000,
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.pwrmngtparam_guided = 0x00fa3000,
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.chnldec = 0x00040000,
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.chnldec2 = 0x00555555,
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.chnldec4 = 0x00aaaaaa,
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.autoref_params = 0x00000022,
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.bootclkdivsr = 8,
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.arefparam = 0x0600a000,
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.aref_freq0 = 0x00100100,
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.aref_freq1 = 0x00100000,
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.readleveling = 0x01000301,
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.freq = {
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{ // 400MHz
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.cas = 0x00000308,
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.pch = 0x00030611,
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.act = 0x14040908,
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.autoref = 0x1834a000,
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.selfref = 0x00038060,
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.modereg = 0x00240502,
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.mifcassch = 0x001f0111,
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.mifqmaxctrl = 0x00000000,
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},
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{ // 200MHz
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.cas = 0x00000004,
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.pch = 0x00000009,
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.act = 0x0a020504,
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.autoref = 0x0c1a0000,
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.selfref = 0x0001c000,
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.modereg = 0x00120000,
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.mifcassch = 0x00000000,
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.mifqmaxctrl = 0x00000000,
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},
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{ // 100MHz
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.cas = 0x00000003,
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.pch = 0x00000005,
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.act = 0x08020303,
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.autoref = 0x060d0000,
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.selfref = 0x0000e000,
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.modereg = 0x00090000,
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.mifcassch = 0x00000000,
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.mifqmaxctrl = 0x00000000,
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},
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{ // 50 & 24MHz
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.cas = 0x00000003,
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.pch = 0x00000003,
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.act = 0x08020303,
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.autoref = 0x03070000,
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.selfref = 0x00007000,
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.modereg = 0x00060000,
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.mifcassch = 0x00000010,
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.mifqmaxctrl = 0x00000001,
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}
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}
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};
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static const struct amc_tunable amc_tunables[] = {
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// These settings are common across all H4x and H5P. Channel decode and hashing
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// is done in mainline init code. Any tunables that match hardware defaults are
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// omitted here.
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{ &rAMC_AIUPRT_CFG, 0x00070000 }, // address error enable
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{ &rAMC_AIUPRT_RD_GEN, 0x00000018 }, // fence read detect on GFX
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{ &rAMC_AIUPRT_WR, 0x00000001 }, // out-of-order write, ignore B-bit
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{ &rAMC_AIU_RDBRSTLEN, 0x01010101 }, // burst len is 64B
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{ &rAMC_AIU_RDMINCRD, 0x7B7B7C7B }, // RT:NRT:CPU:GFX = 40:40:5:10
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{ &rAMC_AIU_WRBRSTLEN, 0x01010101 }, // burst len is 64B
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{ &rAMC_AIU_WRMINCRD, 0x7B7B7C7B }, // RT:NRT:CPU:GFX = 40:40:5:10
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{ &rAMC_AIU_CPUSPCREQ, 0x00000019 }, // CPU ageout timer
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{ &rAMC_AIU_GFXSPCREQ, 0x00000032 }, // GFX ageout timer
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{ &rAMC_AIU_NRTSPCREQ, 0x00000032 }, // Hperf-NRT ageout timer
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{ &rAMC_AIU_RTSPCREQ, 0x00000019 }, // Hperf-RT ageout timer
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{ &rAMC_AIU_WPQSCH, 0x10001000 }, // only supported for Hperf-RT
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{ &rAMC_AIU_THOTLCPUPARAM, 0x0A4640C4 },
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{ &rAMC_AIU_THOTLRTPARAM, 0x0A4640C4 },
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{ &rAMC_AIU_THOTLNRTPARAM, 0x00000000 },
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{ &rAMC_AIU_THOTLGFXPARAM, 0x00000000 },
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{ &rAMC_AIU_PUSHEN, 0x00001100 }, // only supported for Hperf-RT
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{ &rAMC_OPIDLETMR, 0x00200000 },
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{ &rAMC_OPTMRADJEN, 0x00000001 },
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{ &rAMC_OPTMRADJPARAM, 0x20400064 },
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{ &rAMC_MIFACTSCH, 0x00000001 },
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{ &rAMC_PSQRQTIMER0, 0x00000040 }, // RTG bypass up to 64 transactions
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{ &rAMC_PSQRQTIMER1, 0x00000018 }, // RTY bypass up to 24 transactions
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{ &rAMC_PSQRQTIMER2, 0x00000020 }, // RTG bypass up to 32 transactions
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{ &rAMC_PSQRQBRST, 0x040c040c }, // RTR transactions don't affect read burst size
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{ &rAMC_PSQRQSCHCRD, 0x002028f5 }, // read credits = 2 * write credits
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{ &rAMC_PSQWQBRST, 0x0208040c }, // RTR reads cause reduced write burst size
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{ &rAMC_PSQWQSCHCRD, 0x001014f5 }, // write credits = 1/2 * read credits
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{ &rAMC_MCUQOS, 0x00010f04 }, // RTG=4, RTY=15, enable pick-oldest-RTY
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// Platform specific
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{ &rAMC_AIU_RDMAXCRD, 0x1928047F }, // RT:NRT:CPU:GFX = 40:40:5:10
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{ &rAMC_AIU_RDREFL, 0x1421037F }, // 5/6 of AIURDMAXCRD fields
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{ &rAMC_AIU_WRMAXCRD, 0x1928047F }, // RT:NRT:CPU:GFX = 40:40:5:10
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{ &rAMC_AIU_WRREFL, 0x1421037F }, // 5/6 of AIUWRMAXCRD fields
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{ &rAMC_AIU_THOTLEN, 0x00000000 }, // enable throttling
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{ &rAMC_PSQRQCTL1, 0x0000112A }, // ages write out faster than default (1/2 SelfRef)
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{ &rAMC_PSQWQCTL1, 0x00000180 }, // ages write out faster than default (1/2 SelfRef)
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{ &rAMC_MCUQOSLLT, 0x00010108 },
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{ &rAMC_PWRMNGTPARAM, 0x03001000 }, // SelfRef timer = 384 cycles
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// There is a bug around write merge, which we believe is avoided
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// in current drivers: <rdar://problem/9076703>
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// Power and performance measurements of disabling write merging were
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// done: <rdar://problem/9092558> <rdar://problem/9087726>
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{ &rAMC_PSQWQCTL0, 0x00010100 }, // Write merge enable
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{ &rAMC_AIU_ADDRBANKHASH0, 0x00006db6 }, // Enable bank hashing, bank[0] derived from bits 0,3,6,..
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{ &rAMC_AIU_ADDRBANKHASH1, 0x00005b6d }, // Enable bank hashing, bank[1] derived from bits 1,4,7,..
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{ &rAMC_AIU_ADDRBANKHASH2, 0x000036db }, // Enable bank hashing, bank[2] derived from bits 2,5,8,..
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{ &rAMC_AIU_CHNLCRD, 0x00180018 },
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{ &rAMC_AIU_CHNLTM, 0x00006101 },
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{ &rAMC_AIU_LLTSCHCTL, 0x00000001 }, // Ensure LLT traffic from all ports is treated as medium priority request in the AIU arbitration
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};
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#endif |