338 lines
17 KiB
C
338 lines
17 KiB
C
/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __PLATFORM_SOC_HWREGBASE_H
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#define __PLATFORM_SOC_HWREGBASE_H
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#include <platform/memmap.h>
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/* T7000 and T7001 Reg Base Defs */
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#define AMCC_BASE_ADDR (IO_BASE + 0x000000000) // AMCC Config
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#define AMCX_BASE_ADDR (IO_BASE + 0x000100000) // AMCX Config
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#define SWTCH_FAB_BASE_ADDR (IO_BASE + 0x000800000) // Switch Fabric Config
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#define CP_COM_BASE_ADDR (IO_BASE + 0x000D00000) // CP Common Registers
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#define CP_COM_INT_BASE_ADDR (CP_COM_BASE_ADDR + 0x10000) // CP Common Interrupt Config Registers
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#define CP_0_DT_BASE_ADDR (IO_BASE + 0x000D20000) // Dup Tag Config and Debug
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#define CP_0_DT_DBG_CA0_ADDR (IO_BASE + 0x000D30000) // Dup Tag Debug backdoor Ram Access For CP0/CA0
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#define CP_0_CCU_CSR_BASE_ADDR (IO_BASE + 0x000D90000) // CTT and MIU Config and Debug
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#define CP_1_DT_BASE_ADDR (IO_BASE + 0x000E20000) // Dup Tag Config and Debug
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#define CP_1_DT_DBG_CA0_ADDR (IO_BASE + 0x000E30000) // Dup Tag Debug backdoor Ram Access For CP1/CA0
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#define CP_1_CCU_CSR_BASE_ADDR (IO_BASE + 0x000E90000) // CTT and MIU Config and Debug
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#define RGX_CR_BASE_ADDR (IO_BASE + 0x001000000) // Templar4 Space
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#define GPC_BASE_ADDR (IO_BASE + 0x001e00000) // Templar4 Power Controller Space
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#define IMGV42AF_AFC_AIU_BASE_ADDR (IO_BASE + 0x001f00000) // IMGv42AF: Local PIO Config Space of AF AIU Block
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#define IMGV42AF_AFUSR_BASE_ADDR (IO_BASE + 0x001f02000) // IMGv42AF: Bridge PIO Space
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#define CCC_ROM_TABLE_BASE_ADDR (IO_BASE + 0x002000000) // Typhoon ROM Table
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#define CCC_CPU0_DBG_BASE_ADDR (IO_BASE + 0x002010000) // Typhoon CPU0 Debug Registers
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#define CCC_CPU0_CTI_BASE_ADDR (IO_BASE + 0x002020000) // Typhoon CPU0 CTI Registers
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#define CCC_CPU0_PMU_BASE_ADDR (IO_BASE + 0x002030000) // Typhoon CPU0 PMU Registgers
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#define CCC_CPU0_TRC_BASE_ADDR (IO_BASE + 0x002040000) // Typhoon CPU0 TRACE Registers
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#define CCC_CPU0_SYS_BASE_ADDR (IO_BASE + 0x002050000) // Typhoon CPU0 Implementation Specific Registers
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#define CCC_CPU1_DBG_BASE_ADDR (IO_BASE + 0x002110000) // Typhoon CPU1 Debug Registers
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#define CCC_CPU1_CTI_BASE_ADDR (IO_BASE + 0x002120000) // Typhoon CPU1 CTI Registers
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#define CCC_CPU1_PMU_BASE_ADDR (IO_BASE + 0x002130000) // Typhoon CPU1 PMU Registgers
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#define CCC_CPU1_TRC_BASE_ADDR (IO_BASE + 0x002140000) // Typhoon CPU1 TRACE Registers
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#define CCC_CPU1_SYS_BASE_ADDR (IO_BASE + 0x002150000) // Typhoon CPU1 Implementation Specific Registers
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#define CCC_CCC_DBG_BASE_ADDR (IO_BASE + 0x002250000) // Typhoon CCC Debug Registers
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#if SUB_PLATFORM_T7001
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#define CCC_CPU2_TRC_BASE_ADDR (IO_BASE + 0x002440000) // Typhoon CPU2 Trace Registers
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#define CCC_CPU2_SYS_BASE_ADDR (IO_BASE + 0x002450000) // Typhoon CPU2 Implementation Specific Registers
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#endif
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#define CCC0_SYS_BASE_ADDR (IO_BASE + 0x002200000) // Typhoon Core Complex Registers
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#define CCC_SOC_BUSMUX_BASE_ADDR (IO_BASE + 0x004000000) // AF SoC BusMux Config
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#define SOC_BUSMUX_BASE_ADDR (IO_BASE + 0x004000000) // AF SoC BusMux Config
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#if SUB_PLATFORM_T7000
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#define CCC_CAM_BUSMUX_BASE_ADDR (IO_BASE + 0x005000000) // AF Camera BusMux Config
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#endif
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#define ISP_AFC_AIU_0_BASE_ADDR (IO_BASE + 0x005B00000) // ISP AXI to AF Bridge
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#if SUB_PLATFORM_T7000
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#define ISP_AFC_AIU_1_BASE_ADDR (IO_BASE + 0x005B10000) // ISP AXI to AF Bridge
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#endif
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#define ISP_INTR2AXI_BASE_ADDR (IO_BASE + 0x005B20000) // ISP Interrupt to AXI Widget
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#define ISP_DART_BASE_ADDR (IO_BASE + 0x005B22000) // ISP DART
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#define ISP_SMMU_BASE_ADDR (IO_BASE + 0x005B24000) // ISP SMMU
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#define ISP_ISPCTRL_R0_BASE_ADDR (IO_BASE + 0x005B40000) // SISP Region 0 Control
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#define ISP_MIPI_CSI_0_BASE_ADDR (IO_BASE + 0x005B80000) // MIPI CSI Controller
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#define ISP_MIPI_CSI_1_BASE_ADDR (IO_BASE + 0x005B81000) // MIPI CSI Controller
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#define ISP_SMB_0_BASE_ADDR (IO_BASE + 0x005B82000) // SMB Controller
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#define ISP_SMB_1_BASE_ADDR (IO_BASE + 0x005B83000) // SMB Controller
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#define ISP_FD_BASE_ADDR (IO_BASE + 0x005B84000) // Face Detect
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#define ISP_AISP_BASE_ADDR (IO_BASE + 0x005BA0000) // AISP
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#define ISP_ISPCTRL_R1_BASE_ADDR (IO_BASE + 0x005BC0000) // SISP Region 1 Control
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#define ISP_AKF_BASE_ADDR (IO_BASE + 0x005C00000) // SISP KF Widgets and Config
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#if SUB_PLATFORM_T7000
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#define DISP_BUSMUX_BASE_ADDR (IO_BASE + 0x006000000) // AF Display BusMux Config
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#endif
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#define DISP0_FAB_BASE_ADDR (IO_BASE + 0x006100000) // DisplayPipe0 AF and AXI Config
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#define DISP0_BASE_ADDR (IO_BASE + 0x006200000) // DisplayPipe0
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#define DISP0_ADP_BASE_ADDR (IO_BASE + 0x006200000) // DisplayPipe0 Configuration
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#define DISP0_SMMU_BASE_ADDR (IO_BASE + 0x006300000) // DisplayPipe0 SMMU Configuration
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#define DISP0_ADBE_BASE_ADDR (IO_BASE + 0x006400000) // DisplayPipe0 Backend Config
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#define DISP0_AAP_BASE_ADDR (IO_BASE + 0x006440000) // DisplayPipe0 Ambient-Adaptive Pixel Config
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#define DISP0_DPB_BASE_ADDR (IO_BASE + 0x006480000) // DisplayPipe0 Pixel Backlight Config
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#define DISP0_DITHER_BASE_ADDR (IO_BASE + 0x0064C0000) // DisplayPipe0 Dither Config
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#define DITHER_BASE_ADDR DISP0_DITHER_BASE_ADDR
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#define DITHER_VERSION (3)
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#if SUB_PLATFORM_T7000
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#define DISP0_MIPI_DSI_BASE_ADDR (IO_BASE + 0x006600000) // DisplayPipe0 MIPI DSI Config
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#endif
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#define DISP0_DPTX_BASE_ADDR (IO_BASE + 0x006700000) // DisplayPipe0 DisplayPort TX Config
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#define DISP1_FAB_BASE_ADDR (IO_BASE + 0x006900000) // DisplayPipe1 AF and AXI Config
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#define DISP1_BASE_ADDR (IO_BASE + 0x006A00000) // DisplayPipe1
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#define DISP1_ADP_BASE_ADDR (IO_BASE + 0x006A00000) // DisplayPipe1 Ambient-Adaptive Pixel Config
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#define DISP1_SMMU_BASE_ADDR (IO_BASE + 0x006B00000) // DisplayPipe1 SMMU Configuration
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#define DISP1_MEDIA_BUSMUX_BASE_ADDR (IO_BASE + 0x007000000) // DisplayPipe1 AF Media BusMux Config
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#define MSR_AFC_AIU_BASE_ADDR (IO_BASE + 0x007800000) // MSR AXI2AF AFC_AIU
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#define MSR_BASE_ADDR (IO_BASE + 0x007900000) // Memory Scalar Rotator
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#define MSR_SMMU_BASE_ADDR (IO_BASE + 0x007904000) // MSR SMMU
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#define MSR_DART_BASE_ADDR (IO_BASE + 0x007908000) // DART for MSR SMMU
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#define MSR_INTR2AXI_BASE_ADDR (IO_BASE + 0x00790C000) // MSR Interrupt to AXI Widget
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#define AJPEG_AFC_AIU_BASE_ADDR (IO_BASE + 0x007A00000) // AJPEG AXI2AF AFC_AIU
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#define AJPEG_BASE_ADDR (IO_BASE + 0x007B00000) // AJPEG Wrap
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#define AJPEG_DART_BASE_ADDR (IO_BASE + 0x007B02000) // AJPEG DART
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#define AJPEG_INTR2AXI_BASE_ADDR (IO_BASE + 0x007B04000) // AJPEG Interrupt to AXI Widget
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#define SVE_BASE_ADDR (IO_BASE + 0x007C00000) // SVE Video Encoder Subsystem
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#define SVE_AVE_AXI2AF (IO_BASE + 0x007C00000) // SVE AVE AXI to Apple Fabric Bridge
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#define SVE_AFC_AIU_BASE_ADDR (IO_BASE + 0x007C00000) // SVE AXI2AF AFC_AIU
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#define SVE_INTR2AXI_BASE_ADDR (IO_BASE + 0x007C10000) // SVE VENC Interrupt to AXI Widget
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#define SVE_SMMU_BASE_ADDR (IO_BASE + 0x007C20000) // SVE Streaming MMU for AVE
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#define SVE_DART_BASE_ADDR (IO_BASE + 0x007C30000) // SVE DART for AVE SMMU
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#define SVE_PL301_BASE_ADDR (IO_BASE + 0x007C40000) // SVE PL301 Config
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#define SVE_AKF_BASE_ADDR (IO_BASE + 0x007C80000) // SVE Kingfisher Wrapper Configuration
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// XXX #define SVE_AVE_KF_DBG_BASE_ADDR (IO_BASE + 0x007CA0000) // SVE Kingfisher Wrapper Debug APB
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#define SVE_CTRL_BASE_ADDR (IO_BASE + 0x007CC0000) // SVE Control Registers
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#define VXD_AFC_AIU_BASE_ADDR (IO_BASE + 0x007E00000) // VXD AXI2AF AFC_AIU
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#define VXD_INTR2AXI_BASE_ADDR (IO_BASE + 0x007E10000) // VXD Interrupt to AXI Widget
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#define VXD_PL301_BASE_ADDR (IO_BASE + 0x007E20000) // VXD PL301 Config
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#define VXD_CFG_BASE_ADDR (IO_BASE + 0x007F00000) // VXD Config Registers
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#define ANS_AFC_AIU_BASE_ADDR (IO_BASE + 0x008000000) // ANS AXI2AF AFC_AIU
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#define ANS_PL301_BASE_ADDR (IO_BASE + 0x008010000) // ANS PL301 Config
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#define ANS_AKF_PL301_TLMT_BASE_ADDR (IO_BASE + 0x008020000) // ANS KF Transaction Limit Widget
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#define ANS_AKF_INTR2AXI_BASE_ADDR (IO_BASE + 0x008021000) // ANS KF Interrupt to AXI Widget
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#define ANS_ANC_PL301_TLMT_0_BASE_ADDR (IO_BASE + 0x008030000) // ANS NAND Controller Transaction Limit Widget
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#define ANS_ANC_PL301_TLMT_1_BASE_ADDR (IO_BASE + 0x008031000) // ANS NAND Controller Transaction Limit Widget
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#define ANS_ANC_INTR2AXI_0_BASE_ADDR (IO_BASE + 0x008038000) // ANS NAND Controller Interrupt to AXI Widget
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#define ANS_ANC_INTR2AXI_1_BASE_ADDR (IO_BASE + 0x008039000) // ANS NAND Controller Interrupt to AXI Widget
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#define ANS_AKF_BASE_ADDR (IO_BASE + 0x008040000) // ANS KF Wrapper
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// XXX AKF DBG (IO_BASE + 0x008060000) - (IO_BASE + 0x008070000)
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#define ANS_CFG_BASE_BADDR (IO_BASE + 0x008080000) // ANS Config
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#define ANS_PPN_N_PL_BASE_ADDR (IO_BASE + 0x008081000) // ANS PPN-N-PL Config
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#define ANS_ANC_BASE_ADDR (IO_BASE + 0x008700000) // ANC Broadcast writes to all ANCs
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#define ANS_ANC_0_BASE_ADDR (IO_BASE + 0x008800000) // ANS NAND Controller 0
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#define ANS_ANC_1_BASE_ADDR (IO_BASE + 0x008900000) // ANS NAND Controller 1
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#define ANS_IO_BUSMUX_BASE_ADDR (IO_BASE + 0x009000000) // ANS AF IO BusMux Config
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#define IOBUSMUX_BASE_ADDR (IO_BASE + 0x009000000) // IO BusMux Config
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#define SB_BASE_ADDR (IO_BASE + 0x00A000000) // South Bridge
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#define ASIO_MISC_0_BASE_ADDR (IO_BASE + 0x00A000000) // ASIO Shim0 Misc Registers
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#define ASIO_AUD_MUX_BASE_ADDR (IO_BASE + 0x00A003000) // ASIO Audio I2S Switch Config
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#define ASIO_SPI_BASE_ADDR (IO_BASE + 0x00A080000) // ASIO SPI Device
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#define ASIO_SPI_TX_CFG_BASE_ADDR (IO_BASE + 0x00A081000) // ASIO SPI TX DMA Channel
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#define ASIO_SPI_RX_CFG_BASE_ADDR (IO_BASE + 0x00A081800) // ASIO SPI RX DMA Channel
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#define ASIO_SPI_TX_FIFO_BASE_ADDR (IO_BASE + 0x00A082000) // ASIO SPI TX DMA Shim FIFO
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#define ASIO_SPI_RX_FIFO_BASE_ADDR (IO_BASE + 0x00A083000) // ASIO SPI RX DMA Shim FIFO
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#define ASIO_MCA_BASE_ADDR (IO_BASE + 0x00A0A0000) // ASIO MCA Device
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#define ASIO_MCA_TX_CFG_BASE_ADDR (IO_BASE + 0x00A0A1000) // ASIO MCA TX DMA Channel
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#define ASIO_MCA_RX_CFG_BASE_ADDR (IO_BASE + 0x00A0A1800) // ASIO MCA RX DMA Channel
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#define ASIO_MCA_TX_FIFO_BASE_ADDR (IO_BASE + 0x00A0A2000) // ASIO MCA TX DMA Shim FIFO
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#define ASIO_MCA_RX_FIFO_BASE_ADDR (IO_BASE + 0x00A0A3000) // ASIO MCA RX DMA Shim FIFO
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#define ASIO_UART_BASE_ADDR (IO_BASE + 0x00A0C0000) // ASIO UART Device
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#define ASIO_UART_TX_CFG_BASE_ADDR (IO_BASE + 0x00A0C1000) // ASIO UART TX DMA Channel
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#define ASIO_UART_RX_CFG_BASE_ADDR (IO_BASE + 0x00A0C1800) // ASIO UART RX DMA Channel
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#define ASIO_UART_TX_FIFO_BASE_ADDR (IO_BASE + 0x00A0C2000) // ASIO UART TX DMA Shim FIFO
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#define ASIO_UART_RX_FIFO_BASE_ADDR (IO_BASE + 0x00A0C3000) // ASIO UART RX DMA Shim FIFO
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#define ASIO_MISC_1_BASE_ADDR (IO_BASE + 0x00A100000) // ASIO Shim1 Misc Registers
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#define ASIO_AES_BASE_ADDR (IO_BASE + 0x00A108000) // ASIO AES Config and DMA Registers
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#define ASIO_SMB_0_BASE_ADDR (IO_BASE + 0x00A110000) // ASIO I2C 0 Device
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#define ASIO_SMB_1_BASE_ADDR (IO_BASE + 0x00A111000) // ASIO I2C 1 Device
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#define ASIO_SMB_2_BASE_ADDR (IO_BASE + 0x00A112000) // ASIO I2C 2 Device
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#define ASIO_SMB_3_BASE_ADDR (IO_BASE + 0x00A113000) // ASIO I2C 3 Device
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#define ASIO_PWM_BASE_ADDR (IO_BASE + 0x00A118000) // ASIO PWM
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#define ASIO_DNSZ_AXI_0_BASE_ADDR (IO_BASE + 0x00A141000) // ASIO Downsizer 0 Configuration Registers
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#define ASIO_DNSZ_AXI_1_BASE_ADDR (IO_BASE + 0x00A142000) // ASIO Downsizer 1 Configuration Registers
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#define ASIO_AKF_BASE_ADDR (IO_BASE + 0x00AE00000) // ASIO KF Wrapper
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// XXX ASIO AKF DBG
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#define AUSB_CTL_REG_BASE_ADDR (IO_BASE + 0x00C000000) // USBCTL Config
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#define AUSB_CTL_USB20PHY_REG_OFFSET (0x30) // USB20PHY Register offset within AUSBCTL registers
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#define AUSB_OTG_BASE_ADDR (IO_BASE + 0x00C100000) // USB OTG
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#define AUSB_USB2HOST0_EHCI_BASE_ADDR (IO_BASE + 0x00C200000) // EHCI0
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#define AUSB_USB2HOST0_OHCI_BASE_ADDR (IO_BASE + 0x00C300000) // OHCI0
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#define AUSB_USB2HOST1_EHCI_BASE_ADDR (IO_BASE + 0x00C400000) // EHCI1
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#define AUSB_USB2HOST1_OHCI_BASE_ADDR (IO_BASE + 0x00C500000) // OHCI1
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#define AUSB_PL301_BASE_ADDR (IO_BASE + 0x00C800000) // AUSB PL301 4-AHB Master to 1-AXI Slave
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#define AUSB_PL301_WIDGET_BASE_ADDR (IO_BASE + 0x00C900000) // AUSB PL301 Widget
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#define AUSB_INTR2AXI_BASE_ADDR (IO_BASE + 0x00CA00000) // AUSB Interrupt to AXI Widget
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#define AUSB_AFIFO_WIDGET_BASE_ADDR (IO_BASE + 0x00CB00000) // AUSB Async FIFO
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#define ASEP_AKF_BASE_ADDR (IO_BASE + 0x00DA00000) // ASEP AKF control Registers
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#define PMGR_BASE_ADDR (IO_BASE + 0x00E000000) // PMGR
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#define AIC_BASE_ADDR (IO_BASE + 0x00E100000) // AIC
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#define AIC_WIRE_VIRT_BASE_ADDR (IO_BASE + 0x00E110000) // AIC Wrapper
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#define DWI_BASE_ADDR (IO_BASE + 0x00E200000) // DWI
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#define GPIO_BASE_ADDR (IO_BASE + 0x00E300000) // GPIO
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#define AMPS_0_DQ0_BASE_ADDR (IO_BASE + 0x00E400000) // AMP 0 DQ0 DRAM PHY
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#define AMPS_0_DQ1_BASE_ADDR (IO_BASE + 0x00E410000) // AMP 0 DQ1 DRAM PHY
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#define AMPS_0_CA_BASE_ADDR (IO_BASE + 0x00E420000) // AMP 0 CA DRAM PHY
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#define AMPS_1_DQ0_BASE_ADDR (IO_BASE + 0x00E430000) // AMP 1 DQ0 DRAM PHY
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#define AMPS_1_DQ1_BASE_ADDR (IO_BASE + 0x00E440000) // AMP 1 DQ1 DRAM PHY
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#define AMPS_1_CA_BASE_ADDR (IO_BASE + 0x00E450000) // AMP 1 CA DRAM PHY
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#if SUB_PLATFORM_T7001
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#define AMPS_2_DQ0_BASE_ADDR (IO_BASE + 0x00E460000) // AMP 2 DQ0 DRAM PHY
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#define AMPS_2_DQ1_BASE_ADDR (IO_BASE + 0x00E470000) // AMP 2 DQ1 DRAM PHY
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#define AMPS_2_CA_BASE_ADDR (IO_BASE + 0x00E480000) // AMP 2 CA DRAM PHY
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#define AMPS_3_DQ0_BASE_ADDR (IO_BASE + 0x00E490000) // AMP 3 DQ0 DRAM PHY
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#define AMPS_3_DQ1_BASE_ADDR (IO_BASE + 0x00E4A0000) // AMP 3 DQ1 DRAM PHY
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#define AMPS_3_CA_BASE_ADDR (IO_BASE + 0x00E4B0000) // AMP 3 CA DRAM PHY
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#endif
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#define LIO_MEM_PL301_BASE_ADDR (IO_BASE + 0x00E900000) // PL310 for pd_lio memory
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#define LIO_PIO_PL310_BASE_ADDR (IO_BASE + 0x00E940000) // PL310 for pd_lio PIO
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#define LIO_DNSZ_AXI_BASE_ADDR (IO_BASE + 0x00E9C8000) // PL310 for pd_lio downsizer
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#define LIO_SIO_AFIFO_WIDGETS_BASE_ADDR (IO_BASE + 0x00E9C0000) // SIO Async FIFO for pd_lio
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#define LIO_DAP_AFIFO_WIDGETS_BASE_ADDR (IO_BASE + 0x00E9E0000) // DAP Async FIFO for pd_lio
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#define LIO_AFC_AIU_BASE_ADDR (IO_BASE + 0x00F010000) // LIO AXI to AF Bridge
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#define DBG_WRP_BASE_ADDR (IO_BASE + 0x00F000000) // Debug Sub-system Config
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#define ERR_REFLECTION_BASE_ADDR (IO_BASE + 0x00FFFF000)
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#define APCIE_VERSION (1)
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#define APCIE_COMMON_BASE_ADDR (PCI_REG_BASE + 0x000000000)
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#define APCIE_CONFIG_BASE_ADDR (PCI_REG_BASE + 0x01004000)
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#define APCIE_CONFIG_PORT_STRIDE (0x01000000)
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#define APCIE_COUNTER_BASE_ADDR (PCI_REG_BASE + 0x800)
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/* iBoot Specific Defs */
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#define AKF_VERSION (1)
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#define UART0_BASE_ADDR (ASIO_UART_BASE_ADDR)
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#define UART1_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x04000)
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#define UART2_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x08000)
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#define UART3_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x0C000)
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#define UART4_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x10000)
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#define UART5_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x14000)
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#define UART6_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x18000)
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#define UART7_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x1C000)
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#define UART8_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x20000)
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#define UARTS_COUNT (9)
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#define UART_VERSION (1)
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#define SPI0_BASE_ADDR (ASIO_SPI_BASE_ADDR)
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#define SPI1_BASE_ADDR (ASIO_SPI_BASE_ADDR + 0x04000)
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#define SPI2_BASE_ADDR (ASIO_SPI_BASE_ADDR + 0x08000)
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#define SPI3_BASE_ADDR (ASIO_SPI_BASE_ADDR + 0x0C000)
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#define SPI_VERSION (1)
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#define SPIS_COUNT (4)
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#define IIC_BASE_ADDR (ASIO_SMB_0_BASE_ADDR)
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#define IIC_SPACING (0x00001000)
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#define IICS_COUNT (4)
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#define USBPHY_VERSION (4)
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#if SUB_PLATFORM_T7000
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#define DSIM_BASE_ADDR (DISP0_MIPI_DSI_BASE_ADDR)
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#define DSIM_LANE_COUNT (4)
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#define DSIM_VERSION (1)
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#endif
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#define EDP_BASE_ADDR (DISP0_DPTX_BASE_ADDR)
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#define DP_BASE_ADDR (DISP0_DPTX_BASE_ADDR)
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#define LPDP_PHY_BASE_ADDR (DISP0_DPTX_BASE_ADDR + 0x080000)
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#define DISPLAYPORT_VERSION (3)
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#define ADBE_DISPLAYPIPE_BASE_ADDR (DISP0_BASE_ADDR)
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#define DISP_VERSION (5)
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#if SUB_PLATFORM_T7000
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#define ADP_VERSION (1)
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#elif SUB_PLATFORM_T7001
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#define ADP_VERSION (2)
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#endif
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#define AMP_REG_VERSION (3)
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#define AMP_BASE_ADDR (AMPS_0_DQ0_BASE_ADDR)
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#define AMP_SPACING (0x00030000)
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#define AMP_DQCA_SPACING (0x00010000)
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#define AMP_CA_SPACING (0x00020000)
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#define CHIPID_BASE_ADDR (PMGR_BASE_ADDR + 0x2A000)
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#define GPIO_VERSION (4)
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#if SUB_PLATFORM_T7000
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#define GPIO_GROUP_COUNT (26)
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#elif SUB_PLATFORM_T7001
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#define GPIO_GROUP_COUNT (23)
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#endif
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#define GPIO_PAD_SPI (GPIO_GROUP_COUNT)
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#define AIC_VERSION (1)
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#define AIC_INT_COUNT (256)
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#define PMGR_WDG_VERSION (1)
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#define USBOTG_BASE_ADDR (AUSB_OTG_BASE_ADDR)
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#if SUB_PLATFORM_T7000
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#define APCIE_NUM_LINKS (2)
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#elif SUB_PLATFORM_T7001
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#define APCIE_NUM_LINKS (4)
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#endif
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#define DART0_BASE_ADDR (PCI_REG_BASE + 0x1002000)
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#define DART0_ADDR_MASK (0x3FFFFFFF)
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#define DART1_BASE_ADDR (PCI_REG_BASE + 0x2002000)
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#define DART1_ADDR_MASK (0x3FFFFFFF)
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#if SUB_PLATFORM_T7001
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#define DART2_BASE_ADDR (PCI_REG_BASE + 0x3002000)
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#define DART2_ADDR_MASK (0x3FFFFFFF)
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#define DART3_BASE_ADDR (PCI_REG_BASE + 0x4002000)
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#define DART3_ADDR_MASK (0x3FFFFFFF)
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#endif
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#define PCIE_PORT0_DART_ID (0)
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#define PCIE_PORT1_DART_ID (1)
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#if SUB_PLATFORM_T7000
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#define NUM_DARTS (2)
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#elif SUB_PLATFORM_T7001
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#define PCIE_PORT2_DART_ID (2)
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#define PCIE_PORT3_DART_ID (3)
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#define NUM_DARTS (4)
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#endif
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#define AES_AP_BASE_ADDR (ASIO_AES_BASE_ADDR)
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#define AES_AP_VERSION (0)
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#endif /* ! __PLATFORM_SOC_HWREGBASE_H */
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