146 lines
7.1 KiB
C
146 lines
7.1 KiB
C
/*
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* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __PLATFORM_SOC_MIU_H
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#define __PLATFORM_SOC_MIU_H
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#include <lib/devicetree.h>
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#include <platform/soc/hwregbase.h>
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#define rSECUREROMCTRL_ROMADDRREMAP (*(volatile u_int32_t *)(AMCC_BASE_ADDR + 0x0904))
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#define rMCCLOCKREGION_TZ0BASEADDR (*(volatile u_int32_t *)(AMCC_BASE_ADDR + 0x480))
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#define rMCCLOCKREGION_TZ0ENDADDR (*(volatile u_int32_t *)(AMCC_BASE_ADDR + 0x484))
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#define rMCCLOCKREGION_TZ1BASEADDR (*(volatile u_int32_t *)(AMCC_BASE_ADDR + 0x488))
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#define rMCCLOCKREGION_TZ1ENDADDR (*(volatile u_int32_t *)(AMCC_BASE_ADDR + 0x48c))
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#define rMCCLOCKREGION_TZ0LOCK (*(volatile u_int32_t *)(AMCC_BASE_ADDR + 0x490))
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#define rMCCLOCKREGION_TZ1LOCK (*(volatile u_int32_t *)(AMCC_BASE_ADDR + 0x494))
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#define ASIO_CLK_CTRL (0x100004)
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#define rASIO_CLK_CTRL (*(volatile u_int32_t *)(SB_BASE_ADDR + ASIO_CLK_CTRL))
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#define ASIO_AKF_IDLE_CTRL (0xe00024)
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#define rASIO_AKF_IDLE_CTRL (*(volatile u_int32_t *)(SB_BASE_ADDR + ASIO_AKF_IDLE_CTRL))
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#define DYN_CLK_GATING (0x49a0000)
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#define rDYN_CLK_GATING (*(volatile u_int32_t *)(SB_BASE_ADDR + DYN_CLK_GATING))
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#define SIO_ASYNC_FIFO_SB_RD_RATE_LIMIT (0x49c0000)
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#define rSIO_ASYNC_FIFO_SB_RD_RATE_LIMIT (*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_ASYNC_FIFO_SB_RD_RATE_LIMIT))
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#define SIO_ASYNC_FIFO_SB_WR_RATE_LIMIT (0x49c0004)
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#define rSIO_ASYNC_FIFO_SB_WR_RATE_LIMIT (*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_ASYNC_FIFO_SB_WR_RATE_LIMIT))
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#define SIO_ASYNC_FIFO_SB_WGATHER (0x49c0010)
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#define rSIO_ASYNC_FIFO_SB_WGATHER (*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_ASYNC_FIFO_SB_WGATHER))
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#define SIO_DAPASYNC_FIFO_SB_RD_RATE_LIMIT (0x49e0000)
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#define rSIO_DAPASYNC_FIFO_SB_RD_RATE_LIMIT (*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_DAPASYNC_FIFO_SB_RD_RATE_LIMIT))
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#define SIO_DAPASYNC_FIFO_SB_WR_RATE_LIMIT (0x49e0004)
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#define rSIO_DAPASYNC_FIFO_SB_WR_RATE_LIMIT (*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_DAPASYNC_FIFO_SB_WR_RATE_LIMIT))
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#define SIO_DAPASYNC_FIFO_SB_WGATHER (0x49e0010)
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#define rSIO_DAPASYNC_FIFO_SB_WGATHER (*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_DAPASYNC_FIFO_SB_WGATHER))
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#define AIU_SB_ARBCFG (0x5010000)
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#define rAIU_SB_ARBCFG (*(volatile u_int32_t *)(SB_BASE_ADDR + AIU_SB_ARBCFG))
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#define AIU_SB_CPG_CNTL (0x5010014)
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#define rAIU_SB_CPG_CNTL (*(volatile u_int32_t *)(SB_BASE_ADDR + AIU_SB_CPG_CNTL))
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#define SOCBUSMUX_ARBCFG (0x0000)
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#define rSOCBUSMUX_ARBCFG (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + SOCBUSMUX_ARBCFG))
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#if SUB_PLATFORM_T7001
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#define DWRRCFG_DISP0_RT (0x0004)
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#define rDWRRCFG_DISP0_RT (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + DWRRCFG_DISP0_RT))
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#endif
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#define DWRRCFG_DISPMUX_BULK (0x0008)
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#define rDWRRCFG_DISPMUX_BULK (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + DWRRCFG_DISPMUX_BULK))
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#if SUB_PLATFORM_T7001
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#define DWRRCFG_IOMUX_BULK (0x001c)
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#define rDWRRCFG_IOMUX_BULK (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + DWRRCFG_IOMUX_BULK))
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#endif
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#define TLIMIT_LVL0_DISP0 (0x0024)
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#define rTLIMIT_LVL0_DISP0 (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL0_DISP0))
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#define TLIMIT_LVL1_DISP0 (0x0028)
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#define rTLIMIT_LVL1_DISP0 (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL1_DISP0))
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#define TLIMIT_LVL2_DISP0 (0x002c)
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#define rTLIMIT_LVL2_DISP0 (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL2_DISP0))
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#define TLIMIT_LVL3_DISP0 (0x0030)
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#define rTLIMIT_LVL3_DISP0 (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL3_DISP0))
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#define TLIMIT_LVL0_CAMERAMUX (0x0034)
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#define rTLIMIT_LVL0_CAMERAMUX (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL0_CAMERAMUX))
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#define TLIMIT_LVL1_CAMERAMUX (0x0038)
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#define rTLIMIT_LVL1_CAMERAMUX (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL1_CAMERAMUX))
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#define TLIMIT_LVL1_MEDIAMUX (0x0048)
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#define rTLIMIT_LVL1_MEDIAMUX (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL1_MEDIAMUX))
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#define TLIMIT_LVL2_MEDIAMUX (0x004c)
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#define rTLIMIT_LVL2_MEDIAMUX (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL2_MEDIAMUX))
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#define TLIMIT_LVL0_IOMUX (0x0054)
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#define rTLIMIT_LVL0_IOMUX (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL0_IOMUX))
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#define TLIMIT_LVL1_IOMUX (0x0058)
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#define rTLIMIT_LVL1_IOMUX (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL1_IOMUX))
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#define TLIMIT_LVL2_IOMUX (0x005c)
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#define rTLIMIT_LVL2_IOMUX (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL2_IOMUX))
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#define TLIMIT_LVL3_IOMUX (0x0060)
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#define rTLIMIT_LVL3_IOMUX (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL3_IOMUX))
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#define SOCBUSMUX_CPG_CNTL (0x0088)
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#define rSOCBUSMUX_CPG_CNTL (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + SOCBUSMUX_CPG_CNTL))
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#define IOBUSMUX_ARBCFG (0x0000)
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#define rIOBUSMUX_ARBCFG (*(volatile u_int32_t *)(IOBUSMUX_BASE_ADDR + IOBUSMUX_ARBCFG))
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#if SUB_PLATFORM_T7001
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#define IOBUSMUX_REGS_DWRRCFG_DISP1_BULK (0x0010)
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#define rIOBUSMUX_REGS_DWRRCFG_DISP1_BULK (*(volatile u_int32_t *)(IOBUSMUX_BASE_ADDR + IOBUSMUX_REGS_DWRRCFG_DISP1_BULK))
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#endif
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#if SUB_PLATFORM_T7000
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#define IOBUSMUX_CPG_CNTL (0x0024)
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#elif SUB_PLATFORM_T7001
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#define IOBUSMUX_CPG_CNTL (0x002c)
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#endif
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#define rIOBUSMUX_CPG_CNTL (*(volatile u_int32_t *)(IOBUSMUX_BASE_ADDR + IOBUSMUX_CPG_CNTL))
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#define SWITCH_FAB_AMAP_LOCK (0x0000)
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#define rSWITCH_FAB_AMAP_LOCK (*(volatile u_int32_t *)(SWTCH_FAB_BASE_ADDR + SWITCH_FAB_AMAP_LOCK))
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#define SWITCH_FAB_ARBCFG (0x0008)
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#define rSWITCH_FAB_ARBCFG (*(volatile u_int32_t *)(SWTCH_FAB_BASE_ADDR + SWITCH_FAB_ARBCFG))
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#if SUB_PLATFORM_T7000
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#define SWITCH_FAB_PIOLIMIT (0x0028)
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#elif SUB_PLATFORM_T7001
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#define SWITCH_FAB_PIOLIMIT (0x002c)
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#endif
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#define rSWITCH_FAB_PIOLIMIT (*(volatile u_int32_t *)(SWTCH_FAB_BASE_ADDR + SWITCH_FAB_PIOLIMIT))
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#if SUB_PLATFORM_T7000
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#define SWITCH_FAB_CPG_CNTL (0x0070)
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#elif SUB_PLATFORM_T7001
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#define SWITCH_FAB_CPG_CNTL (0x008c)
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#endif
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#define rSWITCH_FAB_CPG_CNTL (*(volatile u_int32_t *)(SWTCH_FAB_BASE_ADDR + SWITCH_FAB_CPG_CNTL))
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#define CP_DYN_CLK_GATING_CTRL (0x000c)
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#define rCP_DYN_CLK_GATING_CTRL (*(volatile u_int32_t *)(CP_COM_BASE_ADDR + CP_DYN_CLK_GATING_CTRL))
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#define CPCOM_INT_NORM_REQUEST (0x0000)
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#define rCP_COM_INT_NORM_REQUEST (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CPCOM_INT_NORM_REQUEST))
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#define CPCOM_INT_NORM_MASK_SET (0x0004)
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#define rCP_COM_INT_NORM_MASK_SET (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CPCOM_INT_NORM_MASK_SET))
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#define CPCOM_INT_NORM_MASK_CLR (0x0008)
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#define rCP_COM_INT_NORM_MASK_CLR (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CPCOM_INT_NORM_MASK_CLR))
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#define LIO_MEMCACHE_DATASETID_OVERRIDE (0x001000)
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enum remap_select {
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REMAP_SRAM = 0,
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REMAP_SDRAM
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};
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extern void miu_select_remap(enum remap_select sel);
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extern void miu_bypass_prep(void);
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extern void miu_update_device_tree(DTNode *pmgr_node);
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#endif /* ! __PLATFORM_SOC_MIU_H */
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