257 lines
13 KiB
C
257 lines
13 KiB
C
#ifndef __TARGET_POWERCONFIG_H
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#define __TARGET_POWERCONFIG_H
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// Configuration per target
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#define PMU_IIC_BUS 0
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#define CHARGER_IIC_BUS 0
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// This configuration is very PMU specific and must be included exactly
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// once in power.c
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#ifdef POWERCONFIG_PMU_SETUP
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static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
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{
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};
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static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
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{
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{ PMU_IIC_BUS, kD2257_EN_CMD0, (1<<7)|(1<<3)|(1<<2)|(1<<1)|(1<<0) },
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{ PMU_IIC_BUS, kD2257_EN_CMD1, (1<<0) }, // buck8
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{ PMU_IIC_BUS, kD2257_EN_CMD2, 1 }, // enable WLED SPI access
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{ PMU_IIC_BUS, kD2257_SPI_CTRL, 1 } // enable SPI access
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};
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static const struct pmu_setup_struct pmu_warm_init[] =
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{
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};
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// IO_CONFIG[7:6] 0=I 1=O_OD 2=O_PP 3=SS
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// IO_TYPE[5:3] O 0=L 1=32K 2=nR 3=TI 4=L
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// PUPD[2:1] O 0=NP 1=PU 2=NP 3=<0>
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// WAKE_LVL[0] O 0=low 1=high
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// IO_TYPE[5:3] I 0=L_AH 1=L_AL 2=RE 3=FE 4=AE
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// PUPD[2:1] I 0=NP 1=PU 2=PD_GND 3=<0>
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// WAKE_LVL[0] I 0=NW 1=W
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//
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// <rdar://problem/19493772> J127 GPIO Spreadsheet (master)
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// J127_IO_spreadsheet_v26 (EVT).xlsx
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static const struct pmu_setup_struct pmu_cold_init[] =
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{
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// TODO :This is a Bringup Hack, remove
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{ PMU_IIC_BUS, kD2257_BUCK0_VSEL, 0xc0 }, // CPU rail
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{ PMU_IIC_BUS, kD2257_BUCK1_VSEL, 0xc0 }, // GPU rail
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{ PMU_IIC_BUS, kD2257_PWRONOFF_BUCK1_EN, 0xf }, // GPU power rail (see <rdar://problem/19733370>)
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{ PMU_IIC_BUS, kD2257_PWRONOFF_BUCK8_EN, 0xf }, // GPU RAM power rail (see <rdar://problem/19733370>)
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// TODO :This is a Bringup Hack, remove
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{ PMU_IIC_BUS, kD2257_PWRONOFF_BUCK3_SW2_EN, 0xf}, // <rdar://20080883> J99A/J127: Keep DVDD power rail on to avoid speaker pops (work around HW issue)
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{ PMU_IIC_BUS, kD2257_PWRONOFF_LDO4_EN, 0x1 }, // Enable PP3V0_ALS
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{ PMU_IIC_BUS, kD2257_PWRONOFF_LDO7_EN, 0x1 }, // Enable PP3V3_USB_SOC
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{ PMU_IIC_BUS, kD2257_LDO2_BYPASS, 0x1}, // bypass when Active rdar://19773152
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// Drive GPIO_PMU_TO_1V1_EXT_SW_ON (PMU GPIO 20) to enable PP1V1_S1_EXT_SW
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// which inturn is SNSI_PP1V1_S1_DDR_VDDQ_x.
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//
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// Should be ON by default via OTP.
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// Drive GPIO_PMU_TO_1V8_EXT_SW2_ON (PMU GPIO 21) to enable PP1V8_S2_EXT_SW2
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// which inturn is PP1V8_S2_IO_EXPANDER.
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//
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// Should be ON by default via OTP.
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{ PMU_IIC_BUS, kDIALOG_TEST_ACCESS, kDIALOG_TEST_ACCESS_ENA }, // Enable Test Mode
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{ PMU_IIC_BUS, kD2257_EN_CMD3, 0}, // Enable SPI access for BUCKx (x=3)
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{ PMU_IIC_BUS, kDIALOG_TEST_ACCESS, kDIALOG_TEST_ACCESS_DIS }, // Disable Test Mode
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// GPIO1: GPIO_AJ_HALL_TO_PMU_IRQ_L
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{ PMU_IIC_BUS, kD2257_GPIO1_CONF1, (0<<6)|(4<<3)|(1<<1)|(1<<0) }, // 0x23 Input, AnyE, PU, WakeUp
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{ PMU_IIC_BUS, kD2257_GPIO1_CONF2, (1<<3)|(1<<0) }, // 0x09 VBUCK3, 5ms
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// GPIO2: GPIO_ACC_TO_PMU_PWR_SW_OC_L
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{ PMU_IIC_BUS, kD2257_GPIO2_CONF1, (0<<6)|(3<<3)|(0<<1)|(0<<0) }, // 0x18 Input, AnyE, No PU/PD
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{ PMU_IIC_BUS, kD2257_GPIO2_CONF2, (1<<3)|(2<<0) }, // 0x0A VBUCK3, 10ms
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// GPIO3: GPIO_ORION_TO_SOC_TO_PMU_IRQ
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{ PMU_IIC_BUS, kD2257_GPIO3_CONF1, (0<<6)|(0<<3)|(2<<1)|(1<<0) }, // 0x25 Input, AH, PD, Wakeup
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{ PMU_IIC_BUS, kD2257_GPIO3_CONF2, (1<<3)|(1<<0) }, // 0x09 VBUCK3, 5ms
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// GPIO4: GPIO_PMU_TO_ACC_PWR_SW (was GPIO_PMU_TO_ACC_PWR_SEL)
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{ PMU_IIC_BUS, kD2257_GPIO4_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // 0x80 Output(Push-Pull), Level, No PU, Low
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{ PMU_IIC_BUS, kD2257_GPIO4_CONF2, (0<<3)|(0<<0) }, // 0x00 VCC_MAIN, no DEB
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// GPIO6: UART_BATT_HDQ
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{ PMU_IIC_BUS, kD2257_GPIO6_CONF1, (0<<6)|(3<<3)|(0<<1)|(1<<0) }, // 0x19 Input, FE, No PU/PD
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{ PMU_IIC_BUS, kD2257_GPIO6_CONF2, (1<<3)|(2<<0) }, // 0x0A VBUCK3, 10ms
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// GPIO7: GPIO_BT_TO_PMU_HOST_WAKE
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{ PMU_IIC_BUS, kD2257_GPIO7_CONF1, (0<<6)|(2<<3)|(0<<1)|(1<<0) }, // 0x11 Input, RE, No PU/PD, Wakeup
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{ PMU_IIC_BUS, kD2257_GPIO7_CONF2, (1<<3)|(1<<0) }, // 0x09 VBUCK3, 5ms
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// GPIO8: GPIO_WLAN_TO_PMU_HOST_WAKE
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{ PMU_IIC_BUS, kD2257_GPIO8_CONF1, (0<<6)|(2<<3)|(2<<1)|(1<<0) }, // 0x15 Input, RE, PD, Wakeup
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{ PMU_IIC_BUS, kD2257_GPIO8_CONF2, (1<<3)|(1<<0) }, // 0x09 VBUCK3, 5ms
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// GPIO10: GPIO_CODEC_TO_PMU_WAKE_L
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{ PMU_IIC_BUS, kD2257_GPIO10_CONF1, (0<<6)|(4<<3)|(1<<1)|(1<<0) }, // 0x23 Input, AnyE, PU, Wakeup
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{ PMU_IIC_BUS, kD2257_GPIO10_CONF2, (1<<3)|(2<<0) }, // 0x0A VBUCK3, 10ms
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// GPIO11: GPIO_STB_HALL_TO_PMU_IRQ_L
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{ PMU_IIC_BUS, kD2257_GPIO11_CONF1, (0<<6)|(4<<3)|(1<<1)|(1<<0) }, // 0x23 Input, AnyE, PU, WakeUp
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{ PMU_IIC_BUS, kD2257_GPIO11_CONF2, (1<<3)|(1<<0) }, // 0x09 VBUCK3, 5ms
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// GPIO12: GPIO_TS_TO_SOC_TO_PMU_IRQ
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{ PMU_IIC_BUS, kD2257_GPIO12_CONF1, (0<<6)|(0<<3)|(0<<1)|(1<<0) }, // 0x01 Input, AH, No PU/PD, Wakeup
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{ PMU_IIC_BUS, kD2257_GPIO12_CONF2, (1<<3)|(1<<0) }, // 0x09 VBUCK3, 5ms
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// GPIO13: GPIO_BELFIELD_TO_PMU_WAKE_L (was GPIO_IO_EXP_TO_PMU_IRQ)
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{ PMU_IIC_BUS, kD2257_GPIO13_CONF1, (0<<6)|(4<<3)|(1<<1)|(1<<0) }, // 0x23 Input, AnyE, PU, WakeUp
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{ PMU_IIC_BUS, kD2257_GPIO13_CONF2, (1<<3)|(2<<0) }, // 0x0A VBUCK3, 10ms
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// GPIO14: GPIO_EUPHRATES_TO_PMU_WAKE (was PCIE_WLAN_TO_PMU_WAKE_L)
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{ PMU_IIC_BUS, kD2257_GPIO14_CONF1, (0<<6)|(0<<3)|(0<<1)|(1<<0) }, // 0x01 Input, AH, No PU/PD, WakeUp
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{ PMU_IIC_BUS, kD2257_GPIO14_CONF2, (3<<3)|(1<<0) }, // 0x19 PP1V8_ALWAYS, 5ms
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// GPIO15: GPIO_EUPHRATES_TO_SOC_TO_PMU_IRQ_L (was GPIO_PMU_TO_CODEC_RESET_L)
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{ PMU_IIC_BUS, kD2257_GPIO15_CONF1, (0<<6)|(3<<3)|(1<<1)|(1<<0) }, // 0x1B Input, FE, PU, WakeUp
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{ PMU_IIC_BUS, kD2257_GPIO15_CONF2, (3<<3)|(2<<0) }, // 0x1A PP1V8_ALWAYS, 10ms
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// GPIO16: GPIO_PMU_TO_NAND_LOW_BATT_L
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// kD2257_GPIO16_CONF1 gets set in target_late_init()
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{ PMU_IIC_BUS, kD2257_GPIO16_CONF2, (1<<3)|(0<<0) }, // 0x08 VBUCK3, no DEB
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// GPIO18: Enable GPIO_PMU_TO_LCD_PWREN
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{ PMU_IIC_BUS, kD2257_GPIO18_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // 0x80 Output(Push-Pull), Level, No PU/PD, Low
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{ PMU_IIC_BUS, kD2257_GPIO18_CONF2, (1<<3)|(0<<0) }, // 0x08 VBUCK3, no DEB
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// GPIO9: GPIO_BB_TO_PMU_HOST_WAKE_L
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{ PMU_IIC_BUS, kD2257_GPIO9_CONF1, (0<<6)|(1<<3)|(2<<1)|(0<<0) }, // 0x0C Input, AL, PD
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{ PMU_IIC_BUS, kD2257_GPIO9_CONF2, (1<<3)|(1<<0) }, // 0x09 VBUCK3, 5ms
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#if TARGET_HAS_BASEBAND
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// GPIO5: GPIO_PMU_TO_BBPMU_RESET_R_L (rdar://20064772, rdar://20110706, rdar://21211826)
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{ PMU_IIC_BUS, kD2257_GPIO5_CONF1, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // 0x80 Output(Push-Pull), Level, no PU/PD, Low
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{ PMU_IIC_BUS, kD2257_GPIO5_CONF2, (1<<3)|(0<<0) }, // 0x08 VBUCK3, no DEB
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// GPIO17: GPIO_PMU_TO_BB_VBUS_DET
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{ PMU_IIC_BUS, kD2257_GPIO17_CONF1, (2<<6)|(0<<3)|(0<<1)|(1<<0) }, // 0x81 Output(Push-Pull), Level, No PU/PD, High
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{ PMU_IIC_BUS, kD2257_GPIO17_CONF2, (0<<3)|(0<<0) }, // 0x00 VCC_MAIN, no DEB
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#else
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// GPIO5: GPIO_PMU_TO_BBPMU_RESET_R_L
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{ PMU_IIC_BUS, kD2257_GPIO5_CONF1, (0<<6)|(0<<3)|(2<<1)|(0<<0) }, // 0x40 Input, AH, PD
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{ PMU_IIC_BUS, kD2257_GPIO5_CONF2, (1<<3)|(0<<0) }, // 0x08 VBUCK3, no DEB
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// GPIO17: GPIO_PMU_TO_BB_VBUS_DET
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{ PMU_IIC_BUS, kD2257_GPIO17_CONF1, (0<<6)|(0<<3)|(2<<1)|(0<<0) }, // 0x40 Input, AH, PD
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{ PMU_IIC_BUS, kD2257_GPIO17_CONF2, (1<<3)|(0<<0) }, // 0x08 VBUCK3, no DEB
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#endif
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// GPIO19: GPIO_PMU_TO_EUPHRATES_LINCH_EN (was GPIO_GANGES_TO_PMU_WAKE)
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{ PMU_IIC_BUS, kD2257_GPIO19_CONF1_SLP1,(1<<6)|(0<<3)|(0<<1)|(1<<0) }, // 0x41 Output(Open Drain), Level, No PU/PD, High
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{ PMU_IIC_BUS, kD2257_GPIO19_CONF1_SLP2,(1<<6)|(0<<3)|(0<<1)|(1<<0) }, // 0x41 Output(Open Drain), Level, No PU/PD, High
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{ PMU_IIC_BUS, kD2257_GPIO19_CONF1_SLP3,(1<<6)|(0<<3)|(0<<1)|(1<<0) }, // 0x41 Output(Open Drain), Level, No PU/PD, High
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{ PMU_IIC_BUS, kD2257_GPIO19_CONF1_OFF, (1<<6)|(0<<3)|(0<<1)|(0<<0) }, // 0x40 Output(Open Drain), Level, No PU/PD, Low
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{ PMU_IIC_BUS, kD2257_GPIO19_CONF1, (1<<6)|(0<<3)|(0<<1)|(1<<0) }, // 0x41 Output(Open Drain), Level, No PU/PD, High
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{ PMU_IIC_BUS, kD2257_GPIO19_CONF2, (1<<3)|(0<<0) }, // 0x08 VBUCK3, no DEB
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// GPIO20: GPIO_PMU_TO_1V1_EXT_SW_ON
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{ PMU_IIC_BUS, kD2257_GPIO20_CONF1_SLP1,(2<<6)|(0<<3)|(0<<1)|(1<<0) }, // 0x81 Output(Push-Pull), Level, No PU/PD, High
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{ PMU_IIC_BUS, kD2257_GPIO20_CONF1_SLP2,(2<<6)|(0<<3)|(0<<1)|(0<<0) }, // 0x80 Output(Push-Pull), Level, No PU/PD, Low
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{ PMU_IIC_BUS, kD2257_GPIO20_CONF1_SLP3,(2<<6)|(0<<3)|(0<<1)|(0<<0) }, // 0x80 Output(Push-Pull), Level, No PU/PD, Low
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{ PMU_IIC_BUS, kD2257_GPIO20_CONF1_OFF, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // 0x80 Output(Push-Pull), Level, No PU/PD, Low
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{ PMU_IIC_BUS, kD2257_GPIO20_CONF1, (2<<6)|(0<<3)|(0<<1)|(1<<0) }, // 0x81 Output(Push-Pull), Level, No PU/PD, High
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{ PMU_IIC_BUS, kD2257_GPIO20_CONF2, (1<<3)|(0<<0) }, // 0x08 VBUCK3, no DEB
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// GPIO21: GPIO_PMU_TO_1V8_EXT_SW2_ON
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{ PMU_IIC_BUS, kD2257_GPIO21_CONF1_SLP1,(2<<6)|(0<<3)|(0<<1)|(1<<0) }, // 0x81 Output(Push-Pull), Level, No PU/PD, Low
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{ PMU_IIC_BUS, kD2257_GPIO21_CONF1_SLP2,(2<<6)|(0<<3)|(0<<1)|(1<<0) }, // 0x81 Output(Push-Pull), Level, No PU/PD, Low
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{ PMU_IIC_BUS, kD2257_GPIO21_CONF1_SLP3,(2<<6)|(0<<3)|(0<<1)|(0<<0) }, // 0x80 Output(Push-Pull), Level, No PU/PD, Low
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{ PMU_IIC_BUS, kD2257_GPIO21_CONF1_OFF, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // 0x80 Output(Push-Pull), Level, No PU/PD, Low
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{ PMU_IIC_BUS, kD2257_GPIO21_CONF1, (2<<6)|(0<<3)|(0<<1)|(1<<0) }, // 0x81 Output(Push-Pull), Level, No PU/PD, High
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{ PMU_IIC_BUS, kD2257_GPIO21_CONF2, (1<<3)|(0<<0) }, // 0x08 VBUCK3, no DEB
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// GPIO22: GPIO_PMU_TO_3V3_EXT_SW_ON (was GPIO_GANGES_TO_SOC_TO_PMU_IRQ_L)
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{ PMU_IIC_BUS, kD2257_GPIO22_CONF1_SLP1,(2<<6)|(0<<3)|(0<<1)|(0<<0) }, // 0x80 Output(Push-Pull), Level, No PU/PD, Low
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{ PMU_IIC_BUS, kD2257_GPIO22_CONF1_SLP2,(2<<6)|(0<<3)|(0<<1)|(0<<0) }, // 0x80 Output(Push-Pull), Level, No PU/PD, Low
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{ PMU_IIC_BUS, kD2257_GPIO22_CONF1_SLP3,(2<<6)|(0<<3)|(0<<1)|(0<<0) }, // 0x80 Output(Push-Pull), Level, No PU/PD, Low
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{ PMU_IIC_BUS, kD2257_GPIO22_CONF1_OFF, (2<<6)|(0<<3)|(0<<1)|(0<<0) }, // 0x80 Output(Push-Pull), Level, No PU/PD, Low
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{ PMU_IIC_BUS, kD2257_GPIO22_CONF1, (2<<6)|(0<<3)|(0<<1)|(1<<0) }, // 0x81 Output(Push-Pull), Level, No PU/PD, High
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{ PMU_IIC_BUS, kD2257_GPIO22_CONF2, (1<<3)|(0<<0) }, // 0x08 VBUCK3, no DEB
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};
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static const struct pmu_setup_struct pmu_backlight_enable[] =
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{
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{ PMU_IIC_BUS, kDIALOG_WLED_ISET, 0x06 }, // 75% of max 0x7FF
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{ PMU_IIC_BUS, kDIALOG_WLED_ISET2, 0x00 },
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{ PMU_IIC_BUS, kD2257_WLED_CTRL1, // enable all LED strings
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(kDIALOG_WLED_CONTROL_WLED_ENABLE1 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE2 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE3 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE4 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE5 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE6) },
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{ PMU_IIC_BUS, kD2257_WLED_CTRL2, // enable all LED strings
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(kDIALOG_WLED_CONTROL_WLED_ENABLE1 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE2 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE3 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE4 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE5 |
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kDIALOG_WLED_CONTROL_WLED_ENABLE6) },
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{ PMU_IIC_BUS, kD2257_PWRONOFF_WLEDA_EN, 0x1 }, // enable LED Power
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{ PMU_IIC_BUS, kD2257_PWRONOFF_WLEDB_EN, 0x1 }, // enable LED Power
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};
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static const struct pmu_setup_struct pmu_backlight_disable[] =
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{
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{ PMU_IIC_BUS, kD2257_PWRONOFF_WLEDA_EN, 0x0 }, // disable LED Power
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{ PMU_IIC_BUS, kD2257_PWRONOFF_WLEDB_EN, 0x0 }, // disable LED Power
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};
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static const struct core_rails_struct soc_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2257_BUCK2_VSEL }
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};
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static const struct core_rails_struct cpu_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2257_BUCK0_VSEL }
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};
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// It's VDD FIXED! used for RAM inside the SOC
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static const struct core_rails_struct ram_rails[] =
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{
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{ PMU_IIC_BUS, 0, kD2257_BUCK5_VSEL }
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};
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// This is indexed with POWER_RAIL_*, I really just need to use the
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// index in LDO[]
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target_rails_t target_rails = {
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{ 0x10, 450, 1250, 3125 }, // POWER_RAIL_CPU, BUCK0
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{ 0x15, 600, 1400, 3125 }, // POWER_RAIL_VDD_FIXED BUCK5
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{ 0x12, 600, 1400, 3125 }, // POWER_RAIL_SOC, BUCK2
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{ 0x17, 600, 1400, 3125 }, // POWER_RAIL_CPU_RAM, BUCK7
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{ 0x11, 450, 1250, 3125 }, // POWER_RAIL_GPU, BUCK1
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{ 0x18, 600, 1400, 3125 }, // POWER_RAIL_GPU_RAM, BUCK8
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};
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#endif // POWERCONFIG_PMU_SETUP
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#define NO_BATTERY_VOLTAGE 2700
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#define MIN_BOOT_BATTERY_VOLTAGE 3600
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#define TARGET_BOOT_BATTERY_VOLTAGE 3700
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#define TARGET_BOOT_BATTERY_CAPACITY 50
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#define PRECHARGE_BACKLIGHT_LEVEL 824
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#define ALWAYS_BOOT_BATTERY_VOLTAGE (TARGET_BOOT_BATTERY_VOLTAGE + 100)
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#define TARGET_MAX_USB_INPUT_CURRENT 2400
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#define TARGET_PRECHARGE_ALWAYS_DISPLAY_IDLE 1
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#define ACC_PWR_LDO (6)
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#define GASGAUGE_BATTERYID_BLOCK 1
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#endif
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