first and last commit

platform/s5l8747x/asm.S

@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <arch/arm/assembler.h>
+#include <platform/memmap.h>
+
+	.text
+
+ARM_FUNCTION _platform_start
+	
+#if WITH_PROFILE && PROFILE_BUF_SIZE > 0
+	// Turn on PCLK to TIM64
+	mov		r2, #0x0200
+	movt		r2, #0x3c50
+	ldr		r3, [r2, #4]
+	bic		r3, #(1 << 30)
+	str		r3, [r2, #4]
+	
+	// Turn on NCLK to TIM64
+	ldr		r3, [r2, #0x10]
+	bic		r3, #(1 << 8)
+	str		r3, [r2, #0x10]
+
+	// Enable TIM64
+	mov		r2, #0x0088
+	movt		r2, #0x3c70
+	// r3 = (r<<15)|(1<<4)
+	mov		r3, #((1 << 15) | (1 << 4))
+	movt		r3, #1
+	str		r3, [r2]
+#endif
+
+	bx		lr
+
+	

platform/s5l8747x/chipid/chipid.c

@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <platform.h>
+#include <platform/soc/chipid.h>
+#include <platform/soc/hwclocks.h>
+
+bool chipid_get_production_mode(void)
+{
+	while (!chipid_get_read_done());
+
+	return ((rCHIPIDL >> 0) & 1) != 0;
+}
+
+bool chipid_get_secure_mode(void)
+{
+	while (!chipid_get_read_done());
+
+	return ((rCHIPIDH >> 1) & 1) != 0;
+}
+
+u_int32_t chipid_get_security_domain(void)
+{
+	while (!chipid_get_read_done());
+
+#if SUPPORT_FPGA
+	return kPlatformSecurityDomainDarwin;
+#else
+	return (rCHIPIDH >> 1) & 3;
+#endif
+}
+
+u_int32_t chipid_get_minimum_epoch(void)
+{
+	while (!chipid_get_read_done());
+
+	return (rCHIPIDH >> 3) & 0x7F;
+}
+
+bool chipid_get_ecid_image_personalization_required(void)
+{
+	return ((rCHIPIDH >> 14) & 1) != 0;
+}
+
+u_int32_t chipid_get_board_id(void)
+{
+	while (!chipid_get_read_done());
+
+	return (rCHIPIDH >> 10) & 3;
+}
+
+u_int32_t chipid_get_chip_id(void)
+{
+	while (!chipid_get_read_done());
+
+	return (rCHIPIDH >> 16) & 0xFFFF;
+}
+
+u_int32_t chipid_get_chip_revision(void)
+{
+	while (!chipid_get_read_done());
+
+	return (((rCHIPIDL >> 24) & 0xF) << 4) | (((rCHIPIDL >> 28) & 0xF) << 0);
+}
+
+u_int32_t chipid_get_osc_frequency(void)
+{
+	return OSC_FREQ;
+}
+
+u_int64_t chipid_get_ecid_id(void)
+{
+	u_int64_t ecid = 0;
+
+	while (!chipid_get_read_done());
+
+#if SUPPORT_FPGA
+	ecid = 0x000012345678ABCDULL;
+#else
+	/*
+	 * For the sake of the next poor bastard that comes along and has
+	 * to decode the ECID produced by this silliness, the code here
+	 * produces output formatted thus:
+	 *
+	 * 6              4               3               1
+	 * 3              8               2               6               0
+	 * ......................lllllllllllllllllllllwwwwwyyyyyyyyxxxxxxxx
+	 *
+	 * l - lot number
+	 * w - wafer number
+	 * y - wafer y position
+	 * x - wafer x position
+	 */
+	ecid |= ((rDIEIDL >>  0)) & ((1ULL << (21 -  0)) - 1);	// LOT_ID
+
+	ecid <<= (26 - 21);
+	ecid |= ((rDIEIDL >> 21)) & ((1ULL << (26 - 21)) - 1);	// WAFER_NUM
+
+	ecid <<= (10 -  2);
+	ecid |= ((rDIEIDH >>  2)) & ((1ULL << (10 -  2)) - 1);	// Y_POS
+
+	ecid <<= (32 - 26);
+	ecid |= ((rDIEIDL >> 26)) & ((1ULL << (32 - 26)) - 1);	// X_POS_H
+
+	ecid <<= ( 2 -  0);
+	ecid |= ((rDIEIDH >>  0)) & ((1ULL << ( 2 -  0)) - 1);	// X_POS_L
+#endif
+
+	return ecid;
+}
+
+u_int64_t chipid_get_die_id(void)
+{
+	while (!chipid_get_read_done());
+
+	return ((u_int64_t)rDIEIDH << 32) | rDIEIDL;
+}
+
+//  chipid_get_tv_dac_cals
+//    Saves the three tv dac calibration values in the given array.
+//
+void chipid_get_tv_dac_cals(u_int32_t *dac_cals)
+{
+	while (!chipid_get_read_done());
+
+	dac_cals[0] = (rCHIPIDL >>  9) & 0x1F;
+	dac_cals[1] = (rCHIPIDL >> 14) & 0x1F;
+	dac_cals[2] = (rCHIPIDL >> 19) & 0x1F;
+}
+
+bool chipid_get_read_done(void)
+{
+#if !SUPPORT_FPGA
+	return ((rEFUSE_READ_DONE >> 0) & 1) != 0;
+#else
+	return true;
+#endif
+}
+

platform/s5l8747x/chipid/rules.mk

@@ -0,0 +1,15 @@
+# Copyright (C) 2011 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_PLATFORM_CHIPID=1
+
+ALL_OBJS += $(LOCAL_DIR)/chipid.o

platform/s5l8747x/clocks/clocks.c

@@ -0,0 +1,504 @@
+/*
+ * Copyright (C) 2011-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <debug.h>
+#include <platform.h>
+#include <lib/libc.h>
+#include <platform/clocks.h>
+#include <platform/timer.h>
+#include <platform/soc/clocks.h>
+#include <platform/soc/hwclocks.h>
+#include <platform/soc/chipid.h>
+#include <sys.h>
+#include <sys/boot.h>
+#include <sys/menu.h>
+
+#include <drivers/power.h>
+
+
+#define PLL_FREQ_TARGET(pllx) (1ULL * pllx##_O * pllx##_M / pllx##_P / (1 << pllx##_S))
+
+#define PRESCALE_EN(x)	((x) == 1 ? 0 : 1)
+#define CLK_DIV_N(x)	((x) == 1 ? 0 : ((x)/2)-1)
+
+#if APPLICATION_IBOOT
+
+//PLL0 @ 800MHz
+#define PLL0		0
+#define PLL0_O		OSC_FREQ
+#define PLL0_P		12
+#define PLL0_M		400
+#define PLL0_S		0
+#define PLL0_VSEL	1 // High if 600MHz < Fvco < 864MHz (Fvco = Fin * M / P)
+#define PLL0_T		PLL_FREQ_TARGET(PLL0)
+
+// PLL1 @ 330MHz
+#define PLL1		1
+#define PLL1_O		OSC_FREQ
+#define PLL1_P		4
+#define PLL1_M		110
+#define PLL1_S		1
+#define PLL1_VSEL	1 // High if 600MHz < Fvco < 864MHz (Fvco = Fin * M / P)
+#define PLL1_T		PLL_FREQ_TARGET(PLL1)
+
+// PLL2 @ 432MHz
+#define PLL2		2
+#define PLL2_O		OSC_FREQ
+#define PLL2_P		5
+#define PLL2_M		180
+#define PLL2_S		1
+#define PLL2_VSEL	1 // High if 600MHz < Fvco < 864MHz (Fvco = Fin * M / P)
+#define PLL2_T		PLL_FREQ_TARGET(PLL2432/)
+
+#define LOW_PERF_DIV_N		(11)
+#define MEDIUM_PERF_DIV_N	(5)
+#define MEMORY_PERF_DIV_N	(2)
+// With PLL0 @ 800MHz for B0, SCLK_DIV_VAL needs to be at least 2!
+#define HIGH_PERF_DIV_N		(2)
+
+#endif /* APPLICATION_IBOOT */
+
+#if APPLICATION_SECUREROM
+
+#define PLL0		0
+#define PLL0_O		OSC_FREQ
+#define PLL0_P		6
+#define PLL0_M		133
+#define PLL0_S		2
+#define PLL0_VSEL	0
+#define PLL0_T		PLL_FREQ_TARGET(PLL0)
+
+#define LOW_PERF_DIV_N		(1)
+#define MEDIUM_PERF_DIV_N	(1)
+#define MEMORY_PERF_DIV_N	(2)
+#define HIGH_PERF_DIV_N		(1)
+
+#endif /* APPLICATION_SECUREROM */
+
+#define SCLK_PLL	0
+#define FCLK_DIV_N	(1)
+#define DCLK_DIV_N	(1)
+#define ACLK_DIV_N	(MEMORY_PERF_DIV_N)
+#define HCLK_DIV_N	(MEMORY_PERF_DIV_N)
+#define PCLK_DIV_N	(MEMORY_PERF_DIV_N)
+
+#define NCLK_DIV_N	(1)
+
+/* current clock speeds */
+static u_int32_t clks[CLKGEN_CLK_COUNT];
+static u_int32_t *plls = &clks[CLKGEN_CLK_PLL0];
+
+static u_int32_t perf_level;
+static u_int32_t perf_div;
+
+static u_int32_t get_pll(int pll);
+
+int clocks_init(void)
+{
+#if APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC)
+	
+#if SUPPORT_FPGA
+	clks[CLKGEN_CLK_SCLK] = 10000000;
+	clks[CLKGEN_CLK_FCLK] = 10000000;
+	clks[CLKGEN_CLK_DCLK] = 10000000;
+	clks[CLKGEN_CLK_ACLK] = 10000000;
+	clks[CLKGEN_CLK_HCLK] = 10000000;
+	clks[CLKGEN_CLK_PCLK] = 10000000;
+	clks[CLKGEN_CLK_NCLK] = 10000000;
+	clks[CLKGEN_CLK_USBPHY] = 12000000;
+
+	perf_div = 1;
+	perf_level = kPerformanceHigh;
+
+#else
+#error "The calculations of vclk0 and vclk1 need to be scrubbed"
+	int cnt;
+	int sclk_pll	= ((rCLKCON0 >> 12) & 3) - 1;
+	int sclk_div_n	= ((rCLKCON0 >>  0) & 0xF) + 1;
+	int fclk_div_n	= ((rCLKCON1 >> 29) & 1) ? ((((rCLKCON1 >> 24) & 0x1F) + 1) * 2) : 1;
+	int dclk_div_n	= ((rCLKCON1 >> 23) & 1) ? ((((rCLKCON1 >> 18) & 0x1F) + 1) * 2) : 1;
+	int hclk_div_n	= ((rCLKCON1 >> 17) & 1) ? ((((rCLKCON1 >> 12) & 0x1F) + 1) * 2) : 1;
+	int pclk_div_n	= ((rCLKCON1 >> 11) & 1) ? ((((rCLKCON1 >>  6) & 0x1F) + 1) * 2) : 1;
+	int aclk_div_n	= ((rCLKCON1 >>  5) & 1) ? ((((rCLKCON1 >>  0) & 0x1F) + 1) * 2) : 1;
+	int vclk0_pll	= ((rCLKCON2 >> 28) & 3) - 1;
+	int vclk0_div_n	= ((rCLKCON2 >> 16) & 0xF) + 1;
+	int vclk1_pll	= ((rCLKCON2 >> 12) & 3) - 1;
+	int vclk1_div_n	= (((rCLKCON2 >> 0) & 0xF) + 1) * (((rCLKCON2 >> 4) & 0xF) + 1);
+	
+	plls[-1] = OSC_FREQ;
+	for (cnt = 0; cnt < 3; cnt++) plls[cnt] = get_pll(cnt);
+	
+	perf_div = sclk_div_n;
+
+	switch (perf_div) {
+		default :
+		case HIGH_PERF_DIV_N : perf_level = kPerformanceHigh; break;
+		case MEDIUM_PERF_DIV_N : perf_level = kPerformanceMedium; break;
+		case LOW_PERF_DIV_N : perf_level = kPerformanceLow; break;
+	}
+
+	clks[CLKGEN_CLK_SCLK] = plls[sclk_pll] / HIGH_PERF_DIV_N;
+	clks[CLKGEN_CLK_FCLK] = clks[CLKGEN_CLK_SCLK] / fclk_div_n;
+	clks[CLKGEN_CLK_DCLK] = clks[CLKGEN_CLK_SCLK] / dclk_div_n;
+	clks[CLKGEN_CLK_ACLK] = clks[CLKGEN_CLK_SCLK] / aclk_div_n;
+	clks[CLKGEN_CLK_HCLK] = clks[CLKGEN_CLK_SCLK] / hclk_div_n;
+	clks[CLKGEN_CLK_PCLK] = clks[CLKGEN_CLK_SCLK] / pclk_div_n;
+	clks[CLKGEN_CLK_VCLK0] = plls[vclk0_pll] / vclk0_div_n;
+	clks[CLKGEN_CLK_VCLK1] = plls[vclk1_pll] / vclk1_div_n;
+	
+	clks[CLKGEN_CLK_NCLK] = OSC_FREQ;
+	
+	clks[CLKGEN_CLK_USBPHY] = OSC_FREQ;
+#endif
+	
+#endif /* APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC) */
+
+	return 0;
+}
+
+static u_int32_t get_pll(int pll)
+{
+	volatile u_int32_t *pllpms;
+	u_int32_t pllcon, pms;
+	u_int64_t freq;
+	
+	pllcon = rPLLCON;
+	
+	if (((pllcon >> pll) & 1) == 0) return OSC_FREQ;
+	
+	switch (pll) {
+		case 0:
+			pllpms = &rPLL0PMS;
+			break;
+		case 1:
+			pllpms = &rPLL1PMS;
+			break;
+		case 2:
+			pllpms = &rPLL2PMS;
+			break;
+		case 3:
+			pllpms = &rPLL3PMS;
+			break;
+		default:
+			return 0;
+			break;
+	}
+	
+	freq = OSC_FREQ;
+	pms = *pllpms;
+	
+	freq *= (pms >> 8) & 0x3FF;  // *M
+	
+	freq /= (pms >> 24) & 0x3F;  // /P
+	
+	freq /= 1 << (pms & 0x07);   // /2^S
+	
+	return freq;
+}
+
+static void set_pll(int pll, u_int32_t p, u_int32_t m, u_int32_t s, u_int32_t vsel)
+{
+	volatile u_int32_t *pllpms;
+	volatile u_int32_t *plllcnt;
+
+	switch (pll) {
+		case 0:
+			pllpms = &rPLL0PMS;
+			plllcnt = &rPLL0LCNT;
+			break;
+		case 1:
+			pllpms = &rPLL1PMS;
+			plllcnt = &rPLL1LCNT;
+			break;
+		case 2:
+			pllpms = &rPLL2PMS;
+			plllcnt = &rPLL2LCNT;
+			break;
+		case 3:
+			pllpms = &rPLL3PMS;
+			plllcnt = &rPLL3LCNT;
+			break;
+		default:
+			return;
+	}
+
+	*pllpms = (vsel << 30) | (p << 24) | (m << 8) | (s << 0);	// set p/m/s values
+	*plllcnt = 300 * 24;						// set lock counter for 300us
+	rPLLCON |= (1<<(0+pll));					// pll power up
+#if !SUPPORT_FPGA
+	while ((rPLLLOCK & (1 << pll)) == 0);				// wait for pll to lock
+#endif /* ! SUPPORT_FPGA */
+	*pllpms = (vsel << 30) | (p << 24) | (m << 8) | (s << 0);	// set p/m/s values again
+	rPLLCON |= (1<<(16+pll));					// pll select output
+}
+
+int clocks_set_default(void)
+{
+	uint32_t cnt;
+
+	/* Change all the clocks to something safe */
+	clocks_quiesce();
+	
+	/* set up the clock tree to our default setting */
+	clks[CLKGEN_CLK_OSC] = OSC_FREQ;
+	
+#ifdef PLL0_T
+	set_pll(0, PLL0_P, PLL0_M, PLL0_S, PLL0_VSEL);
+#endif
+	
+#ifdef PLL1_T
+	set_pll(1, PLL1_P, PLL1_M, PLL1_S, PLL2_VSEL);
+#endif
+	
+#ifdef PLL2_T
+	set_pll(2, PLL2_P, PLL2_M, PLL2_S, PLL2_VSEL);
+#endif
+
+#ifdef PLL3_T
+	set_pll(3, PLL3_P, PLL3_M, PLL3_S, PLL3_VSEL);
+#endif
+
+	// Use get_pll() to establish the frequencies (unconfigured PLLs will bypass OSC)
+	for (cnt = 0; cnt < 4; cnt++) plls[cnt] = get_pll(cnt);
+	
+	perf_level = kPerformanceHigh;
+	perf_div = HIGH_PERF_DIV_N;
+	
+	clks[CLKGEN_CLK_SCLK] = plls[SCLK_PLL] / perf_div;
+	clks[CLKGEN_CLK_FCLK] = clks[CLKGEN_CLK_SCLK] / FCLK_DIV_N;
+	clks[CLKGEN_CLK_DCLK] = clks[CLKGEN_CLK_SCLK] / DCLK_DIV_N;
+	clks[CLKGEN_CLK_ACLK] = clks[CLKGEN_CLK_SCLK] / ACLK_DIV_N;
+	clks[CLKGEN_CLK_HCLK] = clks[CLKGEN_CLK_SCLK] / HCLK_DIV_N;
+	clks[CLKGEN_CLK_PCLK] = clks[CLKGEN_CLK_SCLK] / PCLK_DIV_N;
+	clks[CLKGEN_CLK_NCLK] = clks[CLKGEN_CLK_OSC] / NCLK_DIV_N;
+	clks[CLKGEN_CLK_USBPHY] = clks[CLKGEN_CLK_OSC];
+	
+	// switch the useful clocks back to their plls
+	rCLKCON1 = 
+		   (PRESCALE_EN(FCLK_DIV_N)<<29)|(CLK_DIV_N(FCLK_DIV_N)<<24) |		// FCLK
+		   (PRESCALE_EN(DCLK_DIV_N)<<23)|(CLK_DIV_N(DCLK_DIV_N)<<18) |		// DCLK
+		   (PRESCALE_EN(HCLK_DIV_N)<<17)|(CLK_DIV_N(HCLK_DIV_N)<<12) |		// HCLK
+		   (PRESCALE_EN(PCLK_DIV_N)<<11)|(CLK_DIV_N(PCLK_DIV_N)<< 6) |		// PCLK
+		   (PRESCALE_EN(ACLK_DIV_N)<< 5)|(CLK_DIV_N(ACLK_DIV_N)<< 0);		// ACLK
+	// must set divider before switching to PLL because of delay in divider taking effect
+	// <rdar://problem/11951206> Race condition in CLKCON register setting causes unpredictable behavior
+	rCLKCON0 = ((perf_div-1)<<0);
+	rCLKCON0 |= ((SCLK_PLL+1)<<12);
+	rCLKCON2 = (0<<15)|(1<<31);				// CLK_OUT0 enable, CLK_OUT1 disable
+	rCLKCON3 = (1<<31)|(2<<28)|(7<<16)			// VCLK_DAC source PLL2, div 7+1, disable
+		 | (1<<15)|(3<<12)|(0<<4)|(0<<0);		// RGBOUT_CLK source PLL3, div 1, disable
+	rCLKCON4 = (1<<31)|(0<<28)|(0<<16)			// MCLK1 source OSC,  div 1, disable
+		|(1<<15)|(3<<12)|(0<<4)|(0<<0);			// MCLK0 source PLL3, div 1, disable
+	rCLKCON5 = (1<<31)|(0<<28)|(0<<16)			// MCLK3 source OSC, div 1, disable
+		|(1<<15)|(0<<12)|(0<<0); 				// MCLK2 source OSC, div 1, disable
+		
+	rCLKCON6 = (0<<28)|((NCLK_DIV_N-1)<<16)		// NCLK source OSC, enable
+		|(1<<15)|(2<<12);						// MFC_CLK source PLL1, div 0+1, disable
+	
+	rCLKCON7 = (0x1F<<27)|(1<<24)|(3<<16)		// VMHCLKx source PLL0, div 3+1, disable
+		|(1<<15)|(1<<12)|(2<<0);		// SCALER source PLL0, div 2+1, disable
+	
+#if SUPPORT_FPGA
+	clks[CLKGEN_CLK_SCLK] = 10000000;
+	clks[CLKGEN_CLK_FCLK] = 10000000;
+	clks[CLKGEN_CLK_DCLK] = 10000000;
+	clks[CLKGEN_CLK_ACLK] = 10000000;
+	clks[CLKGEN_CLK_HCLK] = 10000000;
+	clks[CLKGEN_CLK_PCLK] = 10000000;
+	clks[CLKGEN_CLK_NCLK] = 10000000;
+	clks[CLKGEN_CLK_USBPHY] = 12000000;
+#endif
+	
+	return 0;
+}
+
+void clocks_quiesce(void)
+{
+	// Turn off non-critical device clocks
+	rCGCON0 = 0x00001CBF;	// HCLK to VROM
+	rCGCON1 = 0x3FC5EFFF;	// PCLKs to DREX, Timer64, Cortex-A5 Debug and Sys, AXI, and GPIO
+	rCGCON2 = 0x0000001F;
+	rCGCON3 = 0x00000000;	// ACLKs to AXI, XMC, and SRAM
+	rCGCON4 = 0x003DFEFF;	// NCLK to DREX and Timer64 on
+
+	// Set OSC to select the 12/24MHz clock
+	//rPLLCON &= ~(1 << 8); // FIXME
+
+	// Set all of the clocks to use OSC bypass.
+	// Disable the clocks that will not be used.
+	rCLKCON0 &= ~(0x3<<12);		// Use OSC bypass for SCLK ahead of turning off divider
+	rCLKCON0 = (1<<30);		// MCLK disable, SCLK enable, use OSC bypass, disable prescalar
+	rCLKCON1 = 0;			// FCLK/HCLK/PCLK/ACLK enable, use OSC bypass, disable prescalar
+	rCLKCON2 = (1<<31)|(1<<15);	// CLK_OUT1/CLK_OUT0 disable
+	rCLKCON3 = (1<<31)|(1<<15);	// VCLK_DAC/RGBOUT_VCLK disable
+	rCLKCON4 = (1<<31)|(1<<15);	// MCLK1/MCLK0 disable
+	rCLKCON5 = (1<<31)|(1<<15);	// MCLK3/MCLK2 disable
+	rCLKCON6 = (1<<15);		// NCLK enable, MFC_CLK disable
+	rCLKCON7 = (0x1F<<27)|(1<<15);	// VMHCLKx/SCALER disable
+
+	// Bypass and shut down all PLLs
+	rPLLCON &= ~0xF0000;
+	rPLLCON &= ~0x0000F;
+}
+
+u_int32_t clocks_get_performance_divider(void)
+{
+	return perf_div;
+}
+
+u_int32_t clocks_set_performance(u_int32_t performance_level)
+{
+	u_int32_t old_perf_level = perf_level;
+
+	switch (performance_level) {
+		default : performance_level = kPerformanceHigh;
+		case kPerformanceHigh: perf_div = HIGH_PERF_DIV_N; break;
+		case kPerformanceMedium: perf_div = MEDIUM_PERF_DIV_N; break;
+		case kPerformanceLow: perf_div = LOW_PERF_DIV_N; break;
+
+		case kPerformanceMemory :
+			if (old_perf_level == kPerformanceHigh) goto done;
+
+			perf_div = MEMORY_PERF_DIV_N;
+			break;
+	}
+
+	perf_level = performance_level;
+
+	if (old_perf_level == kPerformanceMemory) {
+		rCLKCON1 =
+			   (PRESCALE_EN(HCLK_DIV_N)<<22)|(CLK_DIV_N(HCLK_DIV_N)<<17) |			// HCLK
+			   (PRESCALE_EN(PCLK_DIV_N)<<14)|(CLK_DIV_N(PCLK_DIV_N)<< 9) |			// PCLK
+			   (PRESCALE_EN(ACLK_DIV_N)<< 6)|(CLK_DIV_N(ACLK_DIV_N)<< 1);			// ACLK
+	}
+
+	rCLKCON0 = (rCLKCON0 & ~0xF) | ((perf_div - 1) & 0xF);
+
+	if (perf_level == kPerformanceMemory) {
+		rCLKCON1 =
+			   (PRESCALE_EN(1)<<22)|(CLK_DIV_N(1)<<17) |					// HCLK
+			   (PRESCALE_EN(1)<<14)|(CLK_DIV_N(1)<< 9) |					// PCLK
+			   (PRESCALE_EN(1)<< 6)|(CLK_DIV_N(1)<< 1);					// ACLK
+	}
+done:
+	return old_perf_level;
+}
+
+u_int32_t clock_get_frequency(int clock)
+{
+	switch (clock) {
+		case CLK_CPU:
+		case CLK_FCLK:
+			return clks[CLKGEN_CLK_FCLK];
+		case CLK_DCLK:
+		case CLK_MEM:
+			return clks[CLKGEN_CLK_DCLK];
+		case CLK_ACLK:
+			return clks[CLKGEN_CLK_ACLK];
+		case CLK_HCLK:
+		case CLK_BUS:
+			return clks[CLKGEN_CLK_HCLK];
+		case CLK_PERIPH:
+		case CLK_PCLK:
+			return clks[CLKGEN_CLK_PCLK];
+		case CLK_NCLK:
+		case CLK_FIXED:
+			return clks[CLKGEN_CLK_NCLK];
+		case CLK_TIMEBASE:
+#if SUPPORT_FPGA
+			// <rdar://problem/10442644> Rig clock frequency data for G1 FPGA
+			return clks[CLKGEN_CLK_NCLK] / 2;
+#else
+			return clks[CLKGEN_CLK_NCLK];
+#endif
+		case CLK_USBPHYCLK:
+			return clks[CLKGEN_CLK_USBPHY];
+		case CLK_MCLK:
+		default:
+			return 0;
+	}
+}
+
+void platform_reset(bool panic)
+{
+#if WITH_BOOT_STAGE
+	if (!panic) boot_set_stage(kPowerNVRAMiBootStageOff);
+#endif
+
+	/* reset ourselves */
+	wdt_chip_reset();
+
+	while (1);
+}
+
+
+void platform_system_reset(bool panic)
+{
+	dprintf(DEBUG_INFO, "no platform system reset, using normal reset\n");
+	platform_reset(panic);
+}
+
+struct clock_gate_entry {
+	u_int32_t	gccon0_mask;
+	u_int32_t	gccon1_mask;
+	u_int32_t	gccon2_mask;
+	u_int32_t	gccon3_mask;
+	u_int32_t	gccon4_mask;
+};
+
+static const struct clock_gate_entry clock_gate_map[] =
+{
+	[CLK_AES] =	{ 0x00000080, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_CHIPID] =	{ 0x00000000, 0x00020000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_DMAC0] =	{ 0x00000800, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_DMAC1] =	{ 0x00001000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_GPIO] =	{ 0x00000000, 0x00001000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_IIC0] =	{ 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00001000 },
+	[CLK_IIC1] =	{ 0x00000000, 0x00000020, 0x00000000, 0x00000000, 0x00002000 },
+	[CLK_IIC2] =	{ 0x00000000, 0x00000040, 0x00000000, 0x00000000, 0x00004000 },
+	[CLK_PKE] =	{ 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_SHA1] =	{ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_SPI0] =	{ 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00008000 },
+	[CLK_SPI1] =	{ 0x00000000, 0x00000008, 0x00000000, 0x00000000, 0x00010000 },
+	[CLK_TIMER] =	{ 0x00000000, 0x7FC00000, 0x00000000, 0x00000000, 0x000001FF },
+	[CLK_UART0] =	{ 0x00000000, 0x00002000, 0x00000000, 0x00000000, 0x00000200 },
+	[CLK_UART1] =	{ 0x00000000, 0x00004000, 0x00000000, 0x00000000, 0x00000400 },
+	[CLK_UART2] =	{ 0x00000000, 0x00008000, 0x00000000, 0x00000000, 0x00000800 },
+	[CLK_USBOTG0] =	{ 0x00000004, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_USBOTG1] =	{ 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_USBPHY] =	{ 0x00000020, 0x00000800, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_ROSC] = 	{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 },
+};
+#define CLOCK_GATE_MAP_COUNT (sizeof(clock_gate_map) / sizeof(struct clock_gate_entry))
+
+void clock_gate(int device, bool enable)
+{
+	const struct clock_gate_entry	*entry = 0;
+
+	if (device > (int)CLOCK_GATE_MAP_COUNT)
+		panic("Invalid clock gate");
+
+	entry = &clock_gate_map[device];
+
+	if (enable) {
+		rCGCON0 &= ~entry->gccon0_mask;
+		rCGCON1 &= ~entry->gccon1_mask;
+		rCGCON2 &= ~entry->gccon2_mask;
+		rCGCON3 &= ~entry->gccon3_mask;
+		rCGCON4 &= ~entry->gccon4_mask;
+	} else {
+		rCGCON0 |= entry->gccon0_mask;
+		rCGCON1 |= entry->gccon1_mask;
+		rCGCON2 |= entry->gccon2_mask;
+		rCGCON3 |= entry->gccon3_mask;
+		rCGCON4 |= entry->gccon4_mask;
+	}
+}
+

platform/s5l8747x/clocks/rules.mk

@@ -0,0 +1,15 @@
+# Copyright (C) 2007 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_CLOCKS=1
+
+ALL_OBJS += $(LOCAL_DIR)/clocks.o

platform/s5l8747x/include/platform/gpiodef.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2011-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_GPIODEF_H
+#define __PLATFORM_GPIODEF_H
+
+/* S5L8747X specific gpio -> pin mappings */
+
+#include <platform/gpio.h>
+#include <platform/soc/hwregbase.h>
+
+#if WITH_TARGET_CONFIG
+# include <target/gpiodef.h>
+#endif
+
+/* define platform-specific gpios in a generic fashion here. */
+#define GPIO_IIC0_SCL		GPIO( 1, 1)
+#define GPIO_IIC0_SDA		GPIO( 1, 2)
+#define GPIO_IIC1_SCL		GPIO( 3, 6)
+#define GPIO_IIC1_SDA		GPIO( 3, 7)
+
+#define GPIO_BOARD_ID0		GPIO( 2, 3)
+#define GPIO_BOARD_ID1		GPIO( 2, 4)
+#define GPIO_BOARD_ID2		GPIO( 2, 5)
+#define GPIO_BOARD_ID3		GPIO( 2, 6)
+
+#define GPIO_BOOT_CONFIG0	GPIO( 2, 1)
+#define GPIO_BOOT_CONFIG1	GPIO( 2, 2)
+
+#define GPIO_FORCE_DFU		GPIO(3, 4)
+#define GPIO_DFU_STATUS		GPIO(3, 5)
+
+#define GPIO_CLK0_OUT		GPIO( 3, 0)
+
+#define SPI_NOR0		(0)
+#define SPI_NOR1		(1)
+
+#if SUPPORT_FPGA
+#define GPIO_SPI0_CS		GPIO(GPIO_PAD_SPI, 0)
+#define GPIO_SPI1_CS		GPIO(GPIO_PAD_SPI, 1)
+#else
+#define GPIO_SPI0_CS		GPIO( 1, 3)
+#define GPIO_SPI3_CS		GPIO( 4, 4)
+#endif
+
+#endif /* ! __PLATFORM_GPIODEF_H */

platform/s5l8747x/include/platform/image_devices.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_IMAGE_DEVICES_H
+#define __PLATFORM_IMAGE_DEVICES_H
+
+static const struct image_device platform_image_devices[] = {
+       { "nor0", 0x00000 }
+};
+
+#if WITH_SYSCFG
+static const struct image_device platform_syscfg_devices[] = {
+       { "nor0", 0x00000 }
+};
+#endif /* WITH_SYSCFG */
+
+#endif /* ! __PLATFORM_IMAGE_DEVICES_H */

platform/s5l8747x/include/platform/memmap.h

@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2011-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_MEMMAP_H
+#define __PLATFORM_MEMMAP_H
+
+/* S5L8747X hardware memory map */
+#define SDRAM_BASE			(0x08000000ULL)
+#define SDRAM_BANK_LEN			(0x10000000ULL)
+#define SDRAM_BANK_COUNT		1
+#define SDRAM_END			(SDRAM_BASE + (SDRAM_BANK_LEN * SDRAM_BANK_COUNT))
+#define VROM_BASE			(0x20000000ULL)
+#define VROM_BANK_LEN			(0x00100000ULL)
+#define VROM_LEN			(0x00020000ULL)
+#define SRAM_BASE			(0x22000000ULL)
+#define SRAM_BANK_LEN			(0x00400000ULL)
+#define SRAM_LEN			(0x00020000ULL)
+
+/* Sleep token is stored at first physical page in kernel memory */
+#define SLEEP_TOKEN_BUFFER_BASE		(SDRAM_BASE)
+
+/* reserved area for panic info */
+#define PANIC_SIZE		(0x00004000ULL)
+#define PANIC_BASE		(SDRAM_END - PANIC_SIZE)
+
+/* Purple graphics memory, must be 1 MB aligned */
+#define PURPLE_GFX_MEMORY_LEN	(0x09600000 - PANIC_SIZE)
+
+/* reserved area for iBoot */
+#define IBOOT_SIZE		(0x00100000 - PANIC_SIZE)
+#define IBOOT_BASE		(PANIC_BASE - IBOOT_SIZE)
+#define PROTECTED_REGION_SIZE	IBOOT_SIZE
+
+/* where to stick the mmu tt, default heap and insecure memory*/
+#if APPLICATION_SECUREROM
+#define MMU_TT_SIZE		(0x1000ULL)
+#define MMU_TT_BASE		(SRAM_BASE + SRAM_LEN - MMU_TT_SIZE)
+#define MMU_NONCACHE0_SIZE	(SRAM_BANK_LEN)
+#define MMU_NONCACHE0_PBASE	(SRAM_BASE)
+#define MMU_NONCACHE0_VBASE	(SRAM_BASE + SRAM_BANK_LEN)
+
+#define STACK_SIZE		(0x3000ULL)
+#define STACK_BASE		(MMU_TT_BASE - STACK_SIZE)
+
+#define HEAP_END		(STACK_BASE)
+
+#ifndef __ASSEMBLY__
+
+#define INSECURE_MEMORY_BASE	(SRAM_BASE)
+#define INSECURE_MEMORY_SIZE	((uintptr_t)__segment_start(__DATA) - INSECURE_MEMORY_BASE)
+
+#endif /* ! __ASSEMBLY__ */
+
+#endif /* APPLICATION_SECUREROM */
+
+/* iBoot SDRAM map
+0x08000000-0x0B000000 - Load area (48 MB)
+0x0B000000-0x0DF00000 - Kernel (47 MB)
+0x0DF00000-0x0E000000 - Device tree (1 MB)
+0x0E000000-0x11000000 - Ramdisk (48 MB)
+0x11000000-0x17F00000 - Heap (111 MB)
+0x17F00000-0x17FFC000 - iBoot (unused) (1008 kB)
+0x17FFC000-0x18000000 - Panic (16kB)
+*/
+
+#if APPLICATION_IBOOT
+#define MMU_TT_SIZE		(0x1000ULL)
+#define MMU_TT_BASE		(TEXT_BASE + TEXT_FOOTPRINT - MMU_TT_SIZE)
+#define MMU_NONCACHE0_SIZE	(SRAM_BANK_LEN)
+#define MMU_NONCACHE0_PBASE	(SRAM_BASE)
+#define MMU_NONCACHE0_VBASE	(SRAM_BASE + SRAM_BANK_LEN)
+#define MMU_NONCACHE1_SIZE	(0x10000000ULL)
+#define MMU_NONCACHE1_PBASE	(0x08000000ULL)
+#define MMU_NONCACHE1_VBASE	(0x28000000ULL)
+
+#if WITH_DFU_MODE
+#define STACK_SIZE		(0x3000ULL)
+
+#define INSECURE_MEMORY_SIZE	(0x00800000ULL)
+#define INSECURE_MEMORY_BASE	(SDRAM_BASE + ((u_int32_t)platform_get_memory_size()) - INSECURE_MEMORY_SIZE)
+
+#else /* !WITH_DFU_MODE */
+#define STACK_SIZE		(0x0800ULL)
+
+#define INSECURE_MEMORY_BASE		(SDRAM_BASE)
+#define INSECURE_MEMORY_SIZE		(DEFAULT_KERNEL_ADDRESS - SDRAM_BASE)
+#define DEFAULT_LOAD_ADDRESS		(INSECURE_MEMORY_BASE)
+#define DEFAULT_LOAD_SIZE		(0x03000000ULL)
+#define DEFAULT_KERNEL_ADDRESS		(DEFAULT_LOAD_ADDRESS + DEFAULT_LOAD_SIZE)
+#define DEFAULT_KERNEL_SIZE		(0x02F00000ULL)
+#define DEFAULT_DEVICETREE_ADDRESS	(DEFAULT_KERNEL_ADDRESS + DEFAULT_KERNEL_SIZE)
+#define DEFAULT_DEVICETREE_SIZE		(0x00100000ULL)
+#define DEFAULT_RAMDISK_ADDRESS		(DEFAULT_DEVICETREE_ADDRESS + DEFAULT_DEVICETREE_SIZE)
+#define DEFAULT_RAMDISK_SIZE		(0x03000000ULL)
+#define DEFAULT_FREE_ADDRESS		(DEFAULT_RAMDISK_ADDRESS + DEFAULT_RAMDISK_SIZE)
+
+#define SECURE_MEMORY_BASE	(INSECURE_MEMORY_BASE + INSECURE_MEMORY_SIZE)
+#define SECURE_MEMORY_SIZE	(IBOOT_BASE - SECURE_MEMORY_BASE)
+
+#define HEAP_EXT_BASE		(DEFAULT_FREE_ADDRESS)
+#define HEAP_EXT_SIZE		(IBOOT_BASE - HEAP_EXT_BASE)
+#endif /* !WITH_DFU_MODE */
+
+#define STACK_BASE		(MMU_TT_BASE - STACK_SIZE)
+
+/* Reserved area for boot trace */
+/* WARNING: We're really tight on SRAM on B137. So, the boot trace area overlaps
+   the initial stack area. We typically only use about 500 bytes of the initial stack,
+   and once we jump into main_task, we never use the initial stack again. So, as long
+   as we don't do too much tracing before jumping into main_task, we'll be OK */
+#define PROFILE_BUF_SIZE	(0x0800ULL)
+#define PROFILE_BUF_BASE	(STACK_BASE)
+
+#define HEAP_END		(STACK_BASE)
+
+#endif /* APPLICATION_IBOOT */
+
+#endif /* ! __PLATFORM_MEMMAP_H */

platform/s5l8747x/include/platform/pinconfig.h

@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_PINCONFIG_H
+#define __PLATFORM_PINCONFIG_H
+
+/* Default S5L8747X SoC Pin Configuration */
+
+static const struct gpio_default_config gpio_default_config[GPIO_GROUP_COUNT] = {
+/* P0  */  PINCONFIG(
+		PCON_DISABLE,	NO_PUPDN,	// I2S0_MCK ->
+		PCON_DISABLE,	NO_PUPDN,	// I2S0_LRCK ->
+		PCON_DISABLE,	NO_PUPDN,	// I2S0_BCK ->
+		PCON_DISABLE,	NO_PUPDN,	// I2S0_DOUT ->
+		PCON_DISABLE,	NO_PUPDN,	// I2S0_DIN ->
+		PCON_DISABLE,	NO_PUPDN,	// UART0_RXD ->
+		PCON_DISABLE,	NO_PUPDN,	// UART0_TXD ->
+		PCON_DISABLE,	NO_PUPDN	// UART0_NRTS ->
+	       ),
+/* P1  */  PINCONFIG(
+		PCON_DISABLE,	NO_PUPDN,	// UART0_NCTS ->
+		PCON_DISABLE,	NO_PUPDN,	// I2C0_SCL ->
+		PCON_DISABLE,	NO_PUPDN,	// I2C0_SDA ->
+		PCON_DISABLE,	PUP,		// SPI0_CEN ->		SPI0_CS
+		PCON_DISABLE,	PDN,		// SPI0_CLK ->		SPI0_CLK
+		PCON_DISABLE,	NO_PUPDN,	// SPI0_MOSI ->		SPI0_MOSI
+		PCON_DISABLE,	NO_PUPDN,	// SPI0_MISO ->		SPI0_MISO
+		PCON_DISABLE,	NO_PUPDN	// - ->
+	       ),
+/* P2  */  PINCONFIG(
+		PCON_DISABLE,	NO_PUPDN,	// GPIO0 ->
+		PCON_DISABLE,	NO_PUPDN,	// GPIO1 ->		BOOT_CONFIG[0]
+		PCON_DISABLE,	NO_PUPDN,	// GPIO2 ->		BOOT_CONFIG[1]
+		PCON_DISABLE,	NO_PUPDN,	// GPIO3 ->		BOARD_ID[1]
+		PCON_DISABLE,	NO_PUPDN,	// GPIO4 ->		BOARD_ID[2]
+		PCON_DISABLE,	NO_PUPDN,	// GPIO5 ->		BOARD_ID[3]
+		PCON_DISABLE,	NO_PUPDN,	// GPIO6 ->		BOARD_ID[4]
+		PCON_DISABLE,	NO_PUPDN	// GPIO7 ->
+	       ),
+/* P3  */  PINCONFIG(
+		PCON_DISABLE,	NO_PUPDN,	// CLK0_OUT ->
+		PCON_DISABLE,	NO_PUPDN,	// CLK1_OUT ->
+		PCON_DISABLE,	NO_PUPDN,	// HDMI_HPD ->
+		PCON_DISABLE,	NO_PUPDN,	// HDMI_CEC ->
+		PCON_IN,	PDN,		// FORCE_DFU ->		FORCE_DFU
+		PCON_DISABLE,	PDN,		// DFU_STATUS ->	DFU_STATUS
+		PCON_DISABLE,	NO_PUPDN,	// I2C1_SCL ->
+		PCON_DISABLE,	NO_PUPDN	// I2C1_SDA ->
+	       ),
+/* P4  */  PINCONFIG(
+		PCON_DISABLE,	NO_PUPDN,	// UART2_RXD ->
+		PCON_DISABLE,	NO_PUPDN,	// UART2_TXD ->
+		PCON_DISABLE,	NO_PUPDN,	// UART2_NRTS ->
+		PCON_DISABLE,	NO_PUPDN,	// UART2_NCTS ->
+		PCON_DISABLE,	NO_PUPDN,	// SPI1_CEN ->
+		PCON_DISABLE,	NO_PUPDN,	// SPI1_CLK ->
+		PCON_DISABLE,	NO_PUPDN,	// SPI1_MOSI ->
+		PCON_DISABLE,	NO_PUPDN	// SPI1_MISO ->
+	       ),
+/* P5  */  PINCONFIG(
+		PCON_DISABLE,	NO_PUPDN,	// UART1_RXD ->
+		PCON_DISABLE,	NO_PUPDN,	// UART1_TXD ->
+		PCON_DISABLE,	NO_PUPDN,	// UART1_NRTS ->
+		PCON_DISABLE,	NO_PUPDN,	// UART1_NCTS ->
+		PCON_DISABLE,	NO_PUPDN,	// VGA_VDEN ->
+		PCON_DISABLE,	NO_PUPDN,	// VGA_HSYNC ->
+		PCON_DISABLE,	NO_PUPDN,	// VGA_VSYNC ->
+		PCON_DISABLE,	NO_PUPDN	// - ->
+	       ),
+};
+
+#endif /* ! __PLATFORM_PINCONFIG_H */

platform/s5l8747x/include/platform/soc/chipid.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_SOC_CHIPID_H
+#define __PLATFORM_SOC_CHIPID_H
+
+#include <platform/chipid.h>
+#include <platform/soc/hwregbase.h>
+
+#define	rEFUSE_READ_DONE		(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x00))
+#define	rCHIPIDL			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x04))
+#define	rCHIPIDH			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x08))
+#define	rDIEIDL				(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x0C))
+#define	rDIEIDH				(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x10))
+
+extern bool     chipid_get_ecid_image_personalization_required(void);
+
+#endif /* __PLATFORM_SOC_CHIPID_H */

platform/s5l8747x/include/platform/soc/clocks.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_CLOCKS_H
+#define __PLATFORM_SOC_CLOCKS_H
+
+#include <platform/soc/hwregbase.h>
+
+#define	rCLKCON0			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x00))
+#define	rCLKCON1			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x10))
+#define	rCLKCON2			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x20))
+#define	rCLKCON3			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x30))
+#define	rCLKCON4			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x40))
+#define	rCLKCON5			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x50))
+#define	rCLKCON6			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x60))
+#define	rCLKCON7			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x70))
+#define	rPLL0PMS			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x100))
+#define	rPLL1PMS			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x104))
+#define	rPLL2PMS			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x108))
+#define	rPLL3PMS			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x10C))
+#define	rPLL0LCNT			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x110))
+#define	rPLL1LCNT			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x114))
+#define	rPLL2LCNT			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x118))
+#define	rPLL3LCNT			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x11C))
+#define	rPLLLOCKINT			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x150))
+#define	rPLLLOCK			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x154))
+#define	rPLLCON				(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x158))
+#define	rCGCON0				(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x200))
+#define	rCGCON1				(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x204))
+#define	rCGCON2				(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x208))
+#define	rCGCON3				(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x20C))
+#define	rCGCON4				(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x210))
+#define	rSWRCON				(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x250))
+#define	rRSTSR				(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x254))
+#define	rKEEPMAP			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x300))
+#define	rVERSION			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0xA00))
+#define	rMONITOR01			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x400))
+#define	rMONITOR2			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x404))
+
+enum {
+	CLKGEN_CLK_OSC = 0,
+	CLKGEN_CLK_PLL0,
+	CLKGEN_CLK_PLL1,
+	CLKGEN_CLK_PLL2,
+	CLKGEN_CLK_PLL3,
+	CLKGEN_CLK_SCLK,
+	CLKGEN_CLK_FCLK,
+	CLKGEN_CLK_DCLK,
+	CLKGEN_CLK_ACLK,
+	CLKGEN_CLK_HCLK,
+	CLKGEN_CLK_PCLK,
+	CLKGEN_CLK_NCLK,
+	CLKGEN_CLK_USBPHY,
+	CLKGEN_CLK_VCLK0,
+	CLKGEN_CLK_VCLK1,
+	CLKGEN_CLK_COUNT
+};
+
+
+#endif /* ! __PLATFORM_SOC_CLOCKS_H */

platform/s5l8747x/include/platform/soc/hwclocks.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWCLOCKS_H
+#define __PLATFORM_SOC_HWCLOCKS_H
+
+#include <platform/clocks.h>
+
+#if SUPPORT_FPGA
+#define OSC_FREQ	(27000000UL)
+#else
+#define OSC_FREQ	(24000000UL)
+#endif
+
+#define CLK_FCLK	(HWCLOCK_BASE+0)
+#define CLK_ACLK	(HWCLOCK_BASE+1)
+#define CLK_HCLK	(HWCLOCK_BASE+2)
+#define CLK_PCLK	(HWCLOCK_BASE+3)
+#define CLK_VCLK0	(HWCLOCK_BASE+4)
+#define CLK_VCLK1	(HWCLOCK_BASE+5)
+#define CLK_MCLK	(HWCLOCK_BASE+6)
+#define CLK_NCLK	(HWCLOCK_BASE+7)
+#define CLK_USBPHYCLK	(HWCLOCK_BASE+8)
+#define CLK_DCLK	(HWCLOCK_BASE+9)
+
+/* S5L8747X clock gate devices */
+enum {
+	CLK_AES,
+	CLK_CHIPID,
+	CLK_DMAC0,
+	CLK_DMAC1,
+	CLK_GPIO,
+	CLK_IIC0,
+	CLK_IIC1,
+	CLK_IIC2,
+	CLK_PKE,
+	CLK_SHA1,
+	CLK_SPI0,
+	CLK_SPI1,
+	CLK_TIMER,
+	CLK_UART0,
+	CLK_UART1,
+	CLK_UART2,
+	CLK_USBOTG0,
+	CLK_USBOTG1,
+	CLK_USBPHY,
+	CLK_ROSC,
+};
+
+// USB PHY driver expects CLK_USBOTG, so give them what they want
+#define CLK_USBOTG	CLK_USBOTG1
+
+#endif /* ! __PLATFORM_SOC_HWCLOCKS_H */

platform/s5l8747x/include/platform/soc/hwisr.h

@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWISR_H
+#define __PLATFORM_SOC_HWISR_H
+
+#define EINT_G6			0	// External Interrupt 6
+#define EINT_G5			1	// External Interrupt 5		
+#define EINT_G4			2	// External Interrupt 4 	
+#define EINT_G3			3	// External Interrupt 3	 	
+#define INT_SWI			4	// SW Interrupt
+#define INT_CMMSTX		5	// COMMS TX Interrupt	
+#define INT_CMMSRX		6	// COMMS RX Interrupt
+#define INT_TIMERFIQ		7	// TIMER FIQ Interrupt
+#define INT_TIMERIRQ		8	// TIMER IRQ Interrupt 
+#define INT_SPI0		9	// SPI0 Interrupt
+#define INT_SPI1		10	// SPI1 Interrupt
+#define INT_RESERVED11		11	// Reserved
+#define INT_VP			12	// VP Interrupt
+#define INT_RGBOUT		13	// RGBOUT Interrupt
+#define INT_RESERVED14		14	// Reserved
+#define INT_RESERVED15		15	// Reserved
+#define INT_DMA0		16	// DMA0 Interrupt 
+#define INT_DMA1		17	// DMA1 Interrupt
+#define INT_USB_OTG0		18	// USB OTG0 Interrupt
+#define INT_USB_OTG1		19	// USB OTG1 Interrupt
+#define INT_RESERVED20		20	// Reserved
+#define INT_IIC0		21	// IIC0 Interrupt
+#define INT_IIC1		22	// IIC1 Interrupt
+#define INT_IIC2		23	// IIC2 Interrupt
+#define INT_UART0 		24	// UART0 Interrupt
+#define INT_UART1 		25	// UART1 Interrupt
+#define INT_UART2		26	// UART2 Interrupt
+#define INT_RESERVED27		27	// Reserved
+#define INT_RESERVED28		28	// Reserved
+#define INT_RESERVED29		29	// Reserved
+#define INT_TVOUT		30	// TVOUT Interrupt
+#define EINT_G2			31	// External Interrupt 2
+#define EINT_G1			32	// External Interrupt 1
+#define EINT_G0			33	// External Interrupt 0		
+#define INT_RESERED34		34	// Reserved
+#define INT_MFC_DEC		35	// MFC DEC Interrupt	 	
+#define INT_PKE			36	// PKE Interrupt
+#define INT_SCALER		37	// SCALER Interrupt
+#define INT_MIXER		38	// MIXER Interrupt	
+#define INT_AES			39	// AES Interrupt
+#define INT_SHA1		40	// SHA1 Interrupt 
+#define INT_PRNG		41	// PRNG Interrupt
+#define INT_SHA2		42	// SHA2 Interrupt
+#define INT_RESERVED43		43	// Reserved
+#define INT_ADC			44	// ADC Interrupt
+#define INT_RESERVED45		45	// Reserved
+#define INT_I2S0		46	// I2S Interrupt
+#define INT_RESERVED47		47	// Reserved
+#define INT_RESERVED48		48	// Reserved 
+#define INT_RESERVED49		49	// Reserved
+#define INT_SUSPEND		50	// SUSPEND Interrupt
+#define INT_WDT			51	// WDT Interrupt
+#define INT_SPDIF		52	// SPDIF Interrupt
+#define INT_RESERVED53		53	// Reserved
+#define INT_RESERVED54		54	// Reserved
+#define INT_RESERVED55		55	// Reserved
+#define INT_RESERVED56 		56	// Reserved
+#define INT_RESERVED57 		57	// Reserved
+#define INT_RESERVED58		58	// Reserved
+#define INT_HDMI_CEC		59	// HDMI CEC Interrupt
+#define INT_HDMI		60	// HDMI Interrupt
+#define INT_CLKRSTGEN		61	// CLKRSTGEN Interrupt
+#define INT_PMU			62	// PMU Interrupt
+#define INT_ARF			63	// ARF Interrupt
+
+#endif /* ! __PLATFORM_SOC_HWISR_H */

platform/s5l8747x/include/platform/soc/hwregbase.h

@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2011 - 2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_SOC_HWREGBASE_H
+#define __PLATFORM_SOC_HWREGBASE_H
+
+#ifndef HWREG_REMAP
+# define HWREG_REMAP(_x)	_x
+#endif
+
+#define AIC_VERSION 			0
+#define AIC_INT_COUNT			(192)
+#define PMGR_WDG_VERSION		0
+
+/* S5L8747X Reg Base Defs */
+
+#define SHA1_BASE_ADDR			HWREG_REMAP(0x38000000)
+
+#define AHB_BASE_ADDR			HWREG_REMAP(0x38100000)
+
+#define DMAC0_BASE_ADDR			HWREG_REMAP(0x38200000)
+#define DMAC1_BASE_ADDR			HWREG_REMAP(0x38700000)
+
+#define SHA2_BASE_ADDR			HWREG_REMAP(0x38300000)
+
+#define USBOTG0_BASE_ADDR		HWREG_REMAP(0x38400000)
+#define USB_OHCI_BASE_ADDR		HWREG_REMAP(0x38500000)
+#define USB_EHCI_BASE_ADDR		HWREG_REMAP(0x39800000)
+#define USBOTG1_BASE_ADDR		HWREG_REMAP(0x39900000)
+#define USBOTG_BASE_ADDR                (USBOTG1_BASE_ADDR)
+#define USBPHY_BASE_ADDR		HWREG_REMAP(0x3C400000)
+#define USBPHY_VERSION			(1)
+
+#define RGBOUT_BASE_ADDR		HWREG_REMAP(0x38900000)
+
+#define AES_BASE_ADDR			HWREG_REMAP(0x38C00000)
+#define AES_VERSION			(1)
+
+#define VIC_BASE_ADDR			HWREG_REMAP(0x38E00000)
+#define VIC_STRIDE			(0x00001000)
+#define VICS_COUNT			(2)
+
+#define EDGEIC_BASE_ADDR		HWREG_REMAP(0x38E02000)
+
+#define SDO_BASE_ADDR			HWREG_REMAP(0x39300000)
+
+#define AAM_BASE_ADDR			HWREG_REMAP(0x39700000)
+#define EINT_NUM_GROUPS			(7)
+#define EINTS_PER_GROUP			(32)
+
+#define SPI0_BASE_ADDR			HWREG_REMAP(0x3C300000)
+#define SPI1_BASE_ADDR			HWREG_REMAP(0x3CE00000)
+#define SPI_VERSION			(1)
+#define SPIS_COUNT			(2)
+
+#define CLKCON_BASE_ADDR		HWREG_REMAP(0x3C500000)
+
+#define IIC0_BASE_ADDR			HWREG_REMAP(0x3C600000)
+#define IIC1_BASE_ADDR			HWREG_REMAP(0x3E500000)
+#define IIC2_BASE_ADDR			HWREG_REMAP(0x3E400000)
+#define IICS_COUNT			(3)
+
+#define TIMER_BASE_ADDR			HWREG_REMAP(0x3C700000)
+#define TIMER_VERSION			(1)
+
+#define WDT_BASE_ADDR			HWREG_REMAP(0x3C800000)
+
+#define UART0_BASE_ADDR			HWREG_REMAP(0x3CC00000)
+#define UART1_BASE_ADDR			HWREG_REMAP(0x3DB00000)
+#define UART2_BASE_ADDR			HWREG_REMAP(0x3DC00000)
+#define UART_VERSION			(1)
+#define UARTS_COUNT			(3)
+
+#define GPIO_BASE_ADDR			HWREG_REMAP(0x3CF00000)
+#define GPIO_FSEL_OFFSET		(0x200)
+// There are 9 groups listed in the user manual, but the last 3
+// aren't actually implemented.
+#define GPIO_GROUP_COUNT		(6) 
+#define GPIO_PAD_SPI			(GPIO_GROUP_COUNT)
+
+#define PKE_BASE_ADDR			HWREG_REMAP(0x3D000000)
+#define PKE_SW_RESET_AVAILABLE		(1)
+
+#define CHIPID_BASE_ADDR		HWREG_REMAP(0x3D100000)
+
+#define AXI_SPINE_BASE_ADDR		HWREG_REMAP(0x3D500000)
+#define DREX_BASE_ADDR	  		HWREG_REMAP(0x3D700000)
+
+#define BUS_BASE_ADDR			HWREG_REMAP(0x3E000000)
+
+#define SRAM_MIU_BASE_ADDR		HWREG_REMAP(0x3E100000)
+
+#define HDMI_LINK_BASE_ADDR		HWREG_REMAP(0x3E200000)
+#define DITHER_VERSION			(1)
+
+#define HDMI_CEC_BASE_ADDR		HWREG_REMAP(0x3E300000)
+
+#endif /* ! __PLATFORM_SOC_HWREGBASE_H */

platform/s5l8747x/include/platform/soc/miu.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2007 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_SOC_MIU_H
+#define __PLATFORM_SOC_MIU_H
+
+#include <platform/soc/hwregbase.h>
+
+#define rAHB_MST0			(*(volatile u_int32_t *)(AHB_BASE_ADDR + 0x004))
+#define rAHB2AXIID_CON			(*(volatile u_int32_t *)(AHB_BASE_ADDR + 0x040))
+#define rAHB2AXIID0			(*(volatile u_int32_t *)(AHB_BASE_ADDR + 0x044))
+#define rAHB2AXIID1			(*(volatile u_int32_t *)(AHB_BASE_ADDR + 0x048))
+#define rAHB2AXIID2			(*(volatile u_int32_t *)(AHB_BASE_ADDR + 0x04C))
+#define rAHB2AXIID3			(*(volatile u_int32_t *)(AHB_BASE_ADDR + 0x050))
+#define rAHB2AXIID4			(*(volatile u_int32_t *)(AHB_BASE_ADDR + 0x054))
+#define rLEVEL1SEL			(*(volatile u_int32_t *)(AHB_BASE_ADDR + 0x090))
+
+#define rPWRDWN_BUS			(*(volatile u_int32_t *)(BUS_BASE_ADDR + 0x008))
+#define rREMAP				(*(volatile u_int32_t *)(BUS_BASE_ADDR + 0x00C))
+#define rDDR1				(*(volatile u_int32_t *)(BUS_BASE_ADDR + 0x010))
+#define rMFC_ARF_CON			(*(volatile u_int32_t *)(BUS_BASE_ADDR + 0x3000))
+#define rMFC_ARF_BASE_ADDR		(*(volatile u_int32_t *)(BUS_BASE_ADDR + 0x3004))
+#define rMFC_ARF_ADDR_MASK		(*(volatile u_int32_t *)(BUS_BASE_ADDR + 0x3008))
+
+enum remap_select {
+  REMAP_SRAM = 0,
+  REMAP_SDRAM
+};
+
+extern void miu_select_remap(enum remap_select sel);
+
+#endif /* ! __PLATFORM_SOC_MIU_H */

platform/s5l8747x/include/platform/soc/power.h

@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2007 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_SOC_POWER_H
+#define __PLATFORM_SOC_POWER_H
+
+#include <platform/soc/hwregbase.h>
+
+#define rPWRCONF			(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x000))
+#define rPWRCMD				(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x004))
+#define rOSCCNT				(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x038))
+#define rPLLCNT				(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x03C))
+#define rSTATESAVE0			(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x044))
+#define rSTATESAVE1			(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x048))
+#define rSTATESAVE2			(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x04C))
+#define rSTATESAVE3			(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x050))
+#define rTMCMD				(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x06C))
+#define rTMDATA				(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x070))
+#define rTMPRE				(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x074))
+#define rTMCNT				(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x078))
+#define rTMALARM			(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x07C))
+#define rSECCONF			(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x104))
+#define rVERSION			(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x108))
+
+#endif /* ! __PLATFORM_SOC_POWER_H */

platform/s5l8747x/include/platform/soc/sdo.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2008 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_SOC_SDO_H
+#define __PLATFORM_SOC_SDO_H
+
+#include <platform/soc/hwregbase.h>
+
+#define	rDAC0_SCALE			(*(volatile u_int32_t *)(SDO_BASE_ADDR + 0x1C))
+#define	rDAC1_SCALE			(*(volatile u_int32_t *)(SDO_BASE_ADDR + 0x20))
+#define	rDAC2_SCALE			(*(volatile u_int32_t *)(SDO_BASE_ADDR + 0x24))
+
+extern int sdo_init(void);
+
+#endif /* ! __PLATFORM_SOC_SDO_H */

platform/s5l8747x/include/platform/trampoline.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_TRAMPOLINE_H
+#define __PLATFORM_TRAMPOLINE_H
+
+#include <platform/memmap.h>
+#include <platform/soc/hwregbase.h>
+
+#define SECURITY_REG		(AAM_BASE_ADDR + 0x104)
+#define ROM_READ_DISABLE	(1 << 2)
+
+#endif /* ! __PLATFORM_TRAMPOLINE_H */

platform/s5l8747x/include/platform/usbconfig.h

@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2007-2009 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_USBCONFIG_H
+#define __PLATFORM_USBCONFIG_H
+
+#define USBPHY_CLK_TYPE		(2) /* Use CLKCORE */
+
+#define USBPHY_UOTGTUNE1	(0x347)
+#define USBPHY_UOTGTUNE2	(0xE3F)
+
+#define USBOTG_AHB_DMA_BURST	(DWCUSB_GAHBCFG_HBST_SINGLE)
+
+#endif /* ! __PLATFORM_USBCONFIG_H */

platform/s5l8747x/init.c

@@ -0,0 +1,855 @@
+/*
+ * Copyright (C) 2007-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <debug.h>
+#include <arch.h>
+#include <arch/arm/arm.h>
+#include <drivers/aes.h>
+#include <drivers/flash_nor.h>
+#include <drivers/iic.h>
+#include <drivers/power.h>
+#include <drivers/spi.h>
+#include <drivers/uart.h>
+#include <drivers/usb/usb_public.h>
+#include <drivers/usbphy.h>
+#include <lib/devicetree.h>
+#include <lib/env.h>
+#include <lib/random.h>
+#include <platform.h>
+#include <platform/clocks.h>
+#include <platform/gpio.h>
+#include <platform/gpiodef.h>
+#include <platform/int.h>
+#include <platform/miu.h>
+#include <platform/memmap.h>
+#include <platform/power.h>
+#include <platform/timer.h>
+#include <platform/trampoline.h>
+#include <platform/soc/chipid.h>
+#include <platform/soc/hwclocks.h>
+#include <platform/soc/miu.h>
+#include <platform/soc/power.h>
+#include <sys.h>
+#include <sys/boot.h>
+#include <target.h>
+
+static void platform_init_boot_strap(void);
+
+static uint8_t boot_debug;
+
+
+int platform_early_init(void)
+{
+#if PRODUCT_LLB || PRODUCT_IBSS
+	/* Verify that SecureROM has been disabled */
+	if (((*(volatile u_int32_t *)SECURITY_REG) & ROM_READ_DISABLE) == 0) {
+		panic("SecureROM is enabled");
+	}
+#endif
+
+#if WITH_HW_PLATFORM_POWER
+	/* initialize the s5l8747x power control driver */
+	platform_power_init();
+#endif
+
+#if WITH_HW_MIU
+	miu_init();
+#endif
+#if WITH_HW_CLOCKS
+	/* initialize the clock driver */
+	clocks_init();
+#endif
+#if WITH_HW_VIC
+	/* initialize the vic, mask all interrupts */
+	interrupt_init();
+#endif
+#if WITH_HW_TIMER
+	timer_init(0);
+#endif
+#if WITH_HW_USBPHY
+	usbphy_power_down();
+#endif
+#if WITH_HW_UART
+	/* do whatever uart initialization we need to get a simple console */
+	uart_init();
+#endif
+#if WITH_IIC
+	iic_init();
+#endif
+#if !PRODUCT_IBOOT && !PRODUCT_IBEC
+	platform_init_power();
+	
+#if WITH_BOOT_STAGE
+	boot_check_stage();
+#endif
+#endif
+
+#if WITH_BOOT_STAGE
+	boot_set_stage(kPowerNVRAMiBootStageProductStart);
+#endif
+
+#if WITH_HW_POWER
+	power_get_nvram(kPowerNVRAMiBootDebugKey, &boot_debug);
+	debug_enable_uarts(boot_debug);
+#endif
+
+#if WITH_HW_DMA
+        /* initialize the dma engine */
+        dma_init();
+#endif
+
+#if WITH_TARGET_CONFIG
+	target_early_init();
+#endif
+	
+	return 0;
+}
+
+int platform_late_init(void)
+{
+	// Chips older then B0 are not supported
+	if (platform_get_chip_revision() < 0x10) platform_not_supported();
+
+#if WITH_ENV
+	/* publish secure-boot flag for restore mode */
+	env_set_uint("secure-boot", 1, 0);
+#endif
+
+#if WITH_HW_USB && WITH_USB_MODE_RECOVERY
+	usb_early_init();
+#endif
+
+#if WITH_HW_POWER
+	power_late_init();
+#endif
+
+#if WITH_TARGET_CONFIG
+	target_late_init();
+#endif
+
+	return 0;
+}
+
+int platform_init_setup_clocks(void)
+{
+#if WITH_HW_CLOCKS
+	clocks_set_default();
+#endif
+
+	return 0;
+}
+
+int platform_init_hwpins(void)
+{
+	// need board id to select the right pinconfig
+	platform_init_boot_strap();
+
+#if WITH_HW_GPIO
+	/* finish initializing the gpio driver */
+	gpio_init_pinconfig();
+#endif
+
+	return 0;
+}
+
+int platform_init_internal_mem(void)
+{
+#if WITH_HW_MIU
+	/* initialize sram bus */
+	miu_initialize_internal_ram();
+#endif
+
+	return 0;
+}
+
+int platform_init_mainmem(bool resume)
+{
+#if WITH_HW_MIU && APPLICATION_IBOOT
+	/* initialize sdram */
+	miu_initialize_dram(resume);
+#endif
+
+	return 0;
+}
+
+int platform_init_power(void)
+{
+#if WITH_HW_POWER
+	power_init();
+#endif
+
+	return 0;
+}
+
+int platform_quiesce_hardware(enum boot_target target)
+{
+	bool quiesce_clocks = false;
+
+#if APPLICATION_SECUREROM
+	quiesce_clocks = true;
+#endif
+
+#if WITH_TARGET_CONFIG
+	target_quiesce_hardware();
+#endif
+
+#if WITH_HW_USB
+	usb_quiesce();
+#endif
+
+	switch (target) {
+		case BOOT_HALT:
+		case BOOT_DARWIN_RESTORE:
+			break;
+		case BOOT_IBOOT:
+		case BOOT_DARWIN:
+#if WITH_BOOT_STAGE
+			boot_set_stage(kPowerNVRAMiBootStageProductEnd);
+#endif
+			break;
+		case BOOT_DIAGS:
+		case BOOT_SECUREROM:
+			quiesce_clocks = true;
+			// fall through to default
+		default:
+#if WITH_BOOT_STAGE
+			boot_set_stage(kPowerNVRAMiBootStageOff);
+#endif
+			break;
+	}
+
+#if WITH_HW_DMA
+#error "Need to quiesce DMA here if a DMA API is ever added"
+#endif
+#if WITH_HW_TIMER
+	timer_stop_all();
+#endif
+#if WITH_HW_VIC
+	interrupt_mask_all();
+#endif
+
+	if (quiesce_clocks) {
+#if WITH_HW_CLOCKS
+		clocks_quiesce();
+#endif
+	}
+
+	return 0;
+}
+
+int platform_bootprep(enum boot_target target)
+{
+	u_int32_t gids = ~0, uids = ~0;	/* leave crypto keys alone by default */
+
+	/* prepare hardware for booting into various targets */
+
+#if WITH_HW_CLOCKS
+	if (target != BOOT_IBOOT) clocks_set_performance(kPerformanceHigh);
+#endif
+
+#if WITH_TARGET_CONFIG
+	target_bootprep(target);
+#endif
+
+	/* If we're not restoring, reset the watchdog-on-wake until enabled */
+	if ((boot_debug & kPowerNVRAMiBootDebugWDTWake) && (target == BOOT_DARWIN))
+	{
+		boot_debug &= ~kPowerNVRAMiBootDebugWDTWake;
+#if WITH_HW_POWER
+		power_set_nvram(kPowerNVRAMiBootDebugKey, boot_debug);
+#endif
+	}
+
+	switch (target) {
+#if APPLICATION_IBOOT
+		case BOOT_DARWIN_RESTORE:
+			platform_quiesce_display();
+		case BOOT_DARWIN:
+			if (boot_debug & kPowerNVRAMiBootDebugWDTWake)
+			    wdt_enable();
+			/* even when trusted, Darwin only gets the UID / GID1 */
+			uids = 1;
+			gids = 2;
+#if WITH_HW_MIU
+			miu_select_remap(REMAP_SDRAM);
+#endif
+			break;
+
+		case BOOT_DIAGS:
+			platform_quiesce_display();
+#if WITH_BOOT_STAGE
+			boot_clear_error_count();
+#endif
+			break;
+
+		case BOOT_IBOOT:
+#endif
+
+		case BOOT_SECUREROM:
+			platform_quiesce_display();
+#if WITH_HW_MIU
+			miu_select_remap(REMAP_SDRAM);
+#endif
+			break;
+			
+		case BOOT_UNKNOWN:
+			platform_quiesce_display();
+			break;
+
+		default:
+			; // do nothing
+	}
+
+	/* Let security override keys */
+	if (!security_allow_modes(kSecurityModeGIDKeyAccess))
+		gids = 0;
+	if (!security_allow_modes(kSecurityModeUIDKeyAccess))
+		uids = 0;
+
+	/* disable all keys not requested */
+	platform_disable_keys(~gids, ~uids);
+
+	return 0;
+}
+
+void platform_mmu_setup(bool resume)
+{
+	RELEASE_ASSERT(false == resume);
+
+	/* mark usable ram as cached/buffered */
+	arm_mmu_map_section_range(SRAM_BASE, SRAM_BASE, ROUNDUP(SRAM_BANK_LEN, MB)/MB, kARMMMUNormal, false, false);
+#if APPLICATION_IBOOT
+	arm_mmu_map_section_range(SDRAM_BASE, SDRAM_BASE, ROUNDUP(SDRAM_BANK_LEN * SDRAM_BANK_COUNT, MB)/MB, kARMMMUNormal, false, false);
+#endif
+#if APPLICATION_SECUREROM
+	arm_mmu_map_section_range(VROM_BASE, VROM_BASE, ROUNDUP(VROM_BANK_LEN, MB)/MB, kARMMMUNormal, false, false);
+#endif
+
+	/* Remap text base is to zero (for exception vectors) */
+	arm_mmu_map_section(0, TEXT_BASE, kARMMMUNormalRX, false);
+
+#ifdef MMU_NONCACHE0_SIZE
+	/* create the noncached0 mapping */
+	arm_mmu_map_section_range(MMU_NONCACHE0_VBASE, MMU_NONCACHE0_PBASE, ROUNDUP(MMU_NONCACHE0_SIZE, MB)/MB, kARMMMUStronglyOrdered, false, false);
+#endif
+
+#ifdef MMU_NONCACHE1_SIZE
+	/* create the noncached1 mapping */
+	arm_mmu_map_section_range(MMU_NONCACHE1_VBASE, MMU_NONCACHE1_PBASE, ROUNDUP(MMU_NONCACHE1_SIZE, MB)/MB, kARMMMUStronglyOrdered, false, false);
+#endif
+}
+
+int platform_init(void)
+{
+#if WITH_HW_SPI
+	spi_init();
+#endif
+
+#if APPLICATION_IBOOT
+	target_init();
+#endif
+
+	return 0;
+}
+
+int platform_debug_init(void)
+{
+#if WITH_HW_USB
+	u_int32_t usb_enabled = 1;
+#if WITH_ENV && SUPPORT_FPGA
+	usb_enabled = env_get_uint("usb-enabled", 1);
+#endif
+	if (usb_enabled) usb_init();
+#endif
+
+#if WITH_TARGET_CONFIG
+	target_debug_init();
+#endif
+
+	return 0;
+}
+
+void platform_poweroff(void)
+{
+	platform_quiesce_display();
+
+#if WITH_TARGET_CONFIG
+	target_poweroff();
+#endif
+
+#if WITH_HW_POWER
+	boot_set_stage(kPowerNVRAMiBootStageOff);
+
+	power_shutdown();
+#endif
+	for(;;);
+}
+
+u_int32_t platform_set_performance(u_int32_t performance_level)
+{
+	u_int32_t old_performance_level = kPerformanceHigh;
+
+#if WITH_HW_CLOCKS
+	old_performance_level = clocks_set_performance(performance_level);
+#endif
+
+	return old_performance_level;
+}
+
+#if WITH_DEVICETREE
+
+int platform_update_device_tree(void)
+{
+	DTNode *node;
+	u_int32_t propSize;
+	char *propName;
+	void *propData;
+	
+	// Find the cpu0 node.
+	if (FindNode(0, "cpus/cpu0", &node)) {
+		
+		// Fill in the cpu frequency
+		propName = "clock-frequency";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			 *(uint32_t *)propData = clock_get_frequency(CLK_CPU);
+		}
+		
+		// Fill in the memory frequency
+		propName = "memory-frequency";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			*(uint32_t *)propData = clock_get_frequency(CLK_MEM);
+		}
+		
+		// Fill in the bus frequency
+		propName = "bus-frequency";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			*(uint32_t *)propData = clock_get_frequency(CLK_BUS);
+		}
+		
+		// Fill in the peripheral frequency
+		propName = "peripheral-frequency";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			*(uint32_t *)propData = clock_get_frequency(CLK_PERIPH);
+		}
+		
+		// Fill in the fixed frequency
+		propName = "fixed-frequency";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			*(uint32_t *)propData = clock_get_frequency(CLK_FIXED);
+		}
+		
+		// Fill in the time base frequency
+		propName = "timebase-frequency";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			*(uint32_t *)propData = clock_get_frequency(CLK_TIMEBASE);
+		}
+	}
+
+	// Find the arm-io node
+	if (FindNode(0, "arm-io", &node)) {
+
+		// Fill in the usb-phy frequency
+		propName = "usbphy-frequency";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			 *(uint32_t *)propData = clock_get_frequency(CLK_USBPHYCLK);
+		}
+	}
+
+#if WITH_HW_PLATFORM_CHIPID
+	// Find the arm-io node
+	if (FindNode(0, "arm-io", &node)) {
+		// Fill in the chip-revision property
+		propName = "chip-revision";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			*(uint32_t *)propData = platform_get_chip_revision();
+		}
+	}
+#endif
+
+#if WITH_HW_USBPHY
+	// Fill in the otgphyctrl0 node
+	if (FindNode(0, "arm-io/otgphyctrl0", &node)) {
+		 usbphy_update_device_tree(node);
+	}
+	// Fill in the otgphyctrl1 node
+	if (FindNode(0, "arm-io/otgphyctrl1", &node)) {
+		 usbphy_update_device_tree(node);
+	}
+#endif
+
+	// Carve mfcram out of base of vram. mfcram node should already have size populated
+	if (FindNode(0, "mfcram", &node)) {
+		uint32_t *mfcramPropData;
+		propName = "reg";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			mfcramPropData = propData;
+			if (FindNode(0, "vram", &node)) {
+				propName = "reg";
+				if (FindProperty(node, &propName, &propData, &propSize)) {
+					uint32_t *vramPropData = propData;
+					mfcramPropData[0] = vramPropData[0];
+					vramPropData[0] += mfcramPropData[1];
+					vramPropData[1] -= mfcramPropData[1];
+				}
+			}
+		}
+	}
+
+	return target_update_device_tree();
+}
+
+#endif
+
+static void platform_init_boot_strap(void)
+{
+	u_int32_t boot_strap, chip_board_id, gpio_board_id, boot_config;
+
+	// If rSTATESAVE0[0] set then boot strap already valid
+	if ((rSTATESAVE0 & 1) != 0) return;
+
+	gpio_configure_pupdn(GPIO_BOARD_ID0, GPIO_PDN);
+	gpio_configure_pupdn(GPIO_BOARD_ID1, GPIO_PDN);
+	gpio_configure_pupdn(GPIO_BOARD_ID2, GPIO_PDN);
+	gpio_configure_pupdn(GPIO_BOARD_ID3, GPIO_PDN);
+
+	gpio_configure_pupdn(GPIO_BOOT_CONFIG0, GPIO_PDN);
+	gpio_configure_pupdn(GPIO_BOOT_CONFIG1, GPIO_PDN);
+
+	gpio_configure(GPIO_BOARD_ID0, GPIO_CFG_IN);
+	gpio_configure(GPIO_BOARD_ID1, GPIO_CFG_IN);
+	gpio_configure(GPIO_BOARD_ID2, GPIO_CFG_IN);
+	gpio_configure(GPIO_BOARD_ID3, GPIO_CFG_IN);
+
+	gpio_configure(GPIO_BOOT_CONFIG0, GPIO_CFG_IN);
+	gpio_configure(GPIO_BOOT_CONFIG1, GPIO_CFG_IN);
+
+#if !SUPPORT_FPGA
+	platform_power_spin(100); // Wait 100us
+#endif
+
+	chip_board_id = chipid_get_board_id();
+
+	gpio_board_id =
+		(gpio_read(GPIO_BOARD_ID3) << 3) |
+		(gpio_read(GPIO_BOARD_ID2) << 2) |
+		(gpio_read(GPIO_BOARD_ID1) << 1) |
+		(gpio_read(GPIO_BOARD_ID0) << 0);
+
+	boot_config =
+		(gpio_read(GPIO_BOOT_CONFIG1) << 1) |
+		(gpio_read(GPIO_BOOT_CONFIG0) << 0);
+
+	gpio_configure(GPIO_BOARD_ID0, GPIO_CFG_DFLT);
+	gpio_configure(GPIO_BOARD_ID1, GPIO_CFG_DFLT);
+	gpio_configure(GPIO_BOARD_ID2, GPIO_CFG_DFLT);
+	gpio_configure(GPIO_BOARD_ID3, GPIO_CFG_DFLT);
+
+	gpio_configure(GPIO_BOOT_CONFIG0, GPIO_CFG_DFLT);
+	gpio_configure(GPIO_BOOT_CONFIG1, GPIO_CFG_DFLT);
+
+	boot_strap = (((chip_board_id << 4) | gpio_board_id) << 16) |
+		     (boot_config << 8) |
+		     (0x01 << 0);
+
+	rSTATESAVE0 = (rSTATESAVE0 & 0xFF000000) | (boot_strap & 0x00FFFFFF);
+}
+
+u_int32_t platform_get_board_id(void)
+{
+	u_int32_t board_id;
+
+	ASSERT((rSTATESAVE0 & kPlatformScratchFlagBootStrap) != 0);
+
+	board_id = (rSTATESAVE0 >> 16) & 0xFF;
+
+#if SUPPORT_FPGA
+	board_id = 0x3F;
+#endif
+
+	return board_id;
+}
+
+u_int32_t platform_get_boot_config(void)
+{
+	u_int32_t boot_config;
+
+	boot_config = (rSTATESAVE0 >> 8) & 0xFF;
+
+	return boot_config;
+}
+
+bool platform_get_boot_device(int32_t index, enum boot_device *boot_device, u_int32_t *boot_flag, u_int32_t *boot_arg)
+{
+	u_int32_t boot_config = platform_get_boot_config();
+
+	/* S5L8747X supports one boot device then USB-DFU per boot config.
+	   Unlike other platforms, the USB-DFU device is selectable. */
+
+#ifdef HACK_BOOT_CONFIG_OVERRIDE
+	boot_config = HACK_BOOT_CONFIG_OVERRIDE;
+#endif
+	
+	/* If the index is not zero force DFU mode */
+	if (index != 0) index = 1;
+
+	switch (boot_config) {
+		case 0: /* SPI 0, then USB0 FDU */
+		case 1: /* SPI 0, then USB1 DFU */
+			if (index == 0) {
+				*boot_device = BOOT_DEVICE_SPI;
+				*boot_flag = 0;
+				*boot_arg = 0;
+			} else {
+				*boot_device = BOOT_DEVICE_USBDFU;
+				*boot_flag = 0;
+				*boot_arg = 0;
+			}
+			return true;
+
+		case 2: /* SPI 0, then USB0 FDU with TEST_MODE */
+		case 3: /* SPI 0, then USB1 DFU with TEST_MODE */
+			if (index == 0) {
+				*boot_device = BOOT_DEVICE_SPI;
+				*boot_flag = BOOT_FLAG_TEST_MODE;
+				*boot_arg = 0;
+			} else {
+				*boot_device = BOOT_DEVICE_USBDFU;
+				*boot_flag = BOOT_FLAG_TEST_MODE;
+				*boot_arg = 0;
+			}
+			return true;
+
+		default:
+			return false;
+	}
+}
+
+/*
+ *  boot_interface_pin tables
+ *    tables are executed in order for disable and reverse order for enable
+ *
+ */
+
+struct boot_interface_pin {
+	gpio_t	  pin;
+	u_int32_t enable;
+	u_int32_t disable;
+};
+
+#if WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI
+#ifdef SPI_NOR0
+static const struct boot_interface_pin spi0_boot_interface_pins[] =
+{
+#if SUPPORT_FPGA
+	{ GPIO( 1, 3), GPIO_CFG_FUNC1, GPIO_CFG_DFLT },	// SPI0_CEN
+#else
+	{ GPIO( 1, 3), GPIO_CFG_OUT_1, GPIO_CFG_DFLT },	// SPI0_CEN
+#endif
+	{ GPIO( 1, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// SPI0_CLK
+	{ GPIO( 1, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// SPI0_MOSI
+	{ GPIO( 1, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT }	// SPI0_MISO
+};
+#endif
+#endif /* WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI */
+
+void platform_enable_boot_interface(bool enable, enum boot_device boot_device, u_int32_t boot_arg)
+{
+	const struct boot_interface_pin *pins = 0;
+	u_int32_t cnt, func, pin_count = 0;
+	gpio_t pin;
+
+	switch (boot_device) {
+#if WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI
+		case BOOT_DEVICE_SPI :
+#ifdef SPI_NOR0
+			if (boot_arg == 0) {
+				pins = spi0_boot_interface_pins;
+				pin_count = (sizeof(spi0_boot_interface_pins) / sizeof(spi0_boot_interface_pins[0]));
+			}
+#endif
+			break;
+#endif /* WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI */
+
+#if WITH_USB_DFU
+		case BOOT_DEVICE_USBDFU :
+			/* USB is always configured */
+			break;
+#endif /* WITH_USB_DFU */
+
+		default :
+			break;
+	}
+
+	for (cnt = 0; cnt < pin_count; cnt++) {
+		if (enable) {
+			pin = pins[pin_count - 1 - cnt].pin;
+			func = pins[pin_count - 1 - cnt].enable;
+		} else {
+			pin = pins[cnt].pin;
+			func = pins[cnt].disable;
+		}
+
+		dprintf(DEBUG_INFO, "platform_enable_boot_interface: %x, %x\n", pin, func);
+		gpio_configure(pin, func);
+	}
+}
+
+u_int64_t platform_get_nonce(void)
+{
+	u_int64_t	nonce;
+	u_int32_t	*nonce_words = (u_int32_t *)&nonce;
+	u_int8_t	*nonce_bytes = (u_int8_t *)&nonce;
+
+	// If rSTATESAVE0[1] set then the nonce has already been generated
+	if ((rSTATESAVE0 & kPlatformScratchFlagNonce) == 0) {
+#if WITH_RANDOM
+		if (random_get_bytes(nonce_bytes, sizeof(nonce)) != 0)
+#endif
+		{
+			memset(nonce_bytes, 0, sizeof(nonce));
+		}
+
+		rSTATESAVE2 = nonce_words[0];
+		rSTATESAVE3 = nonce_words[1];
+
+		rSTATESAVE0 |= kPlatformScratchFlagNonce;
+	} else {
+		nonce_words[0] = rSTATESAVE2;
+		nonce_words[1] = rSTATESAVE3;
+	}
+
+	return nonce;
+}
+
+bool platform_get_ecid_image_personalization_required(void)
+{
+	return chipid_get_ecid_image_personalization_required();
+}
+
+u_int32_t platform_get_osc_frequency(void)
+{
+	return chipid_get_osc_frequency();
+}
+
+u_int32_t platform_get_base_soc_voltage(void)
+{
+	return 1200;
+}
+
+int platform_get_soc_voltages(u_int32_t count, u_int32_t *voltages)
+{
+	u_int32_t cnt;
+
+	if (voltages == 0) return -1;
+
+	for (cnt = 0; cnt < count; cnt++) {
+		voltages[cnt] = platform_get_base_soc_voltage();
+	}
+
+	return 0;
+}
+
+bool platform_get_usb_cable_connected(void)
+{
+#if WITH_HW_USBPHY
+	return usbphy_is_cable_connected();
+#else
+	return false;
+#endif
+}
+
+void platform_set_dfu_status(bool dfu)
+{
+	gpio_write(GPIO_DFU_STATUS, dfu);
+}
+
+bool platform_get_force_dfu(void)
+{
+	return gpio_read(GPIO_FORCE_DFU);
+}
+
+int platform_translate_key_selector(u_int32_t key_selector, u_int32_t *key_opts)
+{
+	switch (key_selector) {
+		case IMAGE_KEYBAG_SELECTOR_PROD :
+			break;
+
+		default :
+			return -1;
+	}
+
+	*key_opts = AES_KEY_TYPE_GID0 | AES_KEY_SIZE_128;
+
+	return 0;
+}
+
+#if APPLICATION_IBOOT
+u_int64_t platform_get_memory_size(void)
+{
+        return (2 * 128 * 1024 * 1024);
+}
+
+uintptr_t platform_get_memory_region_base_optional(memory_region_type_t region)
+{
+	uintptr_t base;
+
+	switch (region) {
+		case kMemoryRegion_Panic:
+			base = SDRAM_BASE + platform_get_memory_size() - PANIC_SIZE;
+			break;
+
+		case kMemoryRegion_Display:
+			base = SDRAM_BASE + platform_get_memory_size() - PURPLE_GFX_MEMORY_LEN - PANIC_SIZE;
+			break;
+
+		case kMemoryRegion_Kernel:
+			base = SDRAM_BASE;
+			break;
+
+		default:
+			base = (uintptr_t)-1;
+	}
+
+	return base;
+}
+
+size_t platform_get_memory_region_size_optional(memory_region_type_t region)
+{
+	size_t size;
+
+	switch (region) {
+		case kMemoryRegion_Panic:
+			size = PANIC_SIZE;
+			break;
+
+		case kMemoryRegion_Display:
+			size = PURPLE_GFX_MEMORY_LEN;
+			break;
+
+#if defined(SLEEP_TOKEN_BUFFER_SIZE)
+		case kMemoryRegion_SleepToken:
+			size = SLEEP_TOKEN_BUFFER_SIZE;
+			break;
+
+#endif
+
+		case kMemoryRegion_Kernel:
+			size = platform_get_memory_size() - PURPLE_GFX_MEMORY_LEN - PANIC_SIZE;
+			break;
+
+		default:
+			size = (size_t)-1;
+	}
+
+	return size;
+}
+
+#endif
+

platform/s5l8747x/miu/miu.c

@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <arch.h>
+#include <drivers/miu.h>
+#include <platform.h>
+#include <platform/miu.h>
+#include <platform/clocks.h>
+#include <platform/memmap.h>
+#include <platform/power.h>
+#include <platform/soc/hwclocks.h>
+#include <platform/soc/miu.h>
+#include <platform/soc/power.h>
+#include <sys.h>
+
+/* memory controller stuff */
+
+#if APPLICATION_IBOOT
+
+int miu_initialize_dram(bool resume)
+{
+#if APPLICATION_IBOOT
+	/* Turn off alias from 0x10000000 to 0x08000000 */
+	rDDR1 = 1;
+
+	/* bring up sdram */
+	mcu_initialize_dram(resume);
+#endif	
+	return 0;
+}
+
+#endif /* APPLICATION_IBOOT */
+
+int miu_initialize_internal_ram(void)
+{
+#if APPLICATION_SECUREROM
+	// Ensure that rSTATESAVE0 and rSTATESAVE1 get cleared
+	rSTATESAVE0 = 0;
+	rSTATESAVE1 = 0;
+#endif /* APPLICATION_SECUREROM */
+
+	// Save the Security Epoch in the top byte of SAVESTATE0
+	rSTATESAVE0 &= ~0xFF000000;
+	rSTATESAVE0 |= (platform_get_security_epoch()) << 24;
+
+	return 0;
+}
+
+void 
+miu_select_remap(enum remap_select sel)
+{
+	switch (sel) {
+		case REMAP_SRAM:
+			rREMAP = (rREMAP & ~3) | (1 << 0) | (1 << 1); // remap, remap_sel = 1
+			break;
+		case REMAP_SDRAM:
+			rREMAP = (rREMAP & ~3) | (1 << 0) | (0 << 1); // remap, remap_sel = 0
+			break;
+	}
+}
+
+void
+miu_setup_mfc_address_filter(void)
+{
+#if ((PURPLE_GFX_MEMORY_LEN + PANIC_SIZE) & 0xFFFFF) != 0
+#error "PurpleGfxMemory must be 1 MB-aligned"
+#endif
+	uint32_t range_end = SDRAM_BASE + (uint32_t)platform_get_memory_size();
+	uint32_t range_base = range_end - PANIC_SIZE - PURPLE_GFX_MEMORY_LEN;
+	rMFC_ARF_BASE_ADDR = range_base;
+	rMFC_ARF_ADDR_MASK = ~(range_end - range_base) & 0xFFF00000;
+	rMFC_ARF_CON = 1;
+}
+
+int miu_init(void)
+{
+#if APPLICATION_IBOOT && !PRODUCT_IBEC
+	// Verify that the Security Epoch in STATESAVE0 matches
+	if ((rSTATESAVE0 >> 24) != platform_get_security_epoch()) {
+		panic("miu_init: Epoch Mismatch\n");
+	}
+#endif
+
+	/* remap whatever bank of ram we're in to zero */
+	if (TEXT_BASE == SRAM_BASE)
+		miu_select_remap(REMAP_SRAM);
+	else if ((TEXT_BASE >= SDRAM_BASE) && (TEXT_BASE < SDRAM_END))
+		miu_select_remap(REMAP_SDRAM);
+
+#if APPLICATION_IBOOT
+	miu_setup_mfc_address_filter();
+#endif
+
+	return 0;
+}

platform/s5l8747x/miu/rules.mk

@@ -0,0 +1,15 @@
+# Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+#
+# This document is the property of Apple Computer, Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Computer, Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_MIU=1
+
+ALL_OBJS += $(LOCAL_DIR)/miu.o

platform/s5l8747x/pmgr/pmgr.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <arch.h>
+#include <platform.h>
+#include <platform/timer.h>
+#include <platform/power.h>
+#include <platform/soc/power.h>
+#include <sys.h>
+#include <sys/boot.h>
+#include <sys/menu.h>
+
+
+void platform_power_init(void)
+{
+	// configure the AAM clock
+	rPWRCONF = (0 << 25) | (1<<24) | (0<<20) |		// AAM clock 12MHz, prescalar on /1
+		   (2<<16) |					// enable 2 synch flip flops
+		   (1<<14) |					// enable all OSCs in normal mode
+		   (1<<13) |					// enable all OSCs in normal mode
+		   (1<<12) |					// enable all OSCs in normal mode
+		   (1<<1);
+
+	rTMCMD = 0;    	       	  				// Stop the AAM timer
+	rTMPRE = platform_get_osc_frequency() / 1000000;	// Set timer prescale for 1 MHz
+}
+
+void platform_power_spin(u_int32_t usecs)
+{
+	rTMDATA = usecs;
+	rTMCMD = (1 << 1) | (1 << 0);				// Clear and start the AAM timer
+
+	while ((rTMALARM & 1) == 0);				// Wait for the timer to fire
+
+	rTMCMD = (1 << 1) | (0 << 0);				// Clear and stop the AAM timer
+}
+
+void platform_disable_keys(u_int32_t gid, u_int32_t uid)
+{
+	if (gid) rSECCONF = 1 << 1;
+	if (uid) rSECCONF = 1 << 0;
+}
+
+

platform/s5l8747x/pmgr/rules.mk

@@ -0,0 +1,17 @@
+# Copyright (C) 2007 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_CLOCKS=1 \
+	WITH_HW_PLATFORM_POWER=1 \
+	WITH_HW_POWER_GATING=0
+
+ALL_OBJS += $(LOCAL_DIR)/pmgr.o

platform/s5l8747x/rules.mk

@@ -0,0 +1,92 @@
+# Copyright (C) 2011-2013 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+GLOBAL_INCLUDES += $(LOCAL_DIR)/include
+
+# modules implied by this platform
+MODULES		+= \
+	platform/defaults \
+	platform/generic \
+	arch/$(ARCH)
+
+##############################################################################
+# Code running on the main CPU
+#
+ifeq ($(PLATFORM_VARIANT),)
+
+ARM_ARCH := armv7
+ARM_CPU := cortex-a5
+
+# Devmap chip ID based on sub-platform identifier
+ifeq ($(SUB_PLATFORM),s5l8747x)
+DEVMAP_CHIP_ID := 8747
+endif
+
+MAX_DFU_SIZE	:=	98304
+
+ifeq ($(TEXT_BANK),srom)
+TEXT_BASE := 0x00000000
+endif
+ifeq ($(TEXT_BANK),sram)
+TEXT_BASE := 0x22000000
+endif
+ifeq ($(TEXT_BANK),sdram)
+TEXT_BASE := 0x0FF00000
+endif
+
+OPTIONS += \
+	WITH_CLASSIC_SUSPEND_TO_RAM=1 \
+	WITH_LEGACY_PANIC_LOGS=1 \
+	WITH_NON_COHERENT_DMA=1 \
+	WITH_ROM_TRAMPOLINE=1 \
+	WITH_CONJOINED_USB_PHYS=1 \
+	PLATFORM_ENTROPY_RATIO=60 \
+	PLATFORM_IRQ_COUNT=192 \
+	TEXT_BASE="$(TEXT_BASE)" \
+	TEXT_FOOTPRINT="$(TEXT_FOOTPRINT)"
+
+GLOBAL_LDFLAGS += -seg1addr $(TEXT_BASE)
+
+ifeq ($(APPLICATION),SecureROM)
+# This selects the start of the DATA segment and the end of the INSECURE_MEMORY area
+DATA_BASE := 0x22019000
+
+OPTIONS += \
+	DATA_BASE="$(DATA_BASE)"
+
+GLOBAL_LDFLAGS += -segaddr __DATA $(DATA_BASE)
+
+# Simulation trace uses STATESAVE2 and STATESAVE3
+# We have to duplicate the literal values here as debug.h is 
+# not necessarily going have hwregbase.h in scope all the time.
+OPTIONS	+= \
+	SIMULATION_TRACE_IP_REGISTER=0x3970004c \
+	SIMULATION_TRACE_PARAMETER_REGISTER=0x39700050
+endif
+
+# SecureROM turns off the timers on G1, so turn them back on as early
+# as possible to get accurate measurements of boot time.
+# By default only do this in development builds though.
+ifeq ($(APPLICATION),iBoot)
+ifeq ($(BUILD),DEVELOPMENT)
+OPTIONS += \
+	PLATFORM_START_FUNCTION=_platform_start
+endif
+endif
+
+ALL_OBJS += \
+	 $(LOCAL_DIR)/asm.o \
+	 $(LOCAL_DIR)/init.o
+
+MODULES_ELIDE += lib/libcorecrypto
+
+endif
+