first and last commit

platform/s5l8940x/amc/amc_s5l8940x.c

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+/*
+ * Copyright (C) 2009-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#include <drivers/amc/amc.h>
+#include <drivers/amc/amc_phy.h>
+#include <drivers/amc/amc_regs.h>
+#include <drivers/dram.h>
+#include <drivers/miu.h>
+#include <sys.h>
+#include <debug.h>
+
+int mcu_initialize_dram (bool resume)
+{
+	return amc_init(resume);
+}
+
+void mcu_bypass_prep (int step)
+{
+	amc_phy_bypass_prep(step);
+}
+
+uint64_t mcu_get_memory_size (void)
+{
+	return amc_get_memory_size();
+}
+
+void amc_configure_address_decoding_and_mapping (void)
+{
+	amc_configure_default_address_decoding_and_mapping();
+}
+
+void amc_enable_slow_boot (bool enable)
+{
+	int slow_freqsel;
+	
+	if (enable) {
+		if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
+			rAMC_FREQSEL = amc_params.freqsel;
+			return;
+		}
+
+		slow_freqsel = 3;
+		rAMC_BOOTCLK = (amc_params.bootclkdivsr << 8) | 1;
+		spin(5);
+		rAMC_FREQSEL = slow_freqsel;
+		amc_phy_scale_dll(slow_freqsel, amc_params.bootclkdivsr);		
+	} else {
+		if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
+			return;
+		}
+		
+		rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_small;
+		spin(2);
+
+		rAMC_BOOTCLK &= ~1;
+		spin(5);
+		rAMC_FREQSEL = amc_params.freqsel;
+		amc_phy_scale_dll(amc_params.freqsel, 1);
+
+		rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_guided;
+	}
+}
+
+void amc_finalize (bool resume)
+{
+	uint8_t odts;
+
+#if SUPPORT_FPGA
+	rAMC_PWRMNGTEN |= 0x00000001;			// Sharing clocks between channels so do not enable clock stopping for PD or SR
+#else // SUPPORT_FPGA
+	rAMC_PWRMNGTEN |= 0x00001001;
+#endif // SUPPORT_FPGA
+
+	amc_mrcmd(MR_READ, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x4, (uintptr_t)&odts);
+	rAMC_ODTS         = 0x00010080;			// [16] => TempDrtEn, [9:0] RdIntrvl XXX based on tREFI
+
+	rAMC_PWRMNGTEN |= 0x00010000;			// Enable srclkoff as well
+	
+	if (!resume) {
+		amc_enable_autorefresh();
+	}
+	
+#if !SUPPORT_FPGA
+	// Turn of Fast Critical Word Forwarding feature and AIU CWF feature
+	// Disabled for NRT <rdar://problem/9416881>
+	rAMC_AIUPRT_RD_CWF     = 0x0001011f;
+	rAMC_QBRPARAM          = 0x00020200;
+	rAMC_QBREN             = 0x00111001;
+#endif	
+}
+
+void amc_dram_workarounds (bool resume)
+{
+	const struct amc_memory_device_info *dev_info;
+	uint32_t chip_id = platform_get_chip_id();
+	uint8_t i;
+	
+	dev_info = amc_get_memory_device_info();
+	
+	switch (dev_info->vendor_id) {
+	case JEDEC_MANUF_ID_SAMSUNG:
+
+		// <rdar://problem/9454992> H4P Samsung 35nm LPDDR2 Transition for N94
+		// TMRS for Samsung 46nm part only
+		if ((chip_id == 0x8940) && (!resume) && (dev_info->rev_id == 0)) {
+			// Test MRS Entry
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xff);
+
+			// Apply Samsung workaround <rdar://problem/9032765>
+
+			// Column Select Line pull in (230ps) TMRS(1)
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x80);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x04);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x08);
+
+			// Latch command
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
+
+			// Column Select Line pull in (230ps) TMRS(2)
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x40);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x01);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
+
+			// Latch command
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
+		}
+			
+		// <rdar://problem/11060879> Samsung 3xnm DRAMs - not functional
+		else if ((chip_id == 0x8942) && (!resume) && (dev_info->rev_id == 1) && (dev_info->rev_id2 == 0)) {
+			// Test MRS Entry
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xff);
+				
+			// PDL_M(-500ps)
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x80);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x01);
+			
+			// Latch Command
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
+		}
+
+		break;
+
+	case JEDEC_MANUF_ID_HYNIX:
+
+		if (dev_info->rev_id == 0) {
+			if (!resume) {
+				// Test MRS Exit "just in case" <rdar://problem/8769095>
+				amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
+
+				// Apply Hynix cold clamp disable workaround <rdar://problem/8907487>
+				// (but only for revid2 == 0 <rdar://problem/8943860>)
+				if ((chip_id == 0x8940) && (dev_info->rev_id2 == 0)) {
+					// Test MRS Entry
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xb0);
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xe0);
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x90);
+
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xa2);
+				}
+
+				// IOSTBP Start Time control (600ps delay)
+				if ((chip_id == 0x8942) && (dev_info->density == JEDEC_DENSITY_1Gb)) {
+					// Test MRS Entry
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xb0);
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xe0);
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x90);
+					
+					for (i = 0; i < 13; i++) {
+						amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x99);
+					}
+				}
+			}
+
+#if !SUB_TARGET_K93 && !SUB_TARGET_K94 && !SUB_TARGET_K95 && !SUB_TARGET_J33
+			// <rdar://problem/9585266> H4G UM Update: Modified setting for tMRR timing parameter
+			// override tMRR to 3 cycles (only if performing dynamic calibration)
+			if (dev_info->density == JEDEC_DENSITY_2Gb) {
+				rAMC_MODE_FREQ(0) = amc_params.freq[0].modereg | 0x3;
+			}
+#endif
+ 		} else if ((dev_info->rev_id == 1) && (dev_info->rev_id2 == 0)) {
+			
+			// <rdar://problem/11059277> Hynix 3xnm workaround solution
+			if ((chip_id == 0x8942) && (!resume)) {
+				// Test MRS Entry
+				amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xb0);
+				amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xe0);
+				amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x90);
+				
+				// Yi Enable +1 step
+				for (i = 0; i < 4; i++) {
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xf1);
+				}
+				
+				// Yi Pulse +1 step
+				for (i = 0; i < 4; i++) {
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x94);
+				}
+			}
+		}
+		break;
+
+	default:
+		break;
+	}
+}
+
+// Shift dq offset as needed.
+// In the future, it's possible the shift value changes based on SOC or DRAM vendor.
+// Thus, we need to have this function per SOC.
+void amc_dram_shift_dq_offset (int8_t *dq_offset, uint8_t num_bytes) {
+	int8_t shift_val;
+	uint8_t i;
+	const struct amc_memory_device_info *dev_info;
+    uint32_t chip_id = platform_get_chip_id();
+
+    // Do nothing for H4P
+	if (chip_id == 0x8940)
+        return;
+
+    // <rdar://problem/11802718> H4A: Need additional DQ WR/RD static offsets
+    dev_info = amc_get_memory_device_info();
+    shift_val = 0;
+    
+    switch (dev_info->vendor_id) {			
+        
+        case JEDEC_MANUF_ID_SAMSUNG:
+        case JEDEC_MANUF_ID_HYNIX:
+            
+            // -3 step shift for DRAMs not used in K93A or J33
+            if (dev_info->rev_id > 0)
+                shift_val = -3;
+
+            break;            
+
+        case JEDEC_MANUF_ID_ELPIDA:
+            
+            // -3 step shift for DRAMs not used in K93A or J33
+            if (dev_info->rev_id > 1)
+                shift_val = -3;
+
+            break;
+			
+        default:
+            dprintf(DEBUG_INFO, "Not applyig any shift to dq offsets for vendor: %d\n", dev_info->vendor_id);
+            break;
+    }
+    
+    for (i = 0; i < num_bytes; i++)
+        dq_offset[i] += shift_val;
+}

platform/s5l8940x/amc/amc_s5l8947x.c

@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2010-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#include <drivers/amc/amc.h>
+#include <drivers/amc/amc_phy.h>
+#include <drivers/amc/amc_regs.h>
+#include <drivers/dram.h>
+#include <drivers/miu.h>
+#include <sys.h>
+
+int mcu_initialize_dram (bool resume)
+{
+	return amc_init(resume);
+}
+
+void mcu_bypass_prep (int step)
+{
+	amc_phy_bypass_prep(step);
+}
+
+uint64_t mcu_get_memory_size (void)
+{
+	return amc_get_memory_size();
+}
+
+void amc_configure_address_decoding_and_mapping (void)
+{
+	amc_configure_default_address_decoding_and_mapping();
+}
+
+void amc_enable_slow_boot (bool enable)
+{
+	int slow_freqsel;
+	
+	if (enable) {
+		if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
+			rAMC_FREQSEL = amc_params.freqsel;
+			return;
+		}
+
+		slow_freqsel = 3;
+		rAMC_BOOTCLK = (amc_params.bootclkdivsr << 8) | 1;
+		spin(5);
+		rAMC_FREQSEL = slow_freqsel;
+		amc_phy_scale_dll(slow_freqsel, amc_params.bootclkdivsr);		
+	} else {
+		if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
+			return;
+		}
+		
+		rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_small;
+		spin(2);
+
+		rAMC_BOOTCLK &= ~1;
+		spin(5);
+		rAMC_FREQSEL = amc_params.freqsel;
+		amc_phy_scale_dll(amc_params.freqsel, 1);
+
+		rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_guided;
+	}
+}
+
+void amc_finalize (bool resume)
+{
+	uint8_t odts;
+
+#if SUPPORT_FPGA
+	rAMC_PWRMNGTEN |= 0x00000001;			// Sharing clocks between channels so do not enable clock stopping for PD or SR
+#else
+	rAMC_PWRMNGTEN |= 0x00011011;
+#endif
+
+	rAMC_AREFPARAM    |= (0x00001000);		// Turn on freq change waiting for refresh and self-refresh exit
+
+	amc_mrcmd(MR_READ, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x4, (uintptr_t)&odts);
+	rAMC_ODTS         = 0x00010320;			// [16] => TempDrtEn, [9:0] RdIntrvl XXX based on tREFI
+
+	if (!resume) {
+		amc_enable_autorefresh();
+	}
+
+#if SUPPORT_FPGA
+	rAMC_FREQSEL = amc_params.freqsel;
+#endif
+
+#if !SUPPORT_FPGA
+	// Turn of Fast Critical Word Forwarding feature and AIU CWF feature
+	// Disabled for NRT <rdar://problem/9416881>
+	rAMC_AIUPRT_RD_CWF     = 0x00161600;
+	rAMC_QBRPARAM          = 0x00810000;
+	rAMC_QBREN             = 0x00111001;
+#endif
+}
+
+void amc_dram_workarounds (bool resume)
+{
+	// XXX - Possibly look in s5l8950x amc.c to see possible workarounds.
+	return;
+}
+
+// Shift dq offset as needed.
+// In the future, it's possible the shift value changes based on SOC or DRAM vendor.
+// Thus, we need to have this function per SOC.
+void amc_dram_shift_dq_offset (int8_t *dq_offset, uint8_t num_bytes) {
+	int8_t shift_val;
+	uint8_t i;
+	const struct amc_memory_device_info *dev_info;
+	
+	dev_info = amc_get_memory_device_info();
+	
+	switch (dev_info->vendor_id) {			
+		case JEDEC_MANUF_ID_HYNIX:
+		case JEDEC_MANUF_ID_SAMSUNG:
+		case JEDEC_MANUF_ID_ELPIDA:
+			
+			// shift 2 steps
+			shift_val = -2;
+			break;
+			
+		default:
+			shift_val = 0;
+			break;
+	}
+	
+	for (i = 0; i < num_bytes; i++)
+		dq_offset[i] += shift_val;	
+}

platform/s5l8940x/amc/rules.mk

@@ -0,0 +1,21 @@
+# Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_AMC=1
+
+ifneq ($(SUB_PLATFORM), s5l8947x)
+ALL_OBJS += \
+	$(LOCAL_DIR)/amc_s5l8940x.o
+else
+ALL_OBJS += \
+	$(LOCAL_DIR)/amc_s5l8947x.o
+endif

platform/s5l8940x/chipid/chipid.c

@@ -0,0 +1,288 @@
+/*
+ * Copyright (C) 2009-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <lib/env.h>
+#include <platform.h>
+#include <platform/soc/chipid.h>
+#include <platform/soc/hwclocks.h>
+
+#if SUPPORT_FPGA
+#define _rCFG_FUSE0				(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x00))
+#undef rCFG_FUSE0
+// XXX ECID (1 << 7)?
+// XXX double-check memory values
+#define rCFG_FUSE0		((0 << 31) | (3 << 28) | (0xE << 24) | (2 << 22) | \
+			 (0 << 9) | (1 << 8) | (3 << 4) | (kPlatformSecurityDomainDarwin << 2) | (0 << 1) | (0 << 0) | \
+			 _rCFG_FUSE0)
+#endif
+
+#if SUB_PLATFORM_S5L8940X
+#define DEFAULT_SOC_VOLTAGE_LOW		1000
+#define DEFAULT_SOC_VOLTAGE_MED		1100
+#define DEFAULT_SOC_VOLTAGE_HIGH	1200
+#define DEFAULT_CPU_VOLTAGE_LOW		1000
+#define DEFAULT_CPU_VOLTAGE_MED		1150
+#define DEFAULT_CPU_VOLTAGE_HIGH	1250
+#define BASE_SOC_VOLTAGE_LOW		875
+#define BASE_SOC_VOLTAGE_MED		975
+#define BASE_SOC_VOLTAGE_HIGH		1075
+#define BASE_CPU_VOLTAGE_LOW		875
+#define BASE_CPU_VOLTAGE_MED		975
+#define BASE_CPU_VOLTAGE_HIGH		1075
+#elif SUB_PLATFORM_S5L8942X
+#define DEFAULT_SOC_VOLTAGE_LOW		925
+#define DEFAULT_SOC_VOLTAGE_MED		1000
+#define DEFAULT_SOC_VOLTAGE_HIGH	1100
+#define DEFAULT_CPU_VOLTAGE_LOW		925
+#define DEFAULT_CPU_VOLTAGE_MED		1025
+#define DEFAULT_CPU_VOLTAGE_HIGH	1125
+#define BASE_SOC_VOLTAGE_LOW		800
+#define BASE_SOC_VOLTAGE_MED		825
+#define BASE_SOC_VOLTAGE_HIGH		925
+#define BASE_CPU_VOLTAGE_LOW		800
+#define BASE_CPU_VOLTAGE_MED		875
+#define BASE_CPU_VOLTAGE_HIGH		975
+#elif SUB_PLATFORM_S5L8947X
+#define DEFAULT_SOC_VOLTAGE_LOW		1100
+#define DEFAULT_SOC_VOLTAGE_MED		1100
+#define DEFAULT_SOC_VOLTAGE_HIGH	1100
+#define DEFAULT_CPU_VOLTAGE_LOW		1100
+#define DEFAULT_CPU_VOLTAGE_MED		1100
+#define DEFAULT_CPU_VOLTAGE_HIGH	1100
+#define BASE_SOC_VOLTAGE_LOW		1075
+#define BASE_SOC_VOLTAGE_MED		1075
+#define BASE_SOC_VOLTAGE_HIGH		1075
+#define BASE_CPU_VOLTAGE_LOW		1075
+#define BASE_CPU_VOLTAGE_MED		1075
+#define BASE_CPU_VOLTAGE_HIGH		1075
+#endif
+
+bool chipid_get_production_mode(void)
+{
+	return ((rCFG_FUSE0 >> 0) & 1) != 0;
+}
+
+void chipid_clear_production_mode(void)
+{
+#if SUPPORT_FPGA
+	_rCFG_FUSE0 &= ~1;
+#else
+	rCFG_FUSE0 &= ~1;
+#endif
+}
+
+bool chipid_get_secure_mode(void)
+{
+	return ((rCFG_FUSE0 >> 1) & 1) != 0;
+}
+
+u_int32_t chipid_get_security_domain(void)
+{
+	return (rCFG_FUSE0 >> 2) & 3;
+}
+
+u_int32_t chipid_get_board_id(void)
+{
+	return (rCFG_FUSE0 >> 4) & 3;
+}
+
+bool chipid_get_ecid_image_personalization_required(void)
+{
+	return ((rCFG_FUSE0 >> 7) & 1) != 0;
+}
+
+u_int32_t chipid_get_minimum_epoch(void)
+{
+	return (rCFG_FUSE0 >> 9) & 0x7F;
+}
+
+u_int32_t chipid_get_chip_id(void)
+{
+#if SUB_PLATFORM_S5L8940X
+        return 0x8940;
+#elif SUB_PLATFORM_S5L8942X
+	return 0x8942;
+#elif SUB_PLATFORM_S5L8947X
+	return 0x8947;
+#endif
+}
+
+u_int32_t chipid_get_chip_revision(void)
+{
+	return (((rECIDHI >> 13) & 0x7) << 4) | (((rECIDHI >> 10) & 0x7) << 0);
+}
+
+u_int32_t chipid_get_osc_frequency(void)
+{
+	return OSC_FREQ;
+}
+
+u_int64_t chipid_get_ecid_id(void)
+{
+	u_int64_t ecid = 0;
+
+#if SUPPORT_FPGA
+	ecid = 0x000012345678ABCDULL;
+#else
+	ecid |= ((rECIDLO >>  0)) & ((1ULL << (21 -  0)) - 1);	// LOT_ID
+
+	ecid <<= (26 - 21);
+	ecid |= ((rECIDLO >> 21)) & ((1ULL << (26 - 21)) - 1);	// WAFER_NUM
+
+	ecid <<= (10 -  2);
+	ecid |= ((rECIDHI >>  2)) & ((1ULL << (10 -  2)) - 1);	// Y_POS
+
+	ecid <<= (32 - 26);
+	ecid |= ((rECIDLO >> 26)) & ((1ULL << (32 - 26)) - 1);	// X_POS_H
+
+	ecid <<= ( 2 -  0);
+	ecid |= ((rECIDHI >>  0)) & ((1ULL << ( 2 -  0)) - 1);	// X_POS_L
+#endif
+
+	return ecid;
+}
+
+u_int64_t chipid_get_die_id(void)
+{
+	return ((u_int64_t)rECIDHI << 32) | rECIDLO;
+}
+
+u_int32_t chipid_get_soc_voltage(u_int32_t index)
+{
+	u_int32_t soc_voltage = 0;
+	u_int32_t soc_bin_offset_data = 0, soc_bin_data = (rCFG_FUSE1 >> 5) & 0x1FF;
+	int32_t   soc_bin_offset;
+
+#if DEBUG_BUILD && WITH_ENV
+	soc_bin_offset_data = env_get_uint("soc-bin-offset", 0);
+
+	switch (index) {
+		case CHIPID_SOC_VOLTAGE_LOW	: soc_bin_offset_data = (soc_bin_offset_data >>  0) & 0xff;		break;
+		case CHIPID_SOC_VOLTAGE_MED	: soc_bin_offset_data = (soc_bin_offset_data >>  8) & 0xff;		break;
+		case CHIPID_SOC_VOLTAGE_HIGH	: soc_bin_offset_data = (soc_bin_offset_data >> 16) & 0xff;		break;
+		default				:									break;
+	}
+#endif
+
+	// if bin data is all zeros, bin data is not valid
+	if (soc_bin_data == 0) {
+		switch (index) {
+			case CHIPID_SOC_VOLTAGE_LOW	: soc_voltage = DEFAULT_SOC_VOLTAGE_LOW;	break;
+			case CHIPID_SOC_VOLTAGE_MED	: soc_voltage = DEFAULT_SOC_VOLTAGE_MED;	break;
+			case CHIPID_SOC_VOLTAGE_HIGH	: soc_voltage = DEFAULT_SOC_VOLTAGE_HIGH;	break;
+			default				:						break;
+		}
+	} else {
+		switch (index) {
+			case CHIPID_SOC_VOLTAGE_LOW	: soc_voltage = BASE_SOC_VOLTAGE_LOW  + 25 * ((soc_bin_data>>6)&7);	break;
+			case CHIPID_SOC_VOLTAGE_MED	: soc_voltage = BASE_SOC_VOLTAGE_MED  + 25 * ((soc_bin_data>>3)&7);	break;
+			case CHIPID_SOC_VOLTAGE_HIGH	: soc_voltage = BASE_SOC_VOLTAGE_HIGH + 25 * ((soc_bin_data>>0)&7);	break;
+			default				:									break;
+		}
+	}
+
+	soc_bin_offset = soc_bin_offset_data | (((soc_bin_offset_data & 0x80) == 0) ? 0 : 0xffffff00);
+	soc_bin_offset *= 25;
+
+	return soc_voltage + soc_bin_offset;
+}
+
+u_int32_t chipid_get_cpu_voltage(u_int32_t index)
+{
+	u_int32_t cpu_voltage = 0;
+	u_int32_t cpu_bin_offset_data = 0, cpu_bin_data = ((((u_int64_t)rCFG_FUSE1 << 32) | rCFG_FUSE0) >> 28) & 0x1FF;
+	int32_t   cpu_bin_offset;
+
+#if DEBUG_BUILD && WITH_ENV
+	cpu_bin_offset_data = env_get_uint("cpu-bin-offset", 0);
+
+	switch (index) {
+		case CHIPID_CPU_VOLTAGE_LOW	: cpu_bin_offset_data = (cpu_bin_offset_data >>  0) & 0xff;		break;
+		case CHIPID_CPU_VOLTAGE_MED	: cpu_bin_offset_data = (cpu_bin_offset_data >>  8) & 0xff;	 	break;
+		case CHIPID_CPU_VOLTAGE_HIGH	: cpu_bin_offset_data = (cpu_bin_offset_data >> 16) & 0xff;		break;
+		default				:									break;
+	}
+
+#endif
+	// if bin data is all zeros, bin data is not valid
+	if (cpu_bin_data == 0) {
+		switch (index) {
+			case CHIPID_CPU_VOLTAGE_LOW	: cpu_voltage = DEFAULT_CPU_VOLTAGE_LOW;	break;
+			case CHIPID_CPU_VOLTAGE_MED	: cpu_voltage = DEFAULT_CPU_VOLTAGE_MED;	break;
+			case CHIPID_CPU_VOLTAGE_HIGH	: cpu_voltage = DEFAULT_CPU_VOLTAGE_HIGH;	break;
+			default				:						break;
+		}
+	} else {
+		switch (index) {
+			case CHIPID_CPU_VOLTAGE_LOW	: cpu_voltage = BASE_CPU_VOLTAGE_LOW  + 25 * ((cpu_bin_data>>6)&7);	break;
+			case CHIPID_CPU_VOLTAGE_MED	: cpu_voltage = BASE_CPU_VOLTAGE_MED  + 25 * ((cpu_bin_data>>3)&7);	break;
+			case CHIPID_CPU_VOLTAGE_HIGH	: cpu_voltage = BASE_CPU_VOLTAGE_HIGH + 25 * ((cpu_bin_data>>0)&7);	break;
+			default				:									break;
+		}
+	}
+
+	cpu_bin_offset = cpu_bin_offset_data | (((cpu_bin_offset_data & 0x80) == 0) ? 0 : 0xffffff00);
+	cpu_bin_offset *= 25;
+
+	return cpu_voltage + cpu_bin_offset;
+}
+
+bool chipid_get_fuse_lock(void)
+{
+	return (rCFG_FUSE1 & (1 << 31)) != 0;
+}
+
+void chipid_set_fuse_lock(bool locked)
+{
+	if (locked) rCFG_FUSE1 |= 1 << 31;
+}
+
+u_int32_t chipid_get_memory_density(void)
+{
+	u_int32_t data = (rCFG_FUSE0 >> 24) & 0x7;
+
+	if (chipid_get_memory_manufacturer() == 0) data = 5;
+
+	return 1 << (24 + data);
+}
+
+u_int32_t chipid_get_memory_manufacturer(void)
+{
+	return (rCFG_FUSE0 >> 20) & 0xF;
+}
+
+u_int32_t chipid_get_memory_ranks(void)
+{
+	u_int32_t data = (rCFG_FUSE0 >> 27) & 0x1;
+
+	if (chipid_get_memory_manufacturer() ==	0) data	= 0;
+
+	return 1 << data;
+}
+
+u_int32_t chipid_get_memory_width(void)
+{
+	u_int32_t data = (rCFG_FUSE0 >> 18) & 0x3;
+
+	if (chipid_get_memory_manufacturer() ==	0) data	= 2;
+
+	return 16 << data;
+}
+
+bool chipid_get_memory_dqcal(u_int32_t *cal_data)
+{
+	/* Swizzle the fuses into a standard format.  One word each
+	 * for CH0 read, CH0 write, etc. */
+	cal_data[0] = rCFG_FUSE2 & 0xffff;
+	cal_data[1] = rCFG_FUSE3 & 0xffff;
+	cal_data[2] = rCFG_FUSE2 >> 16;
+	cal_data[3] = rCFG_FUSE3 >> 16;
+	return true;
+}

platform/s5l8940x/chipid/rules.mk

@@ -0,0 +1,15 @@
+# Copyright (C) 2009 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_PLATFORM_CHIPID=1
+
+ALL_OBJS += $(LOCAL_DIR)/chipid.o

platform/s5l8940x/include/platform/amcconfig.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#include SUB_PLATFORM_HEADER(amcconfig)

platform/s5l8940x/include/platform/amcconfig_s5l8940x.h

@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2009-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#if WITH_TARGET_AMC_PARAMS
+#include <target/amcconfig.h>
+#else
+static const struct amc_param amc_params = {
+	.flags                  = FLAG_AMC_PARAM_ENABLE_AIU | FLAG_AMC_PARAM_SLOW_BOOT,
+
+	.freqsel                = 0,
+	.tREFi                  = 0x5d,
+	.longsrcnt              = 0x0802,
+	.srextrarefcnt		= 0x00010000,
+	.tREFi_1Gb              = 0xbb,
+	.longsrcnt_1Gb          = 0x0401,
+	.rdlat                  = 6,
+	.wrlat                  = 3,
+	.phyrdlat               = 6,				// rdlat
+	.phywrlat   		= 3,
+	.pdn                    = 0x33000303,
+	.read                   = 0x00000103,
+	.bustat                 = 0x00020002,
+	.derate                 = 0x28831258,
+	.mcphyupdate            = 0x00000009,			// <rdar://problem/8199905> <rdar://problem/8256572>
+	.pwrmngtparam_small     = 0x00013000,
+	.pwrmngtparam_guided    = 0x00fa3000,
+	.bootclkdivsr           = 8,
+	.aref_freq0		= 0x00100100,
+	.aref_freq1		= 0x00100000,
+	.chnldec		= 0x00000F00,
+	.arefparam              = 0x06000000,
+	.readleveling           = 0x02000301,
+
+	.freq                   = {
+		{	// 400MHz
+			.cas         = 0x00000308,
+			.pch         = 0x00030611,
+			.act         = 0x14040908,
+			.autoref     = 0x1834a000,
+			.selfref     = 0x00038060,
+			.modereg     = 0x00240502,
+			.mifcassch   = 0x001f0111,
+			.mifqmaxctrl = 0x00000000,
+		},
+		{	// 200MHz
+			.cas         = 0x00000004,
+			.pch         = 0x00000009,
+			.act         = 0x0a020504,
+			.autoref     = 0x0c1a0000,
+			.selfref     = 0x0001c000,
+			.modereg     = 0x00120000,
+			.mifcassch   = 0x00000000,
+			.mifqmaxctrl = 0x00000000,
+		},
+		{	// 100MHz
+			.cas         = 0x00000003,
+			.pch         = 0x00000005,
+			.act         = 0x08020303,
+			.autoref     = 0x060d0000,
+			.selfref     = 0x0000e000,
+			.modereg     = 0x00090000,
+			.mifcassch   = 0x00000000,
+			.mifqmaxctrl = 0x00000000,
+		},
+		{	// 50 & 24MHz
+			.cas         = 0x00000003,
+			.pch         = 0x00000003,
+			.act         = 0x08020303,
+			.autoref     = 0x03070000,
+			.selfref     = 0x00007000,
+			.modereg     = 0x00060000,
+			.mifcassch   = 0x00000010,
+			.mifqmaxctrl = 0x00000001,
+		}
+	}
+};
+
+static const struct amc_tunable amc_tunables[] = {
+	// These settings are common across all H4x and H5P.  Channel decode and hashing
+	// is done in mainline init code.  Any tunables that match hardware defaults are
+	// omitted here.
+	
+	{ &rAMC_AIUPRT_CFG,		0x00070000 },		// address error enable
+	{ &rAMC_AIUPRT_RD_GEN,		0x00000018 },		// fence read detect on GFX
+	{ &rAMC_AIUPRT_WR,		0x00000001 },		// out-of-order write, ignore B-bit
+
+	{ &rAMC_AIU_RDBRSTLEN,		0x01010101 },		// burst len is 64B
+	{ &rAMC_AIU_RDMINCRD,		0x7B7B7C7B },		// RT:NRT:CPU:GFX = 40:40:5:10
+	{ &rAMC_AIU_WRBRSTLEN,		0x01010101 },		// burst len is 64B
+	{ &rAMC_AIU_WRMINCRD,		0x7B7B7C7B },		// RT:NRT:CPU:GFX = 40:40:5:10
+
+	{ &rAMC_AIU_CPUSPCREQ,		0x00000019 },		// CPU ageout timer
+	{ &rAMC_AIU_GFXSPCREQ,		0x00000032 },		// GFX ageout timer
+	{ &rAMC_AIU_NRTSPCREQ,		0x00000032 },		// Hperf-NRT ageout timer
+	{ &rAMC_AIU_RTSPCREQ,		0x00000019 },		// Hperf-RT ageout timer
+	{ &rAMC_AIU_WPQSCH,		0x10001000 },		// only supported for Hperf-RT
+	{ &rAMC_AIU_THOTLCPUPARAM,	0x0A4640C4 },
+	{ &rAMC_AIU_THOTLRTPARAM,	0x0A4640C4 },
+	{ &rAMC_AIU_THOTLNRTPARAM,	0x00000000 },
+	{ &rAMC_AIU_THOTLGFXPARAM,	0x00000000 },
+	{ &rAMC_AIU_PUSHEN,		0x00001100 },		// only supported for Hperf-RT
+
+	{ &rAMC_OPIDLETMR,		0x00200000 },
+	{ &rAMC_OPTMRADJEN,		0x00000001 },
+	{ &rAMC_OPTMRADJPARAM,		0x20400064 },
+
+	{ &rAMC_MIFACTSCH,		0x00000001 },
+
+	{ &rAMC_PSQRQTIMER0,		0x00000040 },		// RTG bypass up to 64 transactions
+	{ &rAMC_PSQRQTIMER1,		0x00000018 },		// RTY bypass up to 24 transactions
+	{ &rAMC_PSQRQTIMER2,		0x00000020 },		// RTG bypass up to 32 transactions
+	{ &rAMC_PSQRQBRST,		0x040c040c },		// RTR transactions don't affect read burst size
+	{ &rAMC_PSQRQSCHCRD,		0x002028f5 },		// read credits = 2 * write credits
+	{ &rAMC_PSQWQBRST,		0x0208040c },		// RTR reads cause reduced write burst size
+	{ &rAMC_PSQWQSCHCRD,		0x001014f5 },		// write credits = 1/2 * read credits
+	{ &rAMC_MCUQOS,			0x00010f04 },		// RTG=4, RTY=15, enable pick-oldest-RTY
+
+	// Platform specific
+	
+	{ &rAMC_AIU_RDMAXCRD,		0x2828050a },		// RT:NRT:CPU:GFX = 40:40:5:10
+	{ &rAMC_AIU_RDREFL,		0x21210408 },		// 5/6 of AIURDMAXCRD fields
+	{ &rAMC_AIU_WRMAXCRD,		0x2828050a }, 		// RT:NRT:CPU:GFX = 40:40:5:10
+	{ &rAMC_AIU_WRREFL,		0x21210408 },		// 5/6 of AIUWRMAXCRD fields
+	{ &rAMC_AIU_THOTLEN,		0x00001111 },		// enable throttling
+	{ &rAMC_PSQWQCTL1,		0x000000C0 },		// ages write out faster than default (1/2 SelfRef)
+	{ &rAMC_MCUQOSLLT,		0x00010104 },
+	{ &rAMC_PWRMNGTPARAM,		0x01801000 },		// SelfRef timer = 384 cycles
+
+	// There is a bug around write merge, which we believe is avoided 
+	// in current drivers: <rdar://problem/9076703>
+	// Power and performance measurements of disabling write merging were
+	// done: <rdar://problem/9092558> <rdar://problem/9087726>
+	{ &rAMC_PSQWQCTL0,		0x00010100 },		// Write merge enable
+};
+#endif

platform/s5l8940x/include/platform/amcconfig_s5l8942x.h

@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2011-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#if WITH_TARGET_AMC_PARAMS
+#include <target/amcconfig.h>
+#else
+static const struct amc_param amc_params = {
+	.flags     	 	= (FLAG_AMC_PARAM_SLOW_BOOT | FLAG_AMC_PARAM_RECONFIG | FLAG_AMC_PARAM_ENABLE_AIU),
+
+	.freqsel                = 0,
+	.tREFi                  = 0x5d,
+	.longsrcnt              = 0x0802,
+	.srextrarefcnt		= 0x00010000,
+	.tREFi_1Gb              = 0xbb,
+	.longsrcnt_1Gb          = 0x0401,
+	.rdlat                  = 6,
+	.wrlat                  = 3,
+	.phyrdlat               = 6,				// rdlat
+	.phywrlat   		= 3,
+	.pdn                    = 0x33000303,
+	.read                   = 0x00000103,
+	.bustat                 = 0x00020002,
+	.derate                 = 0x28831258,
+	.mcphyupdate            = 0x00000009,			// <rdar://problem/8199905> <rdar://problem/8256572>
+	.pwrmngtparam_small     = 0x00013000,
+	.pwrmngtparam_guided    = 0x00fa3000,
+	.bootclkdivsr           = 8,
+	.aref_freq0		= 0x00100100,
+	.aref_freq1		= 0x00100000,
+	.chnldec		= 0x00000F00,
+	.arefparam              = 0x06000000,
+	.readleveling           = 0x02000301,
+
+	.freq                   = {
+		{	// 400MHz
+			.cas         = 0x00000308,
+			.pch         = 0x00030611,
+			.act         = 0x14040908,
+			.autoref     = 0x1834a000,
+			.selfref     = 0x00038060,
+			.modereg     = 0x00240502,
+			.mifcassch   = 0x001f0111,
+			.mifqmaxctrl = 0x00000000,
+		},
+		{	// 200MHz
+			.cas         = 0x00000004,
+			.pch         = 0x00000009,
+			.act         = 0x0a020504,
+			.autoref     = 0x0c1a0000,
+			.selfref     = 0x0001c000,
+			.modereg     = 0x00120000,
+			.mifcassch   = 0x00000000,
+			.mifqmaxctrl = 0x00000000,
+		},
+		{	// 100MHz
+			.cas         = 0x00000003,
+			.pch         = 0x00000005,
+			.act         = 0x08020303,
+			.autoref     = 0x060d0000,
+			.selfref     = 0x0000e000,
+			.modereg     = 0x00090000,
+			.mifcassch   = 0x00000000,
+			.mifqmaxctrl = 0x00000000,
+		},
+		{	// 50 & 24MHz
+			.cas         = 0x00000003,
+			.pch         = 0x00000003,
+			.act         = 0x08020303,
+			.autoref     = 0x03070000,
+			.selfref     = 0x00007000,
+			.modereg     = 0x00060000,
+			.mifcassch   = 0x00000010,
+			.mifqmaxctrl = 0x00000001,
+		}
+	}
+};
+
+static const struct amc_tunable amc_tunables[] = {
+	// These settings are common across all H4x and H5P.  Channel decode and hashing
+	// is done in mainline init code.  Any tunables that match hardware defaults are
+	// omitted here.
+	
+	{ &rAMC_AIUPRT_CFG,		0x00070000 },		// address error enable
+	{ &rAMC_AIUPRT_RD_GEN,		0x00000018 },		// fence read detect on GFX
+	{ &rAMC_AIUPRT_WR,		0x00000001 },		// out-of-order write, ignore B-bit
+
+	{ &rAMC_AIU_RDBRSTLEN,		0x01010101 },		// burst len is 64B
+	{ &rAMC_AIU_RDMINCRD,		0x7B7B7C7B },		// RT:NRT:CPU:GFX = 40:40:5:10
+	{ &rAMC_AIU_WRBRSTLEN,		0x01010101 },		// burst len is 64B
+	{ &rAMC_AIU_WRMINCRD,		0x7B7B7C7B },		// RT:NRT:CPU:GFX = 40:40:5:10
+
+	{ &rAMC_AIU_CPUSPCREQ,		0x00000019 },		// CPU ageout timer
+	{ &rAMC_AIU_GFXSPCREQ,		0x00000032 },		// GFX ageout timer
+	{ &rAMC_AIU_NRTSPCREQ,		0x00000032 },		// Hperf-NRT ageout timer
+	{ &rAMC_AIU_RTSPCREQ,		0x00000019 },		// Hperf-RT ageout timer
+	{ &rAMC_AIU_WPQSCH,		0x10001000 },		// only supported for Hperf-RT
+	{ &rAMC_AIU_THOTLCPUPARAM,	0x0A4640C4 },
+	{ &rAMC_AIU_THOTLRTPARAM,	0x0A4640C4 },
+	{ &rAMC_AIU_THOTLNRTPARAM,	0x00000000 },
+	{ &rAMC_AIU_THOTLGFXPARAM,	0x00000000 },
+	{ &rAMC_AIU_PUSHEN,		0x00001100 },		// only supported for Hperf-RT
+
+	{ &rAMC_OPIDLETMR,		0x00200000 },
+	{ &rAMC_OPTMRADJEN,		0x00000001 },
+	{ &rAMC_OPTMRADJPARAM,		0x20400064 },
+
+	{ &rAMC_MIFACTSCH,		0x00000001 },
+
+	{ &rAMC_PSQRQTIMER0,		0x00000040 },		// RTG bypass up to 64 transactions
+	{ &rAMC_PSQRQTIMER1,		0x00000018 },		// RTY bypass up to 24 transactions
+	{ &rAMC_PSQRQTIMER2,		0x00000020 },		// RTG bypass up to 32 transactions
+	{ &rAMC_PSQRQBRST,		0x040c040c },		// RTR transactions don't affect read burst size
+	{ &rAMC_PSQRQSCHCRD,		0x002028f5 },		// read credits = 2 * write credits
+	{ &rAMC_PSQWQBRST,		0x0208040c },		// RTR reads cause reduced write burst size
+	{ &rAMC_PSQWQSCHCRD,		0x001014f5 },		// write credits = 1/2 * read credits
+	{ &rAMC_MCUQOS,			0x00010f04 },		// RTG=4, RTY=15, enable pick-oldest-RTY
+
+	// Platform specific
+	
+	{ &rAMC_AIU_RDMAXCRD,		0x2828050a },		// RT:NRT:CPU:GFX = 40:40:5:10
+	{ &rAMC_AIU_RDREFL,		0x21210408 },		// 5/6 of AIURDMAXCRD fields
+	{ &rAMC_AIU_WRMAXCRD,		0x2828050a }, 		// RT:NRT:CPU:GFX = 40:40:5:10
+	{ &rAMC_AIU_WRREFL,		0x21210408 },		// 5/6 of AIUWRMAXCRD fields
+	{ &rAMC_AIU_THOTLEN,		0x00001111 },		// enable throttling
+	{ &rAMC_PSQWQCTL1,		0x000000C0 },		// ages write out faster than default (1/2 SelfRef)
+	{ &rAMC_MCUQOSLLT,		0x00010104 },
+	{ &rAMC_PWRMNGTPARAM,		0x01801000 },		// SelfRef timer = 384 cycles
+
+	// There is a bug around write merge, which we believe is avoided 
+	// in current drivers: <rdar://problem/9076703>
+	// Power and performance measurements of disabling write merging were
+	// done: <rdar://problem/9092558> <rdar://problem/9087726>
+	{ &rAMC_PSQWQCTL0,		0x00010100 },		// Write merge enable
+};
+#endif

platform/s5l8940x/include/platform/amcconfig_s5l8947x.h

@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2011-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#if WITH_TARGET_AMC_PARAMS
+#include <target/amcconfig.h>
+#else
+static const struct amc_param amc_params = {
+	.flags     	 	= (FLAG_AMC_PARAM_SLOW_BOOT | FLAG_AMC_PARAM_RECONFIG | FLAG_AMC_PARAM_ENABLE_AIU | FLAG_AMC_PARAM_MRR_BYTE_SWIZZLE | FLAG_AMC_PARAM_MRR_BIT_SWIZZLE),
+
+	.tREFi      		= 0x5d,
+	.longsrcnt  		= 0x2008,
+	.tREFi_1Gb		= 0x5d,
+	.longsrcnt_1Gb		= 0x2008,
+	.rdlat      		= 8,	
+	.wrlat      		= 4,	
+	.phyrdlat   		= 8,	
+	.phywrlat   		= 4,	
+	.pdn        		= 0x33000503,
+	.read       		= 0x00000103,
+	.bustat     		= 0x00222212,
+	.bustat2    		= 0x00222212,
+	.derate     		= 0x34b3187b,
+	.mcphyupdate		= 0x05030000,
+	.autoref_params		= 0x22,		// <rdar://problem/9133484> MIF: tREFBW violation due to freq change
+	.pwrmngtparam_small	= 0x00011000,
+	.pwrmngtparam_guided	= 0x03001000,
+	.chnldec		= 0x00000100,
+	.chnldec2		= 0x003ffffd,
+	.arefparam		= 0x0600a000,
+	.bootclkdivsr		= 0xa,	     
+	.aref_freq0		= 0x00100100,
+	.aref_freq1		= 0x00100100,
+	.srextrarefcnt		= 0x00010000,
+	.readleveling           = 0x01000301,
+
+	.freq     		= {
+		{	// 532.8MHz
+			.cas         = 0x0000040a,
+			.pch         = 0x00040817,
+			.act         = 0x1b060c0a,
+			.autoref     = 0x20469000,
+			.selfref     = 0x0004b080,
+			.modereg     = 0x00300502,
+			.mifcassch   = 0x001f0111,
+		},
+		{	// 400MHz
+			.cas         = 0x00000008,
+			.pch         = 0x00000012,
+			.act         = 0x14050a08,
+			.autoref     = 0x18340000,
+			.selfref     = 0x00038000,
+			.modereg     = 0x00240000,
+			.mifcassch   = 0x00000010,
+		},
+		{	// 106.6MHz
+			.cas         = 0x00000003,
+			.pch         = 0x00000005,
+			.act         = 0x08020303,
+			.autoref     = 0x070e0000,
+			.selfref     = 0x0000f000,
+			.modereg     = 0x000a0000,
+			.mifcassch   = 0x00000000,
+		},
+		{	// 53.3MHz
+			.cas         = 0x00000003,
+			.pch         = 0x00000003,
+			.act         = 0x08020303,
+			.autoref     = 0x04070000,
+			.selfref     = 0x00008000,
+			.modereg     = 0x00060000,
+			.mifcassch   = 0x00000010,
+		}
+	}
+};
+
+static const struct amc_tunable amc_tunables[] = {
+	// These settings are common across all H4x and H5P.  Channel decode and hashing
+	// is done in mainline init code.  Any tunables that match hardware defaults are
+	// omitted here.
+
+	{ &rAMC_AIUPRT_CFG,		0x00070000 },		// address error enable
+	{ &rAMC_AIUPRT_RD_GEN,		0x00000018 },		// fence read detect on GFX
+	{ &rAMC_AIUPRT_WR,		0x00000001 },		// out-of-order write, ignore B-bit
+	{ &rAMC_AIU_RDBRSTLEN,		0x01010101 },		// burst len is 64B
+	{ &rAMC_AIU_WRBRSTLEN,		0x01010101 },		// burst len is 64B
+	{ &rAMC_AIU_CPUSPCREQ,		0x00000019 },		// CPU ageout timer
+	{ &rAMC_AIU_GFXSPCREQ,		0x00000032 },		// GFX ageout timer
+	{ &rAMC_AIU_NRTSPCREQ,		0x00000032 },		// Hperf-NRT ageout timer
+	{ &rAMC_AIU_RTSPCREQ,		0x00000019 },		// Hperf-RT ageout timer
+	{ &rAMC_AIU_PUSHEN,		0x00001100 },		// only supported for Hperf-RT
+
+	{ &rAMC_OPIDLETMR,		0x00200000 },
+	{ &rAMC_OPTMRADJPARAM,		0x20400064 },
+	{ &rAMC_MIFACTSCH,		0x00000001 },
+	{ &rAMC_PSQRQTIMER0,		0x00000040 },		// RTG bypass up to 64 transactions
+	{ &rAMC_PSQRQTIMER1,		0x00000018 },		// RTY bypass up to 24 transactions
+	{ &rAMC_PSQRQTIMER2,		0x00000020 },		// RTG bypass up to 32 transactions
+	{ &rAMC_PSQRQBRST,		0x040c040c },		// RTR transactions don't affect read burst size
+	{ &rAMC_PSQRQSCHCRD,		0x002028f5 },		// read credits = 2 * write credits
+	{ &rAMC_PSQWQBRST,		0x0208040c },		// RTR reads cause reduced write burst size
+	{ &rAMC_PSQWQSCHCRD,		0x001014f5 },		// write credits = 1/2 * read credits
+	{ &rAMC_MCUQOS,			0x00010f04 },		// RTG=4, RTY=15, enable pick-oldest-RTY
+	{ &rAMC_ADDRMAP_MODE,		0x00000002 },		// RIBI2 achieves much better performance for both linear and tiled mode frame buffers, and has better power profile as well
+	{ &rAMC_PWRMNGTPARAM,		0x03001000 },		// Use AiuReq to exiting self refresh state.
+
+	// Platform specific
+	
+	{ &rAMC_AIU_CHNLDEC2,		0x003FFFFD },		// The goal is randomize the channel in most cases to create a balanced distribution.
+	{ &rAMC_AIU_RDMAXCRD,		0x3012097f },		// RT:NRT:CPU:GFX = 48:18:09:MAX
+	{ &rAMC_AIU_RDREFL,		0x280f087f },		// 5/6 of AIURDMAXCRD fields
+	{ &rAMC_AIU_WRMAXCRD,		0x3012097f },		// RT:NRT:CPU:GFX = 48:18:09:MAX
+	{ &rAMC_AIU_WRREFL,		0x280f087f },		// 5/6 of AIUWRMAXCRD fields
+
+	{ &rAMC_AIU_ADDRBANKHASH0,	0x00006db6 },		// Enable bank hashing, bank[0] derived from bits 0,3,6,..
+	{ &rAMC_AIU_ADDRBANKHASH1,	0x00005b6d },		// Enable bank hashing, bank[1] derived from bits 1,4,7,..
+	{ &rAMC_AIU_ADDRBANKHASH2,	0x000036db },		// Enable bank hashing, bank[2] derived from bits 2,5,8,..
+	{ &rAMC_AIU_CHNLCRD,		0x00180018 },
+	{ &rAMC_AIU_LLTSCHCTL,		0x00000001 },		// Ensure LLT traffic from all ports is treated as medium priority request in the AIU arbitration
+	{ &rAMC_MCUQOSLLT,		0x00010108 },
+
+	{ &rAMC_AIU_CHNLTM,		0x40006101 },
+	{ &rAMC_AIU_WPQSCH,		0x08000800 },		// set starvation counts to 8
+	{ &rAMC_PSQRQCTL1,		0x0000132a },
+	{ &rAMC_PSQWQCTL0,		0x00010100 },		// enable write merging
+	{ &rAMC_PSQWQCTL1,		0x00000180 },		// ages write out faster than default (1/2 SelfRef)
+};
+#endif

platform/s5l8940x/include/platform/amgconfig.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+/*
+ * The amg_param struct is defined in drivers/apple/amg/amg.h, and this
+ * file should only by included from amg.c.
+ */
+
+#if WITH_TARGET_AMG_PARAMS
+// Default overrided by ipad2, j33, fpga
+#include <target/amgconfig.h>
+#else
+// Default shared by n94, k93a, n78
+static const struct amg_params amc_phy_params = {
+	.flags         = 0,
+	.core_config   = 0x00001053,
+	.read_latency  = 0x0000669b,
+	.gate_offset   = 0x08080808,
+};
+#endif

platform/s5l8940x/include/platform/ampconfig.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#if WITH_TARGET_AMP_PARAMS
+#include <target/ampconfig.h>
+#else
+static const struct amp_params amc_phy_params = {
+	.flags = (FLAG_AMP_PARAM_SUPPORT_FMCLK_OFF | FLAG_AMP_PARAM_FULLDIFFMODE),
+	.freq = {
+		{
+			.scl = 0x08,
+			.rdcapcfg = 0x00010308,
+		},
+		{
+			.scl = 0x0b,
+			.rdcapcfg = 0x00010306,
+		},
+		{
+			.scl = 0x28,
+			.rdcapcfg = 0x00010301,
+		},
+		{
+			.scl = 0x3f,
+			.rdcapcfg = 0x00010301,
+		},
+	},
+};
+#endif

platform/s5l8940x/include/platform/boot_pins.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_BOOT_PINS_H
+#define __PLATFORM_BOOT_PINS_H
+
+#include <platform.h>
+#include <platform/gpio.h>
+#include <sys/types.h>
+
+struct boot_interface_pin {
+	gpio_t	  pin;
+	u_int32_t enable;
+	u_int32_t disable;
+};
+
+#include SUB_PLATFORM_HEADER(boot_pins)
+
+#endif /* ! __PLATFORM_BOOT_PINS_H */

platform/s5l8940x/include/platform/boot_pins_s5l8940x.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_BOOT_PINS_S5L8940X_H
+#define __PLATFORM_BOOT_PINS_S5L8940X_H
+
+/*
+ *  boot_interface_pin tables
+ *    tables are executed in order for disable and reverse order for enable
+ *
+ */
+
+#if WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI
+static const struct boot_interface_pin spi0_boot_interface_pins[] =
+{
+#if SUPPORT_FPGA
+	{ GPIO(20, 5), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// SPI0_SSIN
+#else
+	{ GPIO(20, 5), GPIO_CFG_OUT_1, GPIO_CFG_IN },	// SPI0_SSIN
+#endif
+	{ GPIO(20, 2), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// SPI0_SCLK
+	{ GPIO(20, 3), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// SPI0_MOSI
+	{ GPIO(20, 4), GPIO_CFG_FUNC0, GPIO_CFG_IN }	// SPI0_MISO
+};
+
+static const struct boot_interface_pin spi3_boot_interface_pins[] =
+{
+#if SUPPORT_FPGA
+	{ GPIO(18, 7), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// SPI3_SSIN
+#else
+	{ GPIO(18, 7), GPIO_CFG_OUT_1, GPIO_CFG_IN },	// SPI3_SSIN
+#endif
+	{ GPIO(18, 6), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// SPI3_SCLK
+	{ GPIO(18, 4), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// SPI3_MOSI
+	{ GPIO(18, 5), GPIO_CFG_FUNC0, GPIO_CFG_IN }	// SPI3_MISO
+};
+#endif /* WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI */
+
+#if WITH_HW_BOOTROM_NAND
+
+/* Note: The code in init.c expects this table to begin with CS3 through CS0 */
+static const struct boot_interface_pin fmi0_boot_interface_pins[] =
+{
+	{ GPIO( 8, 0), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_CEN3
+	{ GPIO( 8, 1), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_CEN2
+	{ GPIO( 8, 2), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_CEN1
+	{ GPIO( 8, 3), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_CEN0
+	{ GPIO( 8, 4), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_CLE
+	{ GPIO( 8, 5), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_ALE
+	{ GPIO( 8, 6), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_REN
+	{ GPIO( 8, 7), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_WEN
+	{ GPIO(10, 0), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_IO0
+	{ GPIO( 9, 7), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_IO1
+	{ GPIO( 9, 6), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_IO2
+	{ GPIO( 9, 5), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_IO3
+	{ GPIO( 9, 3), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_IO4
+	{ GPIO( 9, 2), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_IO5
+	{ GPIO( 9, 1), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_IO6
+	{ GPIO( 9, 0), GPIO_CFG_FUNC0, GPIO_CFG_IN }	// FMI0_IO7
+};
+
+/* Note: The code in init.c expects this table to begin with CS3 through CS0 */
+static const struct boot_interface_pin fmi1_boot_interface_pins[] =
+{
+	{ GPIO(10, 1), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_CEN3
+	{ GPIO(10, 2), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_CEN2
+	{ GPIO(10, 3), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_CEN1
+	{ GPIO(10, 4), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_CEN0
+	{ GPIO(10, 5), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_CLE
+	{ GPIO(10, 6), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_ALE
+	{ GPIO(10, 7), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_REN
+	{ GPIO(11, 0), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_WEN
+	{ GPIO(12, 0), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_IO0
+	{ GPIO(12, 1), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_IO1
+	{ GPIO(11, 7), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_IO2
+	{ GPIO(11, 6), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_IO3
+	{ GPIO(11, 4), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_IO4
+	{ GPIO(11, 3), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_IO5
+	{ GPIO(11, 2), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_IO6
+	{ GPIO(11, 1), GPIO_CFG_FUNC0, GPIO_CFG_IN }	// FMI1_IO7
+};
+#endif /* WITH_HW_BOOTROM_NAND */
+
+#endif /* ! __PLATFORM_BOOT_PINS_S5L8940X_H */

platform/s5l8940x/include/platform/boot_pins_s5l8942x.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_BOOT_PINS_S5L8942X_H
+#define __PLATFORM_BOOT_PINS_S5L8942X_H
+
+/*
+ *  boot_interface_pin tables
+ *    tables are executed in order for disable and reverse order for enable
+ *
+ */
+
+#if WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI
+static const struct boot_interface_pin spi0_boot_interface_pins[] =
+{
+#if SUPPORT_FPGA
+	{ GPIO(12, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// SPI0_SSIN
+#else
+	{ GPIO(12, 3), GPIO_CFG_OUT_1, GPIO_CFG_DFLT },	// SPI0_SSIN
+#endif
+	{ GPIO(12, 0), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// SPI0_SCLK
+	{ GPIO(12, 1), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// SPI0_MOSI
+	{ GPIO(12, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT }	// SPI0_MISO
+};
+
+static const struct boot_interface_pin spi3_boot_interface_pins[] =
+{
+#if SUPPORT_FPGA
+	{ GPIO(16, 3), GPIO_CFG_FUNC1, GPIO_CFG_DFLT },	// SPI3_SSIN
+#else
+	{ GPIO(16, 3), GPIO_CFG_OUT_1, GPIO_CFG_DFLT },	// SPI3_SSIN
+#endif
+	{ GPIO(16, 0), GPIO_CFG_FUNC1, GPIO_CFG_DFLT },	// SPI3_SCLK
+	{ GPIO(16, 1), GPIO_CFG_FUNC1, GPIO_CFG_DFLT },	// SPI3_MOSI
+	{ GPIO(16, 2), GPIO_CFG_FUNC1, GPIO_CFG_DFLT }	// SPI3_MISO
+};
+#endif /* WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI */
+
+#if WITH_HW_BOOTROM_NAND
+
+/* Note: The code in init.c expects this table to begin with CS3 through CS0 */
+static const struct boot_interface_pin fmi0_boot_interface_pins[] =
+{
+	{ GPIO(17, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_CEN3
+	{ GPIO(17, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_CEN2
+	{ GPIO(17, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_CEN1
+	{ GPIO(17, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_CEN0
+	{ GPIO(17, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_CLE
+	{ GPIO(17, 7), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_ALE
+	{ GPIO(18, 0), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_REN
+	{ GPIO(18, 1), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_WEN
+	{ GPIO(20, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO0
+	{ GPIO(20, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO1
+	{ GPIO(20, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO2
+	{ GPIO(20, 1), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO3
+	{ GPIO(18, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO4
+	{ GPIO(18, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO5
+	{ GPIO(18, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO6
+	{ GPIO(18, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT }	// FMI0_IO7
+};
+
+/* Note: The code in init.c expects this table to begin with CS3 through CS0 */
+static const struct boot_interface_pin fmi1_boot_interface_pins[] =
+{
+	{ GPIO(20, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_CEN3
+	{ GPIO(20, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_CEN2
+	{ GPIO(20, 7), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_CEN1
+	{ GPIO(21, 0), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_CEN0
+	{ GPIO(21, 1), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_CLE
+	{ GPIO(21, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_ALE
+	{ GPIO(21, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_REN
+	{ GPIO(21, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_WEN
+	{ GPIO(22, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO0
+	{ GPIO(22, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO1
+	{ GPIO(22, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO2
+	{ GPIO(22, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO3
+	{ GPIO(22, 0), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO4
+	{ GPIO(21, 7), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO5
+	{ GPIO(21, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO6
+	{ GPIO(21, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT }	// FMI1_IO7
+};
+#endif /* WITH_HW_BOOTROM_NAND */
+
+#endif /* ! __PLATFORM_BOOT_PINS_S5L8942X_H */

platform/s5l8940x/include/platform/boot_pins_s5l8947x.h

@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_BOOT_PINS_S5L8947X_H
+#define __PLATFORM_BOOT_PINS_S5L8947X_H
+
+/*
+ *  boot_interface_pin tables
+ *    tables are executed in order for disable and reverse order for enable
+ *
+ */
+
+#if WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI
+static const struct boot_interface_pin spi0_boot_interface_pins[] =
+{
+#if SUPPORT_FPGA
+	{ GPIO(17, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// SPI0_SSIN
+#else
+	{ GPIO(17, 3), GPIO_CFG_OUT_1, GPIO_CFG_DFLT },	// SPI0_SSIN
+#endif
+	{ GPIO(17, 0), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// SPI0_SCLK
+	{ GPIO(17, 1), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// SPI0_MOSI
+	{ GPIO(17, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT }	// SPI0_MISO
+};
+#endif /* WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI */
+
+#if WITH_HW_BOOTROM_NAND
+
+/* Note: The code in init.c expects this table to begin with CS3 through CS0 */
+static const struct boot_interface_pin fmi0_boot_interface_pins[] =
+{
+	{ GPIO( 5, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_CEN1
+	{ GPIO( 5, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_CEN0
+	{ GPIO( 5, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_CLE
+	{ GPIO( 5, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_ALE
+	{ GPIO( 5, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_REN
+	{ GPIO( 5, 7), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_WEN
+	{ GPIO( 7, 0), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO0
+	{ GPIO( 6, 7), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO1
+	{ GPIO( 6, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO2
+	{ GPIO( 6, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO3
+	{ GPIO( 6, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO4
+	{ GPIO( 6, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO5
+	{ GPIO( 6, 1), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO6
+	{ GPIO( 6, 0), GPIO_CFG_FUNC0, GPIO_CFG_DFLT }	// FMI0_IO7
+};
+
+/* Note: The code in init.c expects this table to begin with CS3 through CS0 */
+static const struct boot_interface_pin fmi1_boot_interface_pins[] =
+{
+	{ GPIO( 7, 1), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_CEN1
+	{ GPIO( 7, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_CEN0
+	{ GPIO( 7, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_CLE
+	{ GPIO( 7, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_ALE
+	{ GPIO( 7, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_REN
+	{ GPIO( 7, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_WEN
+	{ GPIO( 8, 7), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO0
+	{ GPIO( 8, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO1
+	{ GPIO( 8, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO2
+	{ GPIO( 8, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO3
+	{ GPIO( 8, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO4
+	{ GPIO( 8, 1), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO5
+	{ GPIO( 8, 0), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO6
+	{ GPIO( 7, 7), GPIO_CFG_FUNC0, GPIO_CFG_DFLT }	// FMI1_IO7
+};
+#endif /* WITH_HW_BOOTROM_NAND */
+
+#endif /* ! __PLATFORM_BOOT_PINS_S5L8947X_H */

platform/s5l8940x/include/platform/gpiodef.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_GPIODEF_H
+#define __PLATFORM_GPIODEF_H
+
+/* S5L8940X specific gpio -> pin mappings */
+
+#include <platform.h>
+#include <platform/gpio.h>
+#include <platform/soc/hwregbase.h>
+
+#if WITH_TARGET_CONFIG
+# include <target/gpiodef.h>
+#endif
+
+#include SUB_PLATFORM_HEADER(gpiodef)
+
+#endif /* ! __PLATFORM_GPIODEF_H */

platform/s5l8940x/include/platform/gpiodef_s5l8940x.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2011-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_GPIODEF_S5L8940X_H
+#define __PLATFORM_GPIODEF_S5L8940X_H
+
+/* S5L8940X specific gpio -> pin mappings */
+
+#if !SUB_PLATFORM_S5L8940X
+#error "Only include for S5L8940X platform"
+#endif
+
+/* define platform-specific gpios in a generic fashion here. */
+#define GPIO_IIC0_SCL		GPIO(21, 3)
+#define GPIO_IIC0_SDA		GPIO(21, 2)
+#define GPIO_IIC1_SCL		GPIO(21, 5)
+#define GPIO_IIC1_SDA		GPIO(21, 4)
+#define GPIO_IIC2_SCL		GPIO(20, 1)
+#define GPIO_IIC2_SDA		GPIO(20, 0)
+
+#define GPIO_BOARD_ID0		GPIO(20, 2)
+#define GPIO_BOARD_ID1		GPIO(20, 3)
+#define GPIO_BOARD_ID2		GPIO(20, 4)
+#define GPIO_BOARD_ID3		GPIO( 2, 0)
+
+#define GPIO_BOOT_CONFIG0	GPIO( 2, 2)
+#define GPIO_BOOT_CONFIG1	GPIO( 3, 1)
+#define GPIO_BOOT_CONFIG2	GPIO( 3, 4)
+#define GPIO_BOOT_CONFIG3	GPIO( 3, 5)
+
+#define GPIO_REQUEST_DFU1	GPIO( 0, 1)	// formerly known as HOLD_KEY
+#define GPIO_REQUEST_DFU2	GPIO( 0, 0)	// formerly known as MENU_KEY
+#define GPIO_FORCE_DFU		GPIO( 3, 2)
+#define GPIO_DFU_STATUS		GPIO( 3, 3)
+
+#define SPI_NOR0		(0)
+#define SPI_NOR3		(3)
+
+#if SUPPORT_FPGA
+#define GPIO_SPI0_CS		GPIO(GPIO_PAD_SPI, 0)
+#define GPIO_SPI3_CS		GPIO(GPIO_PAD_SPI, 3)
+#else
+#define GPIO_SPI0_CS		GPIO(20, 5)
+#define GPIO_SPI3_CS		GPIO(18, 7)
+#endif
+
+#define GPIO_UART1_TXD		GPIO( 5, 3)
+
+#define GPIO_SYSTEM_RESET	GPIO(28, 0)
+
+#endif /* ! __PLATFORM_GPIODEF_S5L8940X_H */

platform/s5l8940x/include/platform/gpiodef_s5l8942x.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2011-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_GPIODEF_S5L8942X_H
+#define __PLATFORM_GPIODEF_S5L8942X_H
+
+/* S5L8942X specific gpio -> pin mappings */
+
+#if !SUB_PLATFORM_S5L8942X
+#error "Only include for S5L8942X platform"
+#endif
+
+/* define platform-specific gpios in a generic fashion here. */
+#define GPIO_IIC0_SCL		GPIO( 6, 5)
+#define GPIO_IIC0_SDA		GPIO( 6, 4)
+#define GPIO_IIC1_SCL		GPIO( 6, 7)
+#define GPIO_IIC1_SDA		GPIO( 6, 6)
+#define GPIO_IIC2_SCL		GPIO(24, 1)
+#define GPIO_IIC2_SDA		GPIO(24, 0)
+
+#define GPIO_BOARD_ID0		GPIO(12, 0)
+#define GPIO_BOARD_ID1		GPIO(12, 1)
+#define GPIO_BOARD_ID2		GPIO(12, 2)
+#define GPIO_BOARD_ID3		GPIO( 2, 0)
+
+#define GPIO_BOOT_CONFIG0	GPIO( 2, 2)
+#define GPIO_BOOT_CONFIG1	GPIO( 3, 1)
+#define GPIO_BOOT_CONFIG2	GPIO( 3, 4)
+#define GPIO_BOOT_CONFIG3	GPIO( 3, 5)
+
+#define GPIO_REQUEST_DFU1	GPIO( 0, 1)	// formerly known as HOLD_KEY
+#define GPIO_REQUEST_DFU2	GPIO( 0, 0)	// formerly known as MENU_KEY
+#define GPIO_FORCE_DFU		GPIO( 3, 2)
+#define GPIO_DFU_STATUS		GPIO( 3, 3)
+
+#define SPI_NOR0		(0)
+#define SPI_NOR3		(3)
+
+#if SUPPORT_FPGA
+#define GPIO_SPI0_CS		GPIO(GPIO_PAD_SPI, 0)
+#define GPIO_SPI3_CS		GPIO(GPIO_PAD_SPI, 3)
+#else
+#define GPIO_SPI0_CS		GPIO(12, 3)
+#define GPIO_SPI3_CS		GPIO(16, 3)
+#endif
+
+#define GPIO_UART1_TXD		GPIO( 5, 0)
+
+#define GPIO_SYSTEM_RESET	GPIO(25, 0)
+
+#endif /* ! __PLATFORM_GPIODEF_S5L8942X_H */

platform/s5l8940x/include/platform/gpiodef_s5l8947x.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2011-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_GPIODEF_S5L8947X_H
+#define __PLATFORM_GPIODEF_S5L8947X_H
+
+/* S5L8947X specific gpio -> pin mappings */
+
+#if !SUB_PLATFORM_S5L8947X
+#error "Only include for S5L8947X platform"
+#endif
+
+/* define platform-specific gpios in a generic fashion here. */
+#define GPIO_IIC0_SCL		GPIO(17, 1)
+#define GPIO_IIC0_SDA		GPIO(17, 0)
+#define GPIO_IIC1_SCL		GPIO( 1, 2)
+#define GPIO_IIC1_SDA		GPIO( 1, 1)
+#define GPIO_IIC2_SCL		GPIO( 1, 6)
+#define GPIO_IIC2_SDA		GPIO( 1, 5)
+
+#define GPIO_BOARD_ID0		GPIO(17, 3)
+#define GPIO_BOARD_ID1		GPIO(17, 4)
+#define GPIO_BOARD_ID2		GPIO(17, 5)
+#define GPIO_BOARD_ID3		GPIO(14, 0)
+
+#define GPIO_BOOT_CONFIG0	GPIO(14, 2)
+#define GPIO_BOOT_CONFIG1	GPIO(16, 3)
+#define GPIO_BOOT_CONFIG2	GPIO(16, 6)
+#define GPIO_BOOT_CONFIG3	GPIO(16, 7)
+
+#define GPIO_REQUEST_DFU1	GPIO(12, 1)	// formerly known as HOLD_KEY
+#define GPIO_REQUEST_DFU2	GPIO(12, 0)	// formerly known as MENU_KEY
+#define GPIO_FORCE_DFU		GPIO(16, 4)
+#define GPIO_DFU_STATUS		GPIO(16, 5)
+
+#define SPI_NOR0		(0)
+
+#if SUPPORT_FPGA
+#define GPIO_SPI0_CS		GPIO(GPIO_PAD_SPI, 0)
+#else
+#define GPIO_SPI0_CS		GPIO(17, 3)
+#endif
+
+#define GPIO_UART1_TXD		GPIO( 0, 7)
+
+#define GPIO_SYSTEM_RESET	GPIO( 3, 4)
+
+#endif /* ! __PLATFORM_GPIODEF_S5L8947X_H */

platform/s5l8940x/include/platform/image_devices.h

@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2009 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_IMAGE_DEVICES_H
+#define __PLATFORM_IMAGE_DEVICES_H
+
+static const struct image_device platform_image_devices[] = {
+#if defined(WITH_NAND_BOOT)
+    { "nand_firmware", 0x00000 }
+#else    
+    { "nor0", 0x00000 }
+#endif
+};
+
+#if WITH_SYSCFG
+static const struct image_device platform_syscfg_devices[] = {
+#if defined(WITH_NAND_BOOT)
+       { "nand_syscfg", 0x00000 }
+#else
+       { "nor0", 0x00000 }
+#endif
+};
+#endif /* WITH_SYSCFG */
+
+#endif /* ! __PLATFORM_IMAGE_DEVICES_H */

platform/s5l8940x/include/platform/memconfig.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2009 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_MEMCONFIG_H
+#define __PLATFORM_MEMCONFIG_H
+
+/* S5L8940X SoC Mem Pin Configuration */
+
+static const gpio_t memory_interface_gpios[] = {
+	/* Not needed */
+};
+#endif /* ! __PLATFORM_MEMCONFIG_H */

platform/s5l8940x/include/platform/memmap.h

@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2009-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_MEMMAP_H
+#define __PLATFORM_MEMMAP_H
+
+#include <platform/memmap_defaults.h>
+
+/*
+ * 0xa0000000	SDRAM_END
+ * 0x9fffc000	PANIC_BASE
+ * 0x9ff00000	IBOOT_BASE
+ * 0x9f000000	DISPLAY_BASE
+ * 0x9e800000	MONITOR_BASE
+ */
+/* S5L8940X specific memory map */
+#define SDRAM_BASE			(0x80000000ULL)
+#define SDRAM_BANK_LEN			(0x10000000ULL)
+#define SDRAM_BANK_COUNT		(2)
+#define SDRAM_END			(SDRAM_BASE + (SDRAM_BANK_LEN * SDRAM_BANK_COUNT))
+#define VROM_BASE			(0x3F000000ULL)
+#define VROM_BANK_LEN			(0x00100000ULL)
+#define VROM_LEN			(0x00010000ULL)
+#define SRAM_BASE			(0x34000000ULL)
+#define SRAM_BANK_LEN			(0x00100000ULL)
+#define SRAM_LEN			(0x00040000ULL)
+
+/* Sleep token is stored at first physical page in kernel memory */
+#define SLEEP_TOKEN_BUFFER_BASE		(SDRAM_BASE)
+
+/* reserved area for panic info */
+#define PANIC_SIZE		(0x00004000ULL)
+#define PANIC_BASE		(SDRAM_END - PANIC_SIZE)
+
+/* reserved area for iBoot */
+#define IBOOT_SIZE		(0x00100000 - PANIC_SIZE)
+#define IBOOT_BASE		(PANIC_BASE - IBOOT_SIZE)
+#define PROTECTED_REGION_SIZE	IBOOT_SIZE
+
+/* reserved area for display */
+#ifndef DISPLAY_SIZE
+#define DISPLAY_SIZE		(0x00F00000ULL)
+#endif
+#define DISPLAY_BASE		(IBOOT_BASE - DISPLAY_SIZE)
+
+/* where to load the monitor/hypervisor */
+#ifdef HACK_MONITOR
+#define MONITOR_SIZE		(0x00800000ULL)
+#else  /* !defined(HACK_MONITOR) */
+#define MONITOR_SIZE		(0)
+#endif /* defined(HACK_MONITOR) */
+#define MONITOR_BASE		(DISPLAY_BASE - MONITOR_SIZE)
+
+/* where to stick the mmu tt, default heap and insecure memory*/
+#if APPLICATION_SECUREROM
+#define MMU_TT_SIZE		(0x4000ULL)
+#define MMU_TT_BASE		(SRAM_BASE + SRAM_LEN - MMU_TT_SIZE)
+#define MMU_NONCACHE0_SIZE	(SRAM_BANK_LEN)
+#define MMU_NONCACHE0_PBASE	(SRAM_BASE)
+#define MMU_NONCACHE0_VBASE	(SRAM_BASE + SRAM_BANK_LEN * 3)
+
+#define STACK_SIZE		(0x3000ULL)
+#define STACK_BASE		(MMU_TT_BASE - STACK_SIZE)
+
+#define HEAP_END		(STACK_BASE)
+
+#ifndef __ASSEMBLY__
+
+#define INSECURE_MEMORY_BASE	(SRAM_BASE)
+#define INSECURE_MEMORY_SIZE	((uintptr_t)__segment_start(__DATA) - INSECURE_MEMORY_BASE)
+
+#endif /* ! __ASSEMBLY__ */
+
+#endif /* APPLICATION_SECUREROM */
+
+#if APPLICATION_IBOOT
+#define MMU_TT_SIZE		(0x4000ULL)
+#define MMU_TT_BASE		(TEXT_BASE + TEXT_FOOTPRINT - MMU_TT_SIZE)
+#define MMU_NONCACHE0_SIZE	(SRAM_BANK_LEN)
+#define MMU_NONCACHE0_PBASE	(SRAM_BASE)
+#define MMU_NONCACHE0_VBASE	(SRAM_BASE + SRAM_BANK_LEN * 3)
+#define MMU_NONCACHE1_SIZE	(0x40000000ULL)
+#define MMU_NONCACHE1_PBASE	(0x80000000ULL)
+#define MMU_NONCACHE1_VBASE	(0xC0000000ULL)
+
+#if WITH_DFU_MODE
+#define STACK_SIZE		(0x3000ULL)
+
+#define INSECURE_MEMORY_SIZE	(0x00200000ULL)
+#define INSECURE_MEMORY_BASE	(SDRAM_BASE + SDRAM_BANK_LEN - INSECURE_MEMORY_SIZE)
+
+#define HEAP_EXT_SIZE		(0x00100000ULL)
+#define HEAP_EXT_BASE		(INSECURE_MEMORY_BASE - HEAP_EXT_SIZE)
+
+#else /* !WITH_DFU_MODE */
+#define STACK_SIZE		(0x1000ULL)
+
+#define INSECURE_MEMORY_BASE	(SDRAM_BASE)
+#define INSECURE_MEMORY_SIZE	(DEFAULT_KERNEL_ADDRESS - SDRAM_BASE)
+
+#define SECURE_MEMORY_BASE	(INSECURE_MEMORY_BASE + INSECURE_MEMORY_SIZE)
+/* If only 1 bank is populated, this only clears to the alias of
+ * DISPLAY_BASE in the first bank. If 2 banks are populated, this
+ * clears all the was to DISPLAY_BASE in the second bank. */
+#define SECURE_MEMORY_SIZE	(DISPLAY_BASE - SECURE_MEMORY_BASE - SDRAM_BANK_LEN * 2 + platform_get_memory_size())
+
+#define HEAP_EXT_BASE		(DEFAULT_FREE_ADDRESS)
+#define HEAP_EXT_SIZE		(MONITOR_BASE - SDRAM_BANK_LEN - HEAP_EXT_BASE)
+#endif /* !WITH_DFU_MODE */
+
+#define STACK_BASE		(MMU_TT_BASE - STACK_SIZE)
+
+#define HEAP_END		(STACK_BASE)
+
+#endif /* APPLICATION_IBOOT */
+
+#if APPLICATION_EMBEDDEDIOP
+# if ARCH_ARMv7
+#  define MMU_TT_SIZE		(0x4000ULL)
+# endif
+
+#define AUDIO_SRAM_RESERVE	(0x1000ULL)
+#define USB_SRAM_RESERVE	(0x10000ULL)
+
+#if TARGET_S5L8940XAE2
+#define HEAP_EXT_BASE		(SRAM_BASE + AUDIO_SRAM_RESERVE)
+#define HEAP_EXT_SIZE		(SRAM_LEN - AUDIO_SRAM_RESERVE - USB_SRAM_RESERVE)
+#endif /* TARGET_S5L8940XAE2 */
+
+
+#endif /* !APPLICATION_EMBEDDEDIOP */
+
+#define SCRATCH_BASE     (0x33600000ULL)
+#define SCRATCH_LEN      (2048)
+
+#endif /* ! __PLATFORM_MEMMAP_H */

platform/s5l8940x/include/platform/pinconfig_s5l8940x.h

@@ -0,0 +1,310 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_PINCONFIG_S5L8940X_H
+#define __PLATFORM_PINCONFIG_S5L8940X_H
+
+/* Default S5L8940X SoC Pin Configuration */
+
+#define FMI_DRIVE_STR	DRIVE_X3
+
+static const u_int32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
+/* Port  0 */
+	CFG_IN,								// GPIO0		-> MENU_KEY
+	CFG_IN,								// GPIO1		-> HOLD_KEY
+	CFG_DISABLED,							// GPIO2		->
+	CFG_DISABLED,							// GPIO3		->
+	CFG_DISABLED,							// GPIO4		->
+	CFG_DISABLED | PULL_DOWN,					// GPIO5		->
+	CFG_DISABLED,							// GPIO6		->
+	CFG_DISABLED | PULL_DOWN,					// GPIO7		->
+
+/* Port  1 */
+	CFG_DISABLED,							// GPIO8		->
+	CFG_DISABLED,							// GPIO9		->
+	CFG_DISABLED,							// GPIO10		->
+	CFG_DISABLED,							// GPIO11		->
+	CFG_DISABLED,							// GPIO12		->
+	CFG_DISABLED,							// GPIO13		->
+	CFG_DISABLED,							// GPIO14		->
+	CFG_DISABLED,							// GPIO15		->
+
+/* Port  2 */
+	CFG_DISABLED,							// GPIO16		-> BOARD_ID[3]
+	CFG_DISABLED,							// GPIO17		->
+	CFG_DISABLED,							// GPIO18		-> BOOT_CONFIG[0]
+	CFG_DISABLED | PULL_DOWN,					// GPIO19		->
+	CFG_DISABLED,							// GPIO20		->
+	CFG_DISABLED,							// GPIO21		->
+	CFG_DISABLED | PULL_DOWN,					// GPIO22		->
+	CFG_DISABLED,							// GPIO23		->
+
+/* Port  3 */
+	CFG_DISABLED | PULL_DOWN,					// GPIO24		->
+	CFG_DISABLED,							// GPIO25		-> BOOT_CONFIG[1]
+	CFG_IN | PULL_DOWN,						// GPIO26		-> FORCE_DFU
+	CFG_DISABLED | PULL_DOWN,					// GPIO27		-> DFU_STATUS
+	CFG_DISABLED,							// GPIO28		-> BOOT_CONFIG[2]
+	CFG_DISABLED,							// GPIO29		-> BOOT_CONFIG[3]
+	CFG_DISABLED,							// GPIO30		->
+	CFG_DISABLED,							// GPIO31		->
+
+/* Port  4 */
+	CFG_DISABLED,							// GPIO32		->
+	CFG_DISABLED,							// GPIO33		->
+	CFG_DISABLED,							// GPIO34		->
+	CFG_DISABLED,							// GPIO35		->
+	CFG_DISABLED,							// GPIO36		->
+	CFG_DISABLED,							// GPIO37		->
+	CFG_DISABLED,							// GPIO38		->
+	CFG_DISABLED,							// GPIO39		->
+
+/* Port  5 */
+	CFG_DISABLED,							// EHCI_PORT_PWR[0]	->
+	CFG_DISABLED,							// EHCI_PORT_PWR[1]	->
+	CFG_DISABLED,							// EHCI_PORT_PWR[2]	->
+	CFG_DISABLED,							// UART1_TXD		->
+	CFG_DISABLED,							// UART1_RXD		->
+	CFG_DISABLED,							// UART1_RTSN		->
+	CFG_DISABLED,							// UART1_CTSN		->
+	CFG_DISABLED,							// UART2_TXD		->
+
+/* Port  6 */
+	CFG_DISABLED,							// UART2_RXD		->
+	CFG_DISABLED,							// UART2_RTSN		->
+	CFG_DISABLED,							// UART2_CTSN		->
+	CFG_DISABLED,							// UART3_TXD		->
+	CFG_DISABLED,							// UART3_RXD		->
+	CFG_DISABLED,							// UART3_RTSN		->
+	CFG_DISABLED,							// UART3_CTSN		->
+	CFG_DISABLED,							// UART5_RTXD		->
+
+/* Port  7 */
+	CFG_DISABLED,							// UART6_TXD		->
+	CFG_DISABLED,							// UART6_RXD		->
+	CFG_DISABLED,							// UART6_RTSN		->
+	CFG_DISABLED,							// UART6_CTSN		->
+	CFG_DISABLED,							// UART4_TXD/SPI4_MOSI	->
+	CFG_DISABLED,							// UART4_RXD/SPI4_MISO	->
+	CFG_DISABLED,							// UART4_RTSN/SPI4_SCLK	->
+	CFG_DISABLED,							// UART4_CTSN/SPI4_SSIN	->
+
+/* Port  8 */
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN3		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN2		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN1		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_WEN		->
+
+/* Port  9 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO5		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO4		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO2		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO1		->
+
+/* Port 10 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO0		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN3		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN2		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN1		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_REN		->
+
+/* Port 11 */
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO5		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO4		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO2		->
+
+/* Port 12 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO1		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO0		->
+	CFG_DISABLED,							// FMI2_CEN3		->
+	CFG_DISABLED,							// FMI2_CEN2		->
+	CFG_DISABLED,							// FMI2_CEN1		->
+	CFG_DISABLED,							// FMI2_CEN0		->
+	CFG_DISABLED,							// FMI2_CLE		->
+	CFG_DISABLED,							// FMI2_ALE		->
+
+/* Port 13 */
+	CFG_DISABLED,							// FMI2_REN		->
+	CFG_DISABLED,							// FMI2_WEN		->
+	CFG_DISABLED,							// FMI2_IO7		->
+	CFG_DISABLED,							// FMI2_IO6		->
+	CFG_DISABLED,							// FMI2_IO5		->
+	CFG_DISABLED,							// FMI2_IO4		->
+	CFG_DISABLED,							// FMI2_DQS		->
+	CFG_DISABLED,							// FMI2_IO3		->
+
+/* Port 14 */
+	CFG_DISABLED,							// FMI2_IO2		->
+	CFG_DISABLED,							// FMI2_IO1		->
+	CFG_DISABLED,							// FMI2_IO0		->
+	CFG_DISABLED,							// FMI0_CEN7		->
+	CFG_DISABLED,							// FMI0_CEN6		->
+	CFG_DISABLED,							// FMI0_CEN5		->
+	CFG_DISABLED,							// FMI0_CEN4		->
+	CFG_DISABLED,							// FMI1_CEN7		->
+
+/* Port 15 */
+	CFG_DISABLED,							// FMI1_CEN6		->
+	CFG_DISABLED,							// FMI1_CEN5		->
+	CFG_DISABLED,							// FMI1_CEN4		->
+	CFG_DISABLED,							// FMI3_CEN3		->
+	CFG_DISABLED,							// FMI3_CEN2		->
+	CFG_DISABLED,							// FMI3_CEN1		->
+	CFG_DISABLED,							// FMI3_CEN0		->
+	CFG_DISABLED,							// FMI3_CLE		->
+
+/* Port 16 */
+	CFG_DISABLED,							// FMI3_ALE		->
+	CFG_DISABLED,							// FMI3_REN		->
+	CFG_DISABLED,							// FMI3_WEN		->
+	CFG_DISABLED,							// FMI3_IO7		->
+	CFG_DISABLED,							// FMI3_IO6		->
+	CFG_DISABLED,							// FMI3_IO5		->
+	CFG_DISABLED,							// FMI3_IO4		->
+	CFG_DISABLED,							// FMI3_DQS		->
+
+/* Port 17 */
+	CFG_DISABLED,							// FMI3_IO3		->
+	CFG_DISABLED,							// FMI3_IO2		->
+	CFG_DISABLED,							// FMI3_IO1		->
+	CFG_DISABLED,							// FMI3_IO0		->
+	CFG_DISABLED,							// FMI2_CEN7		->
+	CFG_DISABLED,							// FMI2_CEN6		->
+	CFG_DISABLED,							// FMI2_CEN5		->
+	CFG_DISABLED,							// FMI2_CEN4		->
+
+/* Port 18 */
+	CFG_DISABLED,							// FMI3_CEN7		->
+	CFG_DISABLED,							// FMI3_CEN6		->
+	CFG_DISABLED,							// FMI3_CEN5		->
+	CFG_DISABLED,							// FMI3_CEN4		->
+	CFG_DISABLED,							// SPI3_MOSI		-> 
+	CFG_DISABLED,							// SPI3_MISO		-> 
+	CFG_DISABLED,							// SPI3_SCLK		-> 
+	CFG_DISABLED,							// SPI3_SSIN		-> 
+
+/* Port 19 */
+	CFG_DISABLED,							// ISP0_PRE_FLASH	->
+	CFG_DISABLED,							// ISP0_FLASH		->
+	CFG_DISABLED,							// ISP1_PRE_FLASH	->
+	CFG_DISABLED,							// ISP1_FLASH		->
+	CFG_DISABLED,							// SPI1_SCLK		->
+	CFG_DISABLED,							// SPI1_MOSI		->
+	CFG_DISABLED,							// SPI1_MISO		->
+	CFG_DISABLED,							// SPI1_SSIN		->
+
+/* Port 20 */
+	CFG_DISABLED,							// I2C2_SDA		->
+	CFG_DISABLED,							// I2C2_SCL		->
+	CFG_DISABLED,							// SPI0_SCLK		-> SPI0_SCLK/BOARD_ID[0]
+	CFG_DISABLED,							// SPI0_MOSI		-> SPI0_MOSI/BOARD_ID[1]
+	CFG_DISABLED,							// SPI0_MISO		-> SPI0_MISO/BOARD_ID[2]
+	CFG_DISABLED | PULL_UP,						// SPI0_SSIN		-> SPI0_SSIN
+	CFG_DISABLED,							// SPI2_SCLK		->
+	CFG_DISABLED,							// SPI2_MOSI		->
+
+/* Port 21 */
+	CFG_DISABLED,							// SPI2_MISO		->
+	CFG_DISABLED,							// SPI2_SSIN		->
+	CFG_DISABLED,							// I2C0_SDA		->
+	CFG_DISABLED,							// I2C0_SCL		->
+	CFG_DISABLED,							// I2C1_SDA		->
+	CFG_DISABLED,							// I2C1_SCL		->
+	CFG_DISABLED,							// ISP0_SDA		->
+	CFG_DISABLED,							// ISP0_SCL		->
+
+/* Port 22 */
+	CFG_DISABLED,							// ISP1_SDA		->
+	CFG_DISABLED,							// ISP1_SCL		->
+	CFG_DISABLED,							// SDIO_CLK		->
+	CFG_DISABLED,							// SDIO_CMD		->
+	CFG_DISABLED,							// SDIO_DATA0		->
+	CFG_DISABLED,							// SDIO_DATA1		->
+	CFG_DISABLED,							// SDIO_DATA2		->
+	CFG_DISABLED,							// SDIO_DATA3		->
+
+/* Port 23 */
+	CFG_DISABLED,							// MIPI_VSYNC		->
+	CFG_DISABLED,							// TMR32_PWM0		->
+	CFG_DISABLED,							// TMR32_PWM1		->
+	CFG_DISABLED,							// TMR32_PWM2		->
+	CFG_DISABLED,							// SWI_DATA		->
+	CFG_DISABLED,							// DWI_DI		->
+	CFG_DISABLED,							// DWI_DO		->
+	CFG_DISABLED,							// DWI_CLK		->
+
+/* Port 24 */
+	CFG_DISABLED,							// SENSOR0_RST		->
+	CFG_DISABLED,							// SENSOR0_CLK		->
+	CFG_DISABLED,							// SENSOR1_RST		->
+	CFG_DISABLED,							// SENSOR1_CLK		->
+	CFG_DISABLED,							// I2S0_MCK		->
+	CFG_DISABLED,							// I2S0_LRCK		->
+	CFG_DISABLED,							// I2S0_BCLK		->
+	CFG_DISABLED,							// I2S0_DOUT		->
+
+/* Port 25 */
+	CFG_DISABLED,							// I2S0_DIN		->
+	CFG_DISABLED,							// I2S1_MCK		->
+	CFG_DISABLED,							// I2S1_LRCK		->
+	CFG_DISABLED,							// I2S1_BCLK		->
+	CFG_DISABLED,							// I2S1_DOUT		->
+	CFG_DISABLED,							// I2S1_DIN		->
+	CFG_DISABLED,							// I2S2_MCK		->
+	CFG_DISABLED,							// I2S2_LRCK		->
+
+/* Port 26 */
+	CFG_DISABLED,							// I2S2_BCLK		->
+	CFG_DISABLED,							// I2S2_DOUT		->
+	CFG_DISABLED,							// I2S2_DIN		->
+	CFG_DISABLED,							// I2S3_MCK		->
+	CFG_DISABLED,							// I2S3_LRCK		->
+	CFG_DISABLED,							// I2S3_BCLK		->
+	CFG_DISABLED,							// I2S3_DOUT		->
+	CFG_DISABLED,							// I2S3_DIN		->
+
+/* Port 27 */
+	CFG_DISABLED,							// SPDIF		->
+	CFG_DISABLED | PULL_DOWN,					// GPIO217		->
+	CFG_DISABLED,							// GPIO218		->
+	CFG_DISABLED,							// DP_HPD		->
+	CFG_DISABLED,							// UART0_TXD		->
+	CFG_DISABLED,							// UART0_RXD		->
+	CFG_DISABLED,							// TST_CLKOUT		->
+	CFG_DISABLED,							// TST_STPCLK		->
+
+/* Port 28 */
+	CFG_DISABLED,							// WDOG			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+};
+
+#endif /* ! __PLATFORM_PINCONFIG_S5L8940X_H */

platform/s5l8940x/include/platform/pinconfig_s5l8942x.h

@@ -0,0 +1,281 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_PINCONFIG_S5L8942X_H
+#define __PLATFORM_PINCONFIG_S5L8942X_H
+
+/* Default S5L8942X SoC Pin Configuration */
+
+#define FMI_DRIVE_STR	DRIVE_X2
+#define FMI_SLEW_RATE	SLEW_RATE_SLOW
+
+static const u_int32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
+/* Port  0 */
+	CFG_IN,								// GPIO0		-> MENU_KEY
+	CFG_IN,								// GPIO1		-> HOLD_KEY
+	CFG_DISABLED,							// GPIO2		->
+	CFG_DISABLED,							// GPIO3		->
+	CFG_DISABLED,							// GPIO4		->
+	CFG_DISABLED,							// GPIO5		->
+	CFG_DISABLED,							// GPIO6		->
+	CFG_DISABLED,							// GPIO7		->
+
+/* Port  1 */
+	CFG_DISABLED,							// GPIO8		->
+	CFG_DISABLED,							// GPIO9		->
+	CFG_DISABLED,							// GPIO10		->
+	CFG_DISABLED,							// GPIO11		->
+	CFG_DISABLED,							// GPIO12		->
+	CFG_DISABLED,							// GPIO13		->
+	CFG_DISABLED,							// GPIO14		->
+	CFG_DISABLED,							// GPIO15		->
+
+/* Port  2 */
+	CFG_DISABLED,							// GPIO16		-> BOARD_ID[3]
+	CFG_DISABLED,							// GPIO17		->
+	CFG_DISABLED,							// GPIO18		-> BOOT_CONFIG[0]
+	CFG_DISABLED,							// GPIO19		-> KEEPACT
+	CFG_DISABLED,							// GPIO20		->
+	CFG_DISABLED,							// GPIO21		->
+	CFG_DISABLED,							// GPIO22		->
+	CFG_DISABLED,							// GPIO23		->
+
+/* Port  3 */
+	CFG_DISABLED,							// GPIO24		->
+	CFG_DISABLED,							// GPIO25		-> BOOT_CONFIG[1]
+	CFG_IN | PULL_DOWN,						// GPIO26		-> FORCE_DFU
+	CFG_DISABLED | PULL_DOWN,					// GPIO27		-> DFU_STATUS
+	CFG_DISABLED,							// GPIO28		-> BOOT_CONFIG[2]
+	CFG_DISABLED,							// GPIO29		-> BOOT_CONFIG[3]
+	CFG_DISABLED,							// GPIO30		->
+	CFG_DISABLED,							// GPIO31		->
+
+/* Port  4 */
+	CFG_DISABLED,							// GPIO32		->
+	CFG_DISABLED,							// GPIO33		->
+	CFG_DISABLED,							// GPIO34		->
+	CFG_DISABLED,							// GPIO35		->
+	CFG_DISABLED,							// GPIO36		->
+	CFG_DISABLED,							// EHCI_PORT_PWR[0]	-> BOARD_REV[0]
+	CFG_DISABLED,							// EHCI_PORT_PWR[1]	-> BOARD_REV[1]
+	CFG_DISABLED,							// EHCI_PORT_PWR[2]	-> BOARD_REV[2]
+
+/* Port  5 */
+	CFG_DISABLED,							// UART1_TXD		->
+	CFG_DISABLED,							// UART1_RXD		->
+	CFG_DISABLED,							// UART1_RTSN		->
+	CFG_DISABLED,							// UART1_CTSN		->
+	CFG_DISABLED,							// UART2_TXD		->
+	CFG_DISABLED,							// UART2_RXD		->
+	CFG_DISABLED,							// UART2_RTSN		->
+	CFG_DISABLED,							// UART2_CTSN		->
+
+/* Port  6 */
+	CFG_DISABLED,							// UART3_TXD		->
+	CFG_DISABLED,							// UART3_RXD		->
+	CFG_DISABLED,							// UART3_RTSN		->
+	CFG_DISABLED,							// UART3_CTSN		->
+	CFG_DISABLED,							// I2C0_SDA		->
+	CFG_DISABLED,							// I2C0_SCL		->
+	CFG_DISABLED,							// I2C1_SDA		->
+	CFG_DISABLED,							// I2C1_SCL		->
+
+/* Port  7 */
+	CFG_DISABLED,							// ISP0_SDA		->
+	CFG_DISABLED,							// ISP0_SCL		->
+	CFG_DISABLED,							// ISP1_SDA		->
+	CFG_DISABLED,							// ISP1_SCL		->
+	CFG_DISABLED,							// UART5_TXD/MIPI_VSYNC	->
+	CFG_DISABLED,							// TMR32_PWM0
+	CFG_DISABLED,							// TMR32_PWM1
+	CFG_DISABLED,							// TMR32_PWM2
+
+/* Port  8 */
+	CFG_DISABLED,							// SWI_DATA		->
+	CFG_DISABLED,							// DWI_DI		->
+	CFG_DISABLED,							// DWI_DO		->
+	CFG_DISABLED,							// DWI_CLK		->
+	CFG_DISABLED,							// SENSOR0_RST		->
+	CFG_DISABLED,							// SENSOR0_CLK		->
+	CFG_DISABLED,							// SENSOR1_RST		->
+	CFG_DISABLED,							// SENSOR1_CLK		->
+
+/* Port  9 */
+	CFG_DISABLED,							// ISP0_PRE_FLASH	->
+	CFG_DISABLED,							// ISP0_FLASH		->
+	CFG_DISABLED,							// ISP1_PRE_FLASH	->
+	CFG_DISABLED,							// ISP1_FLASH		->
+	CFG_DISABLED,							// I2S0_MCK		->
+	CFG_DISABLED,							// I2S0_LRCK		->
+	CFG_DISABLED,							// I2S0_SCLK		->
+	CFG_DISABLED,							// I2S0_DOUT		->
+
+/* Port 10 */
+	CFG_DISABLED,							// I2S0_DIN		->
+	CFG_DISABLED,							// I2S1_MCK		->
+	CFG_DISABLED,							// I2S1_LRCK		->
+	CFG_DISABLED,							// I2S1_SCLK		->
+	CFG_DISABLED,							// I2S1_DOUT		->
+	CFG_DISABLED,							// I2S1_DIN		->
+	CFG_DISABLED,							// I2S2_MCK		->
+	CFG_DISABLED,							// I2S2_LRCK		->
+
+/* Port 11 */
+	CFG_DISABLED,							// I2S2_BCLK		->
+	CFG_DISABLED,							// I2S2_DOUT		->
+	CFG_DISABLED,							// I2S2_DIN		->
+	CFG_DISABLED,							// I2S2_MCK		->
+	CFG_DISABLED,							// I2S3_LRCK		->
+	CFG_DISABLED,							// I2S3_BCLK		->
+	CFG_DISABLED,							// I2S3_DOUT		->
+	CFG_DISABLED,							// I2S3_DIN		->
+
+/* Port 12 */
+	CFG_DISABLED,							// SPI0_SCLK		-> BOARD_ID[0]
+	CFG_DISABLED,							// SPI0_MOSI		-> BOARD_ID[1]
+	CFG_DISABLED,							// SPI0_MISO		-> BOARD_ID[2]
+	CFG_DISABLED | PULL_UP,						// SPI0_SSIN		->
+	CFG_DISABLED,							// SPI1_SCLK		->
+	CFG_DISABLED,							// SPI1_MOSI		->
+	CFG_DISABLED,							// SPI1_MISO		->
+	CFG_DISABLED,							// SPI1_SSIN		->
+
+/* Port 13 */
+	CFG_DISABLED,							// SPI2_SCLK		->
+	CFG_DISABLED,							// SPI2_MOSI		->
+	CFG_DISABLED,							// SPI2_MISO		->
+	CFG_DISABLED,							// SPI2_SSIN		->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 14 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 15 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 16 */
+	CFG_DISABLED,							// UART4_TXD		-> SPI3_SCLK/FMI0_CEN7
+	CFG_DISABLED,							// UART4_RXD		-> SPI3_MOSI/FMI0_CEN6
+	CFG_DISABLED,							// UART4_RTSN		-> SPI3_MISO/FMI0_CEN5
+	CFG_DISABLED,							// UART4_CTSN		-> SPI3_SSIN/FMI0_CEN4
+	CFG_DISABLED,							// SDIO0_DATA3		-> FMI1_CEN7
+	CFG_DISABLED,							// SDIO0_DATA2		-> FMI1_CEN6
+	CFG_DISABLED,							// SDIO0_DATA1		-> FMI1_CEN5
+	CFG_DISABLED,							// SDIO0_DATA0		-> FMI1_CEN4
+
+/* Port 17 */
+	CFG_DISABLED,							// SDIO0_CMD		->
+	CFG_DISABLED,							// SDIO0_CLK		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN3		-> FMI0_RBN0
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN2		-> FMI0_RBN1
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN1		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_ALE		->
+
+/* Port 18 */
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO5		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO4		->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 19 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 20 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO2		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO1		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO0		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN3		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN2		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN1		->
+
+/* Port 21 */
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO5		->
+
+/* Port 22 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO4		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO2		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO1		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO0		->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 23 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 24 */
+	CFG_DISABLED,							// I2C2_SDA		->
+	CFG_DISABLED,							// I2C2_SCL		->
+	CFG_DISABLED,							// UART0_TXD		->
+	CFG_DISABLED,							// UART0_RXD		->
+	CFG_DISABLED,							// UART5_RTXD		-> UART5_RXD
+	CFG_DISABLED,							// DP_HPD		->
+	CFG_DISABLED,							// TST_CLKOUT		->
+	CFG_DISABLED,							// TST_STPCLK		->
+
+/* Port 25 */
+	CFG_DISABLED,							// WDOG			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+};
+
+#endif /* ! __PLATFORM_PINCONFIG_S5L8942X_H */

platform/s5l8940x/include/platform/pinconfig_s5l8947x.h

@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_PINCONFIG_S5L8947X_H
+#define __PLATFORM_PINCONFIG_S5L8947X_H
+
+/* Default S5L8947X SoC Pin Configuration */
+
+#define FMI_DRIVE_STR	DRIVE_X2
+#define FMI_SLEW_RATE	SLEW_RATE_SLOW
+
+static const u_int32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
+/* Port  0 */
+	CFG_DISABLED,							// I2S0_MCK		->
+	CFG_IN,								// I2S0_LRCK		->
+	CFG_DISABLED,							// I2S0_BCLK		->
+	CFG_DISABLED,							// I2S0_DOUT		->
+	CFG_DISABLED,							// I2S0_DIN		->
+	CFG_DISABLED,							// UART0_TXD		->
+	CFG_DISABLED,							// UART0_RXD		->
+	CFG_DISABLED,							// UART1_TXD		->
+
+/* Port  1 */
+	CFG_DISABLED,							// UART1_RXD		->
+	CFG_DISABLED,							// I2C1_SDA		->
+	CFG_DISABLED,							// I2C1_SCL		->
+	CFG_DISABLED,							// HDMI_HPD		->
+	CFG_DISABLED,							// HDMI_CEC		->
+	CFG_DISABLED,							// I2C2_SDA		->
+	CFG_DISABLED,							// I2C2_SCL		->
+	CFG_DISABLED,							// SPDIF		->
+
+/* Port  2 */
+	CFG_DISABLED,							// GPIO22		->
+	CFG_DISABLED,							// GPIO23		->
+	CFG_DISABLED,							// UART2_TXD		->
+	CFG_DISABLED,							// UART2_RXD		->
+	CFG_DISABLED,							// UART2_RTSN		->
+	CFG_DISABLED,							// UART2_CTSN		->
+	CFG_DISABLED,							// UART3_TXD		->
+	CFG_DISABLED,							// UART3_RXD		->
+
+/* Port  3 */
+	CFG_DISABLED,							// UART4_TXD		->
+	CFG_DISABLED,							// UART4_RXD		->
+	CFG_DISABLED,							// TST_CLKOUT		->
+	CFG_DISABLED | PULL_DOWN,					// TST_STPCLK		->
+	CFG_DISABLED,							// WDOG			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port  4 */
+	CFG_DISABLED,							// ENET_MDC		->
+	CFG_DISABLED,							// ENET_MDIO		->
+	CFG_DISABLED,							// RMII_CLK		->
+	CFG_DISABLED,							// RMII_RXER		->
+	CFG_DISABLED,							// RMII_TXD[0]		->
+	CFG_DISABLED,							// RMII_CRSDV		->
+	CFG_DISABLED,							// RMII_RXD[0]		->
+	CFG_DISABLED,							// RMII_RXD[1]		->
+
+/* Port  5 */
+	CFG_DISABLED,							// RMII_TXD[1]		->
+	CFG_DISABLED,							// RMII_TXEN		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN[1]		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN[0]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_WEN		->
+
+/* Port  6 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[7]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[6]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[5]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[4]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[3]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[2]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[1]		->
+
+/* Port  7 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[0]		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN[1]		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN[0]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[7]		->
+
+/* Port  8 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[6]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[5]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[4]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[3]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[2]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[1]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[0]		->
+
+/* Port  9 */
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+
+/* Port 10 */
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+
+/* Port 11 */
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+
+/* Port 12 */
+	CFG_IN,								// GPIO0		-> MENU_KEY
+	CFG_IN,								// GPIO1		-> HOLD_KEY
+	CFG_DISABLED,							// GPIO2		->
+	CFG_DISABLED,							// GPIO3		->
+	CFG_DISABLED,							// GPIO4		->
+	CFG_DISABLED,							// GPIO5		->
+	CFG_DISABLED,							// GPIO6		->
+	CFG_DISABLED,							// GPIO7		->
+
+/* Port 13 */
+	CFG_DISABLED,							// GPIO8		->
+	CFG_DISABLED,							// GPIO9		->
+	CFG_DISABLED,							// GPIO10		->
+	CFG_DISABLED,							// GPIO11		->
+	CFG_DISABLED,							// GPIO12		->
+	CFG_DISABLED,							// GPIO13		->
+	CFG_DISABLED,							// GPIO14		->
+	CFG_DISABLED,							// GPIO15		->
+
+/* Port 14 */
+	CFG_DISABLED,							// GPIO16		-> BOARD_ID[3]
+	CFG_DISABLED,							// GPIO17		->
+	CFG_DISABLED,							// GPIO18		-> BOOT_CONFIG[0]
+	CFG_DISABLED,							// GPIO19		-> KEEPACT
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 15 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 16 */
+	CFG_DISABLED,							// GPIO20		->
+	CFG_DISABLED,							// GPIO21		->
+	CFG_DISABLED,							// GPIO24		->
+	CFG_DISABLED,							// GPIO25		-> BOOT_CONFIG[1]
+	CFG_IN | PULL_DOWN,						// GPIO26		-> FORCE_DFU
+	CFG_DISABLED | PULL_DOWN,					// GPIO27		-> DFU_STATUS
+	CFG_DISABLED,							// GPIO28		-> BOOT_CONFIG{2]
+	CFG_DISABLED,							// GPIO29		-> BOOT_CONFIG[3]
+
+/* Port 17 */
+	CFG_DISABLED,							// I2C0_SDA		->
+	CFG_DISABLED,							// I2C0_SCL		->
+	CFG_DISABLED,							// TMR32_PWM0		->
+	CFG_DISABLED,							// SPI0_SCLK		-> SPI0_SCLK/BOARD_ID[0]
+	CFG_DISABLED,							// SPI0_MOSI		-> SPI0_MOSI/BOARD_ID[1]
+	CFG_DISABLED,							// SPI0_MISO		-> SPI0_MISO/BOARD_ID[2]
+	CFG_DISABLED | PULL_UP,						// SPI0_SSIN		->
+	CFG_DISABLED,							// SWI_DATA		->
+};
+
+#endif /* ! __PLATFORM_PINCONFIG_S5L8947X_H */

platform/s5l8940x/include/platform/soc/chipid.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2009-2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_CHIPID_H
+#define __PLATFORM_SOC_CHIPID_H
+
+#include <platform/chipid.h>
+#include <platform/soc/hwregbase.h>
+
+#define	rCFG_FUSE0			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x00))
+#define	rCFG_FUSE1			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x04))
+#define	rCFG_FUSE2			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x08))
+#define	rCFG_FUSE3			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x0C))
+
+#define	rECIDLO				(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x10))
+#define	rECIDHI				(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x14))
+
+extern bool	chipid_get_ecid_image_personalization_required(void);
+
+#define CHIPID_SOC_VOLTAGE_LOW		(0)
+#define CHIPID_SOC_VOLTAGE_MED		(1)
+#define CHIPID_SOC_VOLTAGE_HIGH		(2)
+extern u_int32_t chipid_get_soc_voltage(u_int32_t index);
+
+#define CHIPID_CPU_VOLTAGE_LOW		(0)
+#define CHIPID_CPU_VOLTAGE_MED		(1)
+#define CHIPID_CPU_VOLTAGE_HIGH		(2)
+extern u_int32_t chipid_get_cpu_voltage(u_int32_t index);
+
+#endif /* __PLATFORM_SOC_CHIPID_H */

platform/s5l8940x/include/platform/soc/display.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2012-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __APPLE_DISPLAY_H
+#define __APPLE_DISPLAY_H
+
+// Platform-specific displaypipe tunables
+static struct adfe_v1_tuneable adfe_tuneables[] = 
+{
+	{
+		.name = "default",
+		.disp_dpcclkcntl[0] = 			0,
+		.disp_dpbclklvl_clock_off_level[0] =	DPBCLKLVL_OFFLVL(0x01f0),
+		.disp_dpbclklvl_clock_on_level[0] =	DPBCLKLVL_ONLVL(0x0180),
+		.disp_dpusrcstrd[0] =			DPUSRCSTRD_SRCBURST_4BLOCKS,
+		.disp_dpcqoscnfg[0] =			(DPCQOSCNFG_QOS_TIMER(0x0040) | \
+							 DPCQOSCNFG_QOS_ENABLE),
+		.disp_dpbqoslvl_med_watermark[0] =	DPBQOSLVL_MED_WATERMARK(0x0100),
+		.disp_dpbqoslvl_high_watermark[0] =	DPBQOSLVL_HIGH_WATERMARK(0x0000),
+		.disp_dpureqcfg[0] =			0,
+
+		.disp_dpcclkcntl[1] = 			0,
+		.disp_dpbclklvl_clock_off_level[1] =	DPBCLKLVL_OFFLVL(0x01f0),
+		.disp_dpbclklvl_clock_on_level[1] =	DPBCLKLVL_ONLVL(0x01c0),
+		.disp_dpusrcstrd[1] =			DPUSRCSTRD_SRCBURST_4BLOCKS,
+		.disp_dpcqoscnfg[1] =			(DPCQOSCNFG_QOS_TIMER(0x0040) | \
+							 DPCQOSCNFG_QOS_ENABLE),
+		.disp_dpbqoslvl_med_watermark[1] =	DPBQOSLVL_MED_WATERMARK(0x0100),
+		.disp_dpbqoslvl_high_watermark[1] =	DPBQOSLVL_HIGH_WATERMARK(0x0000),
+		.disp_dpureqcfg[1] =			0,
+	},
+};
+
+#endif	/* ! __APPLE_DISPLAY_H */

platform/s5l8940x/include/platform/soc/display_timings.h

@@ -0,0 +1,222 @@
+/*
+ * Copyright (C) 2013-2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __APPLE_DISPLAY_TIMINGS_H
+#define __APPLE_DISPLAY_TIMINGS_H
+
+//Supported timings by this platform
+static struct display_timing timing_list[] =
+{
+#if DEBUG_BUILD || SUB_TARGET_K93 || SUB_TARGET_K94 || SUB_TARGET_K95 || SUB_TARGET_K93A
+	{ 
+	.display_name = 	"k48",	
+	.host_clock_id = 	CLK_VCLK0, 
+	.pixel_clock = 		68400000, 
+	.dot_pitch = 		132, 
+	.h_active =		1024,
+	.h_pulse_width = 	135, 
+	.h_back_porch = 	133,
+	.h_front_porch =        133,
+	.v_active = 		768, 
+	.v_pulse_width =  	12, 
+	.v_back_porch = 	10, 
+	.v_front_porch =        10, 
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	18, 
+	.display_type = 	DISPLAY_TYPE_PINOT, 
+	.display_config		= NULL,
+	},
+#endif
+#if DEBUG_BUILD || SUB_TARGET_N94
+	{ 
+	.display_name = 	"n94",	
+	.host_clock_id = 	CLK_VCLK0, 
+	.pixel_clock = 		51300000, 
+	.dot_pitch = 		326,
+	.h_active =		640, 
+	.h_pulse_width =	73, 
+	.h_back_porch =		71, 
+	.h_front_porch =       	71, 
+	.v_active = 		960, 
+	.v_pulse_width =  	16, 
+	.v_back_porch = 	12, 
+	.v_front_porch =       	12, 
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	24, 
+	.display_type = 	DISPLAY_TYPE_PINOT, 
+	.display_config		= NULL,
+	},
+	
+	{ 
+	.display_name = 	"n94-2",	
+	.host_clock_id = 	CLK_VCLK0, 
+	.pixel_clock = 		51300000, 
+	.dot_pitch = 		326, 
+	.h_active =		640, 
+	.h_pulse_width = 	73, 
+	.h_back_porch = 	71, 
+	.h_front_porch =       	71, 
+	.v_active = 		960,
+	.v_pulse_width =  	16, 
+	.v_back_porch = 	12, 
+	.v_front_porch =       	12, 
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	24, 
+	.display_type = 	DISPLAY_TYPE_PINOT, 
+	.display_config		= NULL,
+	},
+	
+	{ 
+	.display_name = 	"d300",	
+	.host_clock_id = 	CLK_VCLK0, 
+	.pixel_clock = 		60350000, 
+	.dot_pitch = 		326, 
+	.h_active =		640,
+	.h_pulse_width = 	48, 
+	.h_back_porch = 	48, 
+	.h_front_porch =       	48, 
+	.v_active = 		960,
+	.v_pulse_width =	3,  
+	.v_back_porch = 	13, 
+	.v_front_porch =       	307, 
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	24, 
+	.display_type = 	DISPLAY_TYPE_PINOT, 
+	.display_config		= NULL,
+	},
+#endif
+#if DEBUG_BUILD || SUB_TARGET_P105 || SUB_TARGET_P106 || SUB_TARGET_P107
+	{ 
+	.display_name = 	"ipad2b",	
+	.host_clock_id = 	CLK_VCLK0, 
+	.pixel_clock = 		68400000, 
+	.dot_pitch = 		163, 
+	.h_active =		768,
+	.h_pulse_width = 	80, 
+	.h_back_porch = 	76,
+	.h_front_porch =        76,
+	.v_active = 		1024,
+	.v_pulse_width =  	40, 
+	.v_back_porch = 	38, 
+	.v_front_porch =        38,
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	18, 
+	.display_type = 	DISPLAY_TYPE_PINOT, 
+	.display_config		= NULL,
+	},
+	
+	{ 
+	.display_name = 	"ipad2b-p0",
+	.host_clock_id =	CLK_VCLK0, 
+	.pixel_clock = 		68400000, 
+	.dot_pitch = 		163, 
+	.h_active =		768,
+	.h_pulse_width = 	80, 
+	.h_back_porch = 	113,
+	.h_front_porch =       	113,
+	.v_active = 		1024,
+	.v_pulse_width =  	18, 
+	.v_back_porch = 	10, 
+	.v_front_porch =       	10, 
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	18, 
+	.display_type = 	DISPLAY_TYPE_PINOT, 
+	.display_config		= NULL,
+	},
+#endif
+#if DEBUG_BUILD || WITH_HW_DISPLAY_DISPLAYPORT
+	{ 
+	.display_name = 	"720p",	
+	.host_clock_id = 	CLK_VCLK1, 
+	.pixel_clock = 		74250000,
+	.dot_pitch = 		243, 
+	.h_active =		1280,
+	.h_pulse_width = 	40,  
+	.h_back_porch = 	220, 
+	.h_front_porch =        110, 
+	.v_active = 		720,
+	.v_pulse_width =  	5, 
+	.v_back_porch = 	20, 
+	.v_front_porch =        5, 
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	24, 
+	.display_type = 	DISPLAY_TYPE_DP,     
+	.display_config		= NULL,
+	},
+#endif
+#if DEBUG_BUILD || SUB_TARGET_N78
+	{ 
+	.display_name = 	"n41",	
+	.host_clock_id = 	CLK_VCLK0, 
+	.pixel_clock = 		68400000, 
+	.dot_pitch = 		326, 
+	.h_active =		640,
+	.h_pulse_width = 	40,  
+	.h_back_porch = 	40, 
+	.h_front_porch =       	40,
+	.v_active = 		1136,
+	.v_pulse_width =  	3,  
+	.v_back_porch = 	13, 
+	.v_front_porch =       	348, 
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	24, 
+	.display_type = 	DISPLAY_TYPE_PINOT, 
+	.display_config		= NULL,
+	},
+#endif
+#if DEBUG_BUILD || WITH_HW_DISPLAY_HDMI
+	{ 
+	.display_name =   	"720p-hdmi",	
+	.host_clock_id =  	CLK_VCLK1, 
+	.pixel_clock = 	  	74250000, 
+	.dot_pitch = 	  	243, 
+	.h_active =	  	1280,
+	.h_pulse_width =  	40, 
+	.h_back_porch =   	220, 
+	.h_front_porch =  	110, 
+	.v_active = 	  	720,
+	.v_pulse_width =  	5,  
+	.v_back_porch =   	20, 
+	.v_front_porch =  	5,
+	.neg_vclk = 	  	0, 
+	.neg_hsync = 	  	0, 
+	.neg_vsync = 	 	0, 
+	.neg_vden = 	  	0, 
+	.display_depth =  	24, 
+	.display_type =   	DISPLAY_TYPE_HDMI,     
+	.display_config		= NULL,
+	},
+#endif
+};
+#endif	/* ! __APPLE_DISPLAY_TIMINGS_H */

platform/s5l8940x/include/platform/soc/hwclocks.h

@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2009 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWCLOCKS_H
+#define __PLATFORM_SOC_HWCLOCKS_H
+
+#include <platform/clocks.h>
+
+#if SUPPORT_FPGA
+#if SUB_PLATFORM_S5L8947X
+#define OSC_FREQ			(7500000UL)
+#else
+#define OSC_FREQ			(5000000UL)
+#endif
+#else
+#define OSC_FREQ			(24000000UL)
+#endif
+
+#define CLK_FCLK	(HWCLOCK_BASE+0)
+#define CLK_ACLK	(HWCLOCK_BASE+1)
+#define CLK_HCLK	(HWCLOCK_BASE+2)
+#define CLK_PCLK	(HWCLOCK_BASE+3)
+#define CLK_VCLK0	(HWCLOCK_BASE+4)
+#define CLK_VCLK1	(HWCLOCK_BASE+5)
+#define CLK_MCLK	(HWCLOCK_BASE+6)
+#define CLK_NCLK	(HWCLOCK_BASE+7)
+#define CLK_USBPHYCLK	(HWCLOCK_BASE+8)
+#define CLK_NCOREF	(HWCLOCK_BASE+9)
+#define CLK_FMI		(HWCLOCK_BASE+10)
+
+/* S5L8940X clock gate devices */
+enum {
+	CLK_CPU0 = 0,
+	CLK_CPU1,
+	CLK_SCU,
+	CLK_L2RAM0,
+	CLK_L2RAM1,
+	CLK_CPU_REGS,
+	CLK_MCU,
+	CLK_GFX_SYS,
+	CLK_GFX_CORES,
+	CLK_HPERFNRT,
+	CLK_VDEC,
+	CLK_SCALER0,
+	CLK_SCALER1,
+	CLK_JPG,
+	CLK_VENCD,
+	CLK_HPERFRT,
+	CLK_ISP,
+	CLK_resv0,
+	CLK_resv1,
+	CLK_DISP0,
+	CLK_DISP1,
+	CLK_DISPOUT,
+	CLK_MIPI,
+	CLK_CLCD,
+	CLK_TVDAC,
+	CLK_RGBOUT,
+	CLK_DPLINK,
+	CLK_CDIO,
+	CLK_CDMA,
+	CLK_IOP,
+	CLK_UPERF,
+	CLK_USBOTG,
+	CLK_USB20,
+	CLK_USB11,
+	CLK_USBOHCI0,
+	CLK_USBOHCI1,
+	CLK_USBPHY,
+	CLK_AUDIO,
+	CLK_I2S0,
+	CLK_I2S1,
+	CLK_I2S2,
+	CLK_I2S3,
+	CLK_SPDIF,
+	CLK_HPARK,
+	CLK_SDIO,
+	CLK_SHA1,
+	CLK_SHA2,
+	CLK_FMI0,
+	CLK_FMI0BCH,
+	CLK_FMI1,
+	CLK_FMI1BCH,
+	CLK_FMI2,
+	CLK_FMI2BCH,
+	CLK_FMI3,
+	CLK_FMI3BCH,
+	CLK_SPI0,
+	CLK_SPI1,
+	CLK_SPI2,
+	CLK_SPI3,
+	CLK_SPI4,
+	CLK_UART0,
+	CLK_UART1,
+	CLK_UART2,
+	CLK_UART3,
+	CLK_UART4,
+	CLK_UART5,
+	CLK_UART6,
+	CLK_PKE,
+	CLK_I2C0,
+	CLK_I2C1,
+	CLK_I2C2,
+	CLK_PWM,
+	CLK_SCRT,
+	CLK_GPIO,
+	CLK_SWI,
+	CLK_DWI,
+	CLK_DEBUG,
+	CLK_AIC,
+#if SUB_PLATFORM_S5L8947X
+	CLK_MCA0,
+	CLK_ETH,
+	CLK_HDMI,
+	CLK_ADC,
+	CLK_USBOTG1,
+	CLK_USB20_1,
+	CLK_USBOHCI0_1,
+	CLK_USBREG1,
+#endif
+};
+
+#endif /* ! __PLATFORM_SOC_HWCLOCKS_H */

platform/s5l8940x/include/platform/soc/hwdmachannels.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWDMACHANNELS_H
+#define __PLATFORM_SOC_HWDMACHANNELS_H
+
+#include <platform.h>
+
+#include SUB_PLATFORM_HEADER(soc/hwdmachannels)
+
+#define DMA_SDIO_TIMEOUT_US (10 * 1000)
+
+#endif /* ! __PLATFORM_SOC_HWDMACHANNELS_H */

platform/s5l8940x/include/platform/soc/hwdmachannels_s5l8940x.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWDMACHANNELS_S5L8940X_H
+#define __PLATFORM_SOC_HWDMACHANNELS_S5L8940X_H
+
+#define DMA_MEMORY_TX		(1)
+#define DMA_MEMORY_RX		(2)
+#define DMA_SDIO		(3)
+#define DMA_FMI0DATA		(5)
+#define DMA_FMI0CHECK		(6)
+#define DMA_FMI1DATA		(7)
+#define DMA_FMI1CHECK		(8)
+#define DMA_FMI2DATA		(9)
+#define DMA_FMI2CHECK		(10)
+#define DMA_FMI3DATA		(11)
+#define DMA_FMI3CHECK		(12)
+
+#define DMA_CHANNEL_COUNT	(44)
+
+#define DMA_CHANNEL_CONFIG						\
+{									\
+	/*	low	high	AES OK	reqID	FIFO address */		\
+	{	3,	4,	false,	0x00,	0x30000020	},	\
+	{	3,	4,	false,	0x01,	0x301000A0	},	\
+	{	3,	4,	false,	0x01,	0x30200020	},	\
+	{	5,	12,	true,	0x00,	0x31200014	},	\
+	{	5,	12,	true,	0x01,	0x31200018	},	\
+ 	{	5,	12,	true,	0x02,	0x31300014	},	\
+	{	5,	12,	true,	0x03,	0x31300018	},	\
+	{	5,	12,	true,	0x04,	0x31400014	},	\
+	{	5,	12,	true,	0x05,	0x31400018	},	\
+ 	{	5,	12,	true,	0x06,	0x31500014	},	\
+	{	5,	12,	true,	0x07,	0x31500018	},	\
+}
+
+#endif /* ! __PLATFORM_SOC_HWDMACHANNELS_S5L8940X_H */

platform/s5l8940x/include/platform/soc/hwdmachannels_s5l8942x.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWDMACHANNELS_S5L8942X_H
+#define __PLATFORM_SOC_HWDMACHANNELS_S5L8942X_H
+
+#define DMA_MEMORY_TX		(1)
+#define DMA_MEMORY_RX		(2)
+#define DMA_SDIO		(3)
+#define DMA_FMI0DATA		(5)
+#define DMA_FMI0CHECK		(6)
+#define DMA_FMI1DATA		(7)
+#define DMA_FMI1CHECK		(8)
+
+#define DMA_CHANNEL_COUNT	(42)
+
+#define DMA_CHANNEL_CONFIG						\
+{									\
+	/*	low	high	AES OK	reqID	FIFO address */		\
+	{	3,	4,	false,	0x00,	0x30000010	},	\
+	{	3,	4,	false,	0x00,	0x30000020	},	\
+	{	3,	4,	false,	0x01,	0x301000A0	},	\
+	{	3,	4,	false,	0x01,	0x30200020	},	\
+	{	5,	8,	true,	0x00,	0x31200014	},	\
+	{	5,	8,	true,	0x01,	0x31200018	},	\
+ 	{	5,	8,	true,	0x02,	0x31300014	},	\
+	{	5,	8,	true,	0x03,	0x31300018	},	\
+}
+
+#endif /* ! __PLATFORM_SOC_HWDMACHANNELS_S5L8942X_H */

platform/s5l8940x/include/platform/soc/hwdmachannels_s5l8947x.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWDMACHANNELS_S5L8947X_H
+#define __PLATFORM_SOC_HWDMACHANNELS_S5L8947X_H
+
+#define DMA_MEMORY_TX		(1)
+#define DMA_MEMORY_RX		(2)
+#define DMA_FMI0DATA		(5)
+#define DMA_FMI0CHECK		(6)
+#define DMA_FMI1DATA		(7)
+#define DMA_FMI1CHECK		(8)
+
+#define DMA_CHANNEL_COUNT	(42)
+
+#define DMA_CHANNEL_CONFIG						\
+{									\
+	/*	low	high	AES OK	reqID	FIFO address */		\
+	{	3,	4,	false,	0x00,	0x30000010	},	\
+	{	3,	4,	false,	0x00,	0x30000020	},	\
+	{	3,	4,	false,	0x01,	0x301000A0	},	\
+	{	3,	4,	false,	0x01,	0x30200020	},	\
+	{	5,	8,	true,	0x00,	0x31200014	},	\
+	{	5,	8,	true,	0x01,	0x31200018	},	\
+ 	{	5,	8,	true,	0x02,	0x31300014	},	\
+	{	5,	8,	true,	0x03,	0x31300018	},	\
+}
+
+#endif /* ! __PLATFORM_SOC_HWDMACHANNELS_S5L8947X_H */

platform/s5l8940x/include/platform/soc/hwisr.h

@@ -0,0 +1,198 @@
+/*
+ * Copyright (C) 2009-2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWISR_H
+#define __PLATFORM_SOC_HWISR_H
+
+#define INT_SW0			0	// Software 0 Interrupt
+#define INT_SW1			1	// Software 1 Interrupt
+#define INT_SW2			2	// Software 2 Interrupt
+#define INT_SW3			3	// Software 3 Interrupt
+#define INT_WDT			4	// Watchdog Timer Interrupt
+#define INT_SWI			5	// SWI Interrupt
+#define INT_DWI			6	// DWI Interrupt
+#define INT_ISP0		7	// ISP 0 Interrupt
+#define INT_ISP1       		8	// ISP 1 Interrupt
+#define INT_SCALER0		9	// Scaler Interrupt
+#define INT_SCALER1		10	// Scaler Interrupt
+#define INT_USB_OTG		11	// USB OTG Interrupt
+#define INT_USB_EHCI		12	// USB EHCI Interrupt
+#define INT_USB_OHCI0		13	// USB OHCI 0 Interrupt
+#define INT_USB_OHCI1		14	// USB OHCI 1 Interrupt
+#define INT_USB_RES		15	// USB PHY Interrupt
+#define INT_PWM			16	// PWM Interrupt
+#define INT_PKE			17	// PKE Interrupt
+#define INT_IIC0		18	// I2C 0 Interrupt
+#define INT_IIC1		19	// I2C 1 Interrupt
+#define INT_IIC2		20	// I2C 2 Interrupt
+#define INT_UART0		21	// UART 0 Interrupt
+#define INT_UART1		22	// UART 1 Interrupt
+#define INT_UART2		23	// UART 2 Interrupt
+#define INT_UART3		24	// UART 3 Interrupt
+#define INT_UART4 		25	// UART 4 Interrupt
+#define INT_UART5 		26	// UART 5 Interrupt
+#if SUB_PLATFORM_S5L8947X
+#define INT_ETH			27	// Ethernet Interrupt
+#else
+#define INT_UART6		27	// UART 6 Interrupt
+#endif
+#define INT_SPI0 		28	// SPI 0 Interrupt
+#define INT_SPI1		29	// SPI 1 Interrupt
+#define INT_SPI2		30	// SPI 2 Interrupt
+#define INT_SPI3		31	// SPI 3 Interrupt
+#if SUB_PLATFORM_S5L8947X
+#define INT_USB_DEV_RES		32	// USB PHY1 Interrupt
+#else
+#define INT_SPI4		32	// SPI 4 Interrupt
+#endif
+#define INT_FMI0		33	// FMI 0 Interrupt
+#define INT_FMI1		34	// FMI 1 Interrupt
+#if SUB_PLATFORM_S5L8947X
+#define INT_USB_DEV_OTG		35	// USB OTG1 Interrupt
+#define INT_USB_DEV_EHCI	36	// USB EHCI1 Interrupt
+#else
+#define INT_FMI2		35	// FMI 2 Interrupt
+#define INT_FMI3		36	// FMI 3 Interrupt
+#endif
+#define INT_SHA1		37	// SHA-1 Interrupt
+#define INT_SHA2		38	// SHA-1 Interrupt
+#define INT_WIFI		39	// WiFi Interrupt
+#define INT_TVOUT		40	// TV Out Interrupt
+#define INT_MIPI_DSI		41	// MIPI DSI Interrupt	 	
+#define INT_CLCD		42	// CLCD Interrupt
+#define INT_DISP0		43	// Display Pipe 0 Interrupt	
+#define INT_DISP1		44	// Display Pipe 1 Interrupt
+#define INT_RGBOUT		45	// RGB Out Interrupt
+#if SUB_PLATFORM_S5L8947X
+#define INT_HDMI_LINK		46	// HDMI link Interrupt
+#define INT_HDMI_CEC		47	// HDMI cec Interrupt
+#else
+#define INT_DPORT0		46	// DisplayPort 0 Interrupt
+#define INT_DPORT1		47	// DisplayPort 1 Interrupt
+#endif
+#define INT_VENC		48	// Video Encoder Interrupt
+#define INT_SGX			49	// SGX Interrupt
+#define INT_VDEC		50	// Video Decoder Interrupt
+#define INT_CDMA_DMAC1		51	// CDMA DMA Channel 1 Interrupt
+#define INT_CDMA_DMAC2		52	// CDMA DMA Channel 2 Interrupt
+#define INT_CDMA_DMAC3		53	// CDMA DMA Channel 3 Interrupt
+#define INT_CDMA_DMAC4		54	// CDMA DMA Channel 4 Interrupt
+#define INT_CDMA_DMAC5		55	// CDMA DMA Channel 5 Interrupt
+#define INT_CDMA_DMAC6		56	// CDMA DMA Channel 6 Interrupt
+#define INT_CDMA_DMAC7		57	// CDMA DMA Channel 7 Interrupt
+#define INT_CDMA_DMAC8		58	// CDMA DMA Channel 8 Interrupt
+#define INT_CDMA_DMAC9		59	// CDMA DMA Channel 9 Interrupt
+#define INT_CDMA_DMAC10		60	// CDMA DMA Channel 10 Interrupt
+#define INT_CDMA_DMAC11		61	// CDMA DMA Channel 11 Interrupt
+#define INT_CDMA_DMAC12		62	// CDMA DMA Channel 12 Interrupt
+#define INT_CDMA_DMAC13		63	// CDMA DMA Channel 13 Interrupt
+#define INT_CDMA_DMAC14		64	// CDMA DMA Channel 14 Interrupt
+#define INT_CDMA_DMAC15		65	// CDMA DMA Channel 15 Interrupt
+#define INT_CDMA_DMAC16		66	// CDMA DMA Channel 16 Interrupt
+#define INT_CDMA_DMAC17		67	// CDMA DMA Channel 17 Interrupt
+#define INT_CDMA_DMAC18		68	// CDMA DMA Channel 18 Interrupt
+#define INT_CDMA_DMAC19		69	// CDMA DMA Channel 19 Interrupt
+#define INT_CDMA_DMAC20		70	// CDMA DMA Channel 20 Interrupt
+#define INT_CDMA_DMAC21		71	// CDMA DMA Channel 21 Interrupt
+#define INT_CDMA_DMAC22		72	// CDMA DMA Channel 22 Interrupt
+#define INT_CDMA_DMAC23		73	// CDMA DMA Channel 23 Interrupt
+#define INT_CDMA_DMAC24		74	// CDMA DMA Channel 24 Interrupt
+#define INT_CDMA_DMAC25		75	// CDMA DMA Channel 25 Interrupt
+#define INT_CDMA_DMAC26		76	// CDMA DMA Channel 26 Interrupt
+#define INT_CDMA_DMAC27		77	// CDMA DMA Channel 27 Interrupt
+#define INT_CDMA_DMAC28		78	// CDMA DMA Channel 28 Interrupt
+#define INT_CDMA_DMAC29		79	// CDMA DMA Channel 29 Interrupt
+#define INT_CDMA_DMAC30		80	// CDMA DMA Channel 30 Interrupt
+#define INT_CDMA_DMAC31		81	// CDMA DMA Channel 31 Interrupt
+#define INT_CDMA_DMAC32		82	// CDMA DMA Channel 32 Interrupt
+#define INT_CDMA_DMAC33		83	// CDMA DMA Channel 33 Interrupt
+#define INT_CDMA_DMAC34		84	// CDMA DMA Channel 34 Interrupt
+#define INT_CDMA_DMAC35		85	// CDMA DMA Channel 35 Interrupt
+#define INT_CDMA_DMAC36		86	// CDMA DMA Channel 36 Interrupt
+#define INT_CDMA_DMAC37		87	// CDMA DMA Channel 37 Interrupt
+#define INT_CDMA_DMAC38		88	// CDMA DMA Channel 38 Interrupt
+#define INT_CDMA_DMAC39		89	// CDMA DMA Channel 39 Interrupt
+#define INT_CDMA_DMAC40		90	// CDMA DMA Channel 40 Interrupt
+#define INT_CDMA_DMAC41		91	// CDMA DMA Channel 41 Interrupt
+#define INT_CDMA_DMAC42		92	// CDMA DMA Channel 42 Interrupt
+#define INT_CDMA_DMAC43		93	// CDMA DMA Channel 43 Interrupt
+#define INT_CDMA_DMAC44		94	// CDMA DMA Channel 44 Interrupt
+
+// Reserved 95 - 96
+
+// Audio and Highland Park Interrupts 97 - 115
+
+#define INT_AUDIO_CPU_IRQ0	97	// 
+#define INT_AUDIO_CPU_IRQ1	98	// 
+
+#define INT_HPERFNRT_DART	116	// HPerf-NRT DART Interrupt
+#define INT_HPERFRT_DART	117	// HPerf-RT DART Interrupt
+#define INT_JPG			118	// JPEG Interrupt
+#define INT_GPIO0		119	// GPIO 0 Interrupt
+#define INT_GPIO1		120	// GPIO 1 Interrupt
+#define INT_MCU			121	// MCU 0 Interrupt
+#define INT_MCU0		122	// MCU 0 Interrupt
+#define INT_MCU1		123	// MCU 1 Interrupt
+#define INT_PIO0		124	// PIO 0 Interrupt
+#define INT_PIO1		125	// PIO 1 Interrupt
+
+// Reserved 126
+
+#define INT_IOP_COMMRX		127	// IOP CommRx Interrupt
+#define INT_IOP_COMMTX		128	// IOP CommTx Interrupt
+#define INT_IOP_PMI		129	// IOP PerfMon Interrupt
+#define INT_IOP_CTIIRQ		130	// IOP CTIIRQ Interrupt
+#define INT_ISP_COMMRX		131	// IOP CommRx Interrupt
+#define INT_ISP_COMMTX		132	// IOP CommTx Interrupt
+#define INT_ISP_PMI		133	// IOP PerfMon Interrupt
+#define INT_ISP_CTIIRQ		134	// IOP CTIIRQ Interrupt
+
+#define INT_CPU0_PMI		135	// IOP Perfmon Interrupt
+#define INT_CPU0_CTIIRQ		136	// IOP CTI Interrupt
+#define INT_CPU0_COMMRX		137	// IOP CommRx Interrupt
+#define INT_CPU0_COMMTX		138	// IOP CommTx Interrupt
+#define INT_CPU1_PMI		139	// IOP PMI Interrupt
+#define INT_CPU1_CTIIRQ		140	// IOP CTI Interrupt
+#define INT_CPU1_COMMRX		141	// IOP CommRx Interrupt
+#define INT_CPU1_COMMTX		142	// IOP CommTx Interrupt
+
+#define INT_L2C			143	// PL310 Interrupt
+
+// Reserved 144 - 151
+
+#define INT_PMGR_PMI		152	// PMGR PerfMon Interrupt
+#define INT_HPERFNTR_PMI	153	// HPerf-NRT PerfMon Interrupt
+#define INT_HPERFRT_PMI		154	// HPerf-RT PerfMon Interrupt
+#define INT_DPIPE0_PMI		155	// Display Pipe 0 PerfMon Interrupt
+#define INT_DPIPE1_PMI		156	// Display Pipe 1 PerfMon Interrupt
+
+// Reserved 157 - 159
+
+#define INT_ETB_FULL		160	// ETB Full Interrupt
+
+#if PLATFORM_VARIANT_IOP
+
+#include <drivers/aic/aic.h>
+
+#define INT_HOST		INT_SW2			// Host processor doorbell
+#define INT_IOP			INT_SW3			// I/O coprocessor doorbell
+#define INT_IOP_NMI		kAIC_VEC_SW_TMR		// I/O coprocessor NMI
+
+#elif PLATFORM_VARIANT_AUDIO
+
+#include <drivers/audio/audio.h>
+
+#define INT_HOST		AE2_INT_SW0		// Host processor doorbell
+#define INT_IOP			AE2_INT_SW0		// I/O coprocessor doorbell
+#define INT_IOP_NMI		AE2_INT_SW1		// I/O coprocessor NMI
+
+#endif
+
+#endif /* ! __PLATFORM_SOC_HWISR_H */

platform/s5l8940x/include/platform/soc/hwregbase.h

@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2009-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWREGBASE_H
+#define __PLATFORM_SOC_HWREGBASE_H
+
+/* S5L8940X/S5L8942X/S5L8947X Reg Base Defs */
+
+#define AIC_VERSION 			0
+#define AIC_INT_COUNT			(192)
+#define PMGR_WDG_VERSION		0
+
+#if !SUB_PLATFORM_S5L8947X
+#define SDIO_BASE_ADDR			(0x30000000)
+
+#define SHA1_BASE_ADDR			(0x30100000)
+#endif
+
+#define SHA2_BASE_ADDR			(0x30200000)
+
+#define FMI0_BASE_ADDR			(0x31200000)
+#define FMI1_BASE_ADDR			(0x31300000)
+#define FMI2_BASE_ADDR			(0x31400000)
+#define FMI3_BASE_ADDR			(0x31500000)
+#define FMI_VERSION			(3)
+#if !SUB_PLATFORM_S5L8940X
+#define FMI_VERSION_MINOR		(1)
+#endif // SUB_PLATFORM_S5L8942X
+
+#if !SUB_PLATFORM_S5L8947X
+#define SPI0_BASE_ADDR			(0x32000000)
+#define SPI1_BASE_ADDR			(0x32100000)
+#define SPI2_BASE_ADDR			(0x32200000)
+#define SPI3_BASE_ADDR			(0x32300000)
+#define SPI4_BASE_ADDR			(0x32400000)
+#define SPI_VERSION			(1)
+#define SPIS_COUNT			(5)
+#else
+#define SPI0_BASE_ADDR			(0x32000000)
+#define SPI_VERSION			(1)
+#define SPIS_COUNT			(1)
+
+#define ADC_BASE_ADDR			(0x32100000)
+#endif
+
+#define UART_VERSION			(1)
+#define UART0_BASE_ADDR			(0x32500000)
+#define UART1_BASE_ADDR			(0x32600000)
+#define UART2_BASE_ADDR			(0x32700000)
+#define UART3_BASE_ADDR			(0x32800000)
+#define UART4_BASE_ADDR			(0x32900000)
+#if SUB_PLATFORM_S5L8947X
+#define UARTS_COUNT			(5)
+#elif SUB_PLATFORM_S5L8942X
+#define UART5_BASE_ADDR			(0x32A00000)
+#define UARTS_COUNT			(6)
+#elif SUB_PLATFORM_S5L8940X
+#define UART5_BASE_ADDR			(0x32A00000)
+#define UART6_BASE_ADDR			(0x32B00000)
+#define UARTS_COUNT			(7)
+#endif
+
+#define PKE_BASE_ADDR			(0x33100000)
+
+#define IIC_BASE_ADDR			(0x33200000)
+#define IIC_SPACING			(0x00100000)
+#define IICS_COUNT			(3)
+
+#define AUDIO_BASE_ADDR			(0x34000000)
+
+#define USBPHY_BASE_ADDR		(0x36000000)
+#if SUB_PLATFORM_S5L8940X
+#define USBPHY_VERSION			(3)
+#else
+#define USBPHY_VERSION			(4)
+#endif
+
+#define USBOTG_BASE_ADDR		(0x36100000)
+#define UPERF_WIDGETS_BASE_ADDR		(0x36E00000)
+#define UPERF_PL301_BASE_ADDR		(0x36F00000)
+
+#define CDMA_BASE_ADDR			(0x37000000)
+#define CDMA_VERSION			3
+
+#if !SUB_PLATFORM_S5L8947X
+#define VENC_BASE_ADDR			(0x38000000)
+#endif
+
+#define VDEC_BASE_ADDR			(0x38100000)
+
+#define JPEG_BASE_ADDR			(0x38200000)
+
+#define SCALER_BASE_ADDR		(0x38300000)
+#define SCALER_SPACING			(0x00100000)
+
+#define NRT_DART_BASE_ADDR		(0x38B00000)
+#define NRT_DART_WIDGETS_BASE_ADDR	(0x38C00000)
+#define NRT_DART_PL301_BASE_ADDR	(0x38D00000)
+#define NRT_TOP_WIDGETS_BASE_ADDR	(0x38E00000)
+#define NRT_TOP_PL301_BASE_ADDR		(0x38F00000)
+
+#define CLCD_BASE_ADDR			(0x39200000)
+#define CLCD_VERSION			(0)
+#define CLCD_DITHER_BASE_ADDR		(0x39300000)
+#define DITHER_VERSION			(1)
+
+#define TVOUT_BASE_ADDR			(0x39400000)
+
+#if !SUB_PLATFORM_S5L8947X
+#define DSIM_BASE_ADDR			(0x39500000)
+#define DSIM_LANE_COUNT			(4)
+#define DSIM_VERSION			(1)
+#endif
+
+#define RGBOUT_BASE_ADDR		(0x39600000)
+
+#if !SUB_PLATFORM_S5L8947X
+#define DP_BASE_ADDR			(0x39700000)
+#define DISPLAYPORT_VERSION		(1)
+#else
+#define HDMI_BASE_ADDR			(0x39700000)
+#define DPBDITHER_BASE_ADDR		(0x39800000)
+#endif
+
+#if !SUB_PLATFORM_S5L8947X
+#define ISP_BASE_ADDR			(0x3A000000)
+
+#define DISP0_BASE_ADDR			(0x3A100000)
+#define CLCD_DISPLAYPIPE_BASE_ADDR	(DISP0_BASE_ADDR)
+#endif
+#define DISP1_BASE_ADDR			(0x3A200000)
+#define RGBOUT_DISPLAYPIPE_BASE_ADDR	(DISP1_BASE_ADDR)
+#define DISP_VERSION			(3)
+
+#if !SUB_PLATFORM_S5L8947X
+#define RT_DART_BASE_ADDR		(0x3A400000)
+#endif
+#define RT_TOP_WIDGETS_BASE_ADDR	(0x3A500000)
+#define RT_TOP_PL301_BASE_ADDR		(0x3A600000)
+
+#if SUB_PLATFORM_S5L8947X
+#define ETHERNET_BASE_ADDR		(0x3B000000)
+#else
+#define HP_BASE_ADDR			(0x3B000000)
+#endif
+
+#if SUB_PLATFORM_S5L8947X
+#define AMP_BASE_ADDR			(0x3D000000)
+#define AMP_SPACING			(0x00100000)
+#else
+#define AMG_BASE_ADDR			(0x3D000000)
+#define AMG_SPACING			(0x00100000)
+#endif
+
+#define PL310_BASE_ADDR			(0x3E000000)
+#define SCU_BASE_ADDR			(0x3E100000)
+
+#define PMGR_BASE_ADDR			(0x3F100000)
+#define AIC_BASE_ADDR			(0x3F200000)
+
+#define IOP_BASE_ADDR			(0x3F300000)
+
+#define ROSC_BASE_ADDR			(0x3F400000)
+#define ROSC_MASK			(0x57FF)
+#define ROSC_WITH_CLOCK			(0)
+
+#define CHIPID_BASE_ADDR		(0x3F500000)
+
+#define SWI_BASE_ADDR			(0x3F600000)
+#if !SUB_PLATFORM_S5L8947X
+#define DWI_BASE_ADDR			(0x3F700000)
+#endif
+
+#define AMC_BASE_ADDR			(0x3F800000)
+
+#define GPIO_BASE_ADDR			(0x3FA00000)
+#define GPIO_VERSION			(1)
+#if SUB_PLATFORM_S5L8940X
+#define GPIO_GROUP_COUNT		(29)
+#elif SUB_PLATFORM_S5L8942X
+#define GPIO_GROUP_COUNT		(26)
+#elif SUB_PLATFORM_S5L8947X
+#define GPIO_GROUP_COUNT		(18)
+#endif
+#define GPIO_PAD_SPI			(GPIO_GROUP_COUNT)
+
+#define PIO_BASE_ADDR			(0x3FB00000)
+#define PIO_SPACING			(0x00100000)
+
+#define CIF_BASE_ADDR			(0x3FD00000)
+
+#define CDIO_WIDGETS_BASE_ADDR		(0x3FE00000)
+#define CDIO_PL301_BASE_ADDR		(0x3FF00000)
+
+#endif /* ! __PLATFORM_SOC_HWREGBASE_H */

platform/s5l8940x/include/platform/soc/miu.h

@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2009-2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_MIU_H
+#define __PLATFORM_SOC_MIU_H
+
+#include <lib/devicetree.h>
+#include <platform/soc/hwregbase.h>
+
+#define	rREMAP_CTL			(*(volatile u_int32_t *)(PIO_BASE_ADDR + 0x0000))
+
+#define rPL310_CONTROL			(*(volatile u_int32_t *)(PL310_BASE_ADDR + 0x0100))
+#define rPL310_INVAL_WAY		(*(volatile u_int32_t *)(PL310_BASE_ADDR + 0x077C))
+#define rPL310_FILTER_START		(*(volatile u_int32_t *)(PL310_BASE_ADDR + 0x0C00))
+#define rPL310_FILTER_END		(*(volatile u_int32_t *)(PL310_BASE_ADDR + 0x0C04))
+
+#define rSCU_CONTROL			(*(volatile u_int32_t *)(SCU_BASE_ADDR + 0x0000))
+#define rSCU_POWER_STATUS		(*(volatile u_int32_t *)(SCU_BASE_ADDR + 0x0008))
+#define rSCU_TAG_INVAL			(*(volatile u_int32_t *)(SCU_BASE_ADDR + 0x000C))
+
+#define rCIF_CONTROL			(*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0000))
+#define rCIF_CLKGATE			(*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0004))
+#define rCIF_RTLIMIT			(*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0008))
+#define rCIF_WTLIMIT			(*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x000C))
+#define rCIF_IDLETMR			(*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0010))
+#define rCIF_RDREMAP			(*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0040))
+#define rCIF_WRREMAP			(*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0044))
+
+#define  CDIO_IOP_RTLIMIT		(0x0008)
+#define rCDIO_IOP_RTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_RTLIMIT))
+#define  CDIO_IOP_WTLIMIT		(0x000C)
+#define rCDIO_IOP_WTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_WTLIMIT))
+#define  CDIO_IOP_WREQSP		(0x001C)
+#define rCDIO_IOP_WREQSP		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_WREQSP))
+#define  CDIO_CDMA_RTLIMIT		(0x0028)
+#define rCDIO_CDMA_RTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_CDMA_RTLIMIT))
+#define  CDIO_CDMA_WTLIMIT		(0x002C)
+#define rCDIO_CDMA_WTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_CDMA_WTLIMIT))
+#define  CDIO_CDMA_WGATHER		(0x0030)
+#define rCDIO_CDMA_WGATHER		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_CDMA_WGATHER))
+#define  CDIO_UPERF_RTLIMIT		(0x0048)
+#define rCDIO_UPERF_RTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPERF_RTLIMIT))
+#define  CDIO_UPERF_WTLIMIT		(0x004C)
+#define rCDIO_UPERF_WTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPERF_WTLIMIT))
+#define  CDIO_UPERF_WGATHER		(0x0050)
+#define rCDIO_UPERF_WGATHER		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPERF_WGATHER))
+#define  CDIO_AUDIO_RTLIMIT		(0x0068)
+#define rCDIO_AUDIO_RTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_AUDIO_RTLIMIT))
+#define  CDIO_AUDIO_WTLIMIT		(0x006C)
+#define rCDIO_AUDIO_WTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_AUDIO_WTLIMIT))
+#define  CDIO_AUDIO_WGATHER		(0x0070)
+#define rCDIO_AUDIO_WGATHER		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_AUDIO_WGATHER))
+#define  CDIO_PIO_RTLIMIT		(0x00A8)
+#define rCDIO_PIO_RTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_PIO_RTLIMIT))
+#define  CDIO_PIO_WTLIMIT		(0x00AC)
+#define rCDIO_PIO_WTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_PIO_WTLIMIT))
+
+#define  CDIO_AR_CHAN_ARB_MI0		(0x0408)
+#define rCDIO_AR_CHAN_ARB_MI0		(*(volatile u_int32_t *)(CDIO_PL301_BASE_ADDR + CDIO_AR_CHAN_ARB_MI0))
+#define  CDIO_AW_CHAN_ARB_MI0		(0x040C)
+#define rCDIO_AW_CHAN_ARB_MI0		(*(volatile u_int32_t *)(CDIO_PL301_BASE_ADDR + CDIO_AW_CHAN_ARB_MI0))
+#define  CDIO_AR_CHAN_ARB_MI1		(0x0428)
+#define rCDIO_AR_CHAN_ARB_MI1		(*(volatile u_int32_t *)(CDIO_PL301_BASE_ADDR + CDIO_AR_CHAN_ARB_MI1))
+#define  CDIO_AW_CHAN_ARB_MI1		(0x042C)
+#define rCDIO_AW_CHAN_ARB_MI1		(*(volatile u_int32_t *)(CDIO_PL301_BASE_ADDR + CDIO_AW_CHAN_ARB_MI1))
+
+#define  UPERF_OTG_QOS			(0x0014)
+#define rUPERF_OTG_QOS			(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OTG_QOS))
+#define  UPERF_OTG_CACHE		(0x0018)
+#define rUPERF_OTG_CACHE		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OTG_CACHE))
+#define  UPERF_EHCI_QOS			(0x0034)
+#define rUPERF_EHCI_QOS			(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_EHCI_QOS))
+#define  UPERF_EHCI_CACHE		(0x0038)
+#define rUPERF_EHCI_CACHE		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_EHCI_CACHE))
+#define  UPERF_OHCI0_QOS		(0x0054)
+#define rUPERF_OHCI0_QOS		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OHCI0_QOS))
+#define  UPERF_OHCI0_CACHE		(0x0058)
+#define rUPERF_OHCI0_CACHE		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OHCI0_CACHE))
+#define  UPERF_OHCI1_QOS		(0x0074)
+#define rUPERF_OHCI1_QOS		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OHCI1_QOS))
+#define  UPERF_OHCI1_CACHE		(0x0078)
+#define rUPERF_OHCI1_CACHE		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OHCI1_CACHE))
+
+#define  HPERF_NRT_DART_DART_RTLIMIT	(0x0004)
+#define rHPERF_NRT_DART_DART_RTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_DART_RTLIMIT))
+#define  HPERF_NRT_DART_DART_WTLIMIT	(0x0008)
+#define rHPERF_NRT_DART_DART_WTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_DART_WTLIMIT))
+#define  HPERF_NRT_DART_JPEG0_QOS	(0x000C)
+#define rHPERF_NRT_DART_JPEG0_QOS	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_JPEG0_QOS))
+#define  HPERF_NRT_DART_JPEG1_QOS	(0x0010)
+#define rHPERF_NRT_DART_JPEG1_QOS	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_JPEG1_QOS))
+#define  HPERF_NRT_DART_SCALER0_RTLIMIT	(0x001C)
+#define rHPERF_NRT_DART_SCALER0_RTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_SCALER0_RTLIMIT))
+#define  HPERF_NRT_DART_SCALER0_WTLIMIT	(0x0020)
+#define rHPERF_NRT_DART_SCALER0_WTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_SCALER0_WTLIMIT))
+#define  HPERF_NRT_DART_SCALER1_RTLIMIT	(0x0030)
+#define rHPERF_NRT_DART_SCALER1_RTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_SCALER1_RTLIMIT))
+#define  HPERF_NRT_DART_SCALER1_WTLIMIT	(0x0034)
+#define rHPERF_NRT_DART_SCALER1_WTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_SCALER1_WTLIMIT))
+
+#define  HPERF_NRT_DART_AR_CHAN_ARB_MI	(0x0408)
+#define rHPERF_NRT_DART_AR_CHAN_ARB_MI	(*(volatile u_int32_t *)(NRT_DART_PL301_BASE_ADDR + HPERF_NRT_DART_AR_CHAN_ARB_MI0))
+#define  HPERF_NRT_DART_AW_CHAN_ARB_MI	(0x040C)
+#define rHPERF_NRT_DART_AW_CHAN_ARB_MI	(*(volatile u_int32_t *)(NRT_DART_PL301_BASE_ADDR + HPERF_NRT_DART_AW_CHAN_ARB_MI0))
+
+#define  HPERF_NRT_TOP_TOP_RTLIMIT	(0x0000)
+#define rHPERF_NRT_TOP_TOP_RTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_TOP_RTLIMIT))
+#define  HPERF_NRT_TOP_TOP_WTLIMIT	(0x0004)
+#define rHPERF_NRT_TOP_TOP_WTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_TOP_WTLIMIT))
+#define  HPERF_NRT_TOP_VENC_RTLIMIT	(0x0010)
+#define rHPERF_NRT_TOP_VENC_RTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VENC_RTLIMIT))
+#define  HPERF_NRT_TOP_VENC_WTLIMIT	(0x0014)
+#define rHPERF_NRT_TOP_VENC_WTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VENC_WTLIMIT))
+#define  HPERF_NRT_TOP_VENC_WREQSP	(0x0018)
+#define rHPERF_NRT_TOP_VENC_WREQSP	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VENC_WREQSP))
+#define  HPERF_NRT_TOP_VDEC_RTLIMIT	(0x0028)
+#define rHPERF_NRT_TOP_VDEC_RTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VDEC_RTLIMIT))
+#define  HPERF_NRT_TOP_VDEC_WTLIMIT	(0x002C)
+#define rHPERF_NRT_TOP_VDEC_WTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VDEC_WTLIMIT))
+#define  HPERF_NRT_TOP_VDEC_WREQSP	(0x0030)
+#define rHPERF_NRT_TOP_VDEC_WREQSP	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VDEC_WREQSP))
+#define  HPERF_NRT_TOP_DART_WGATHER	(0x0048)
+#define rHPERF_NRT_TOP_DART_WGATHER	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_DART_WGATHER))
+
+#define  HPERF_NRT_TOP_AR_CHAN_ARB_MI	(0x0408)
+#define rHPERF_NRT_TOP_AR_CHAN_ARB_MI	(*(volatile u_int32_t *)(NRT_TOP_PL301_BASE_ADDR + HPERF_NRT_TOP_AR_CHAN_ARB_MI0))
+#define  HPERF_NRT_TOP_AW_CHAN_ARB_MI	(0x040C)
+#define rHPERF_NRT_TOP_AW_CHAN_ARB_MI	(*(volatile u_int32_t *)(NRT_TOP_PL301_BASE_ADDR + HPERF_NRT_TOP_AW_CHAN_ARB_MI0))
+
+#define  HPERF_RT_TOP_DISP0_RTLIMIT	(0x0004)
+#define rHPERF_RT_TOP_DISP0_RTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_DISP0_RTLIMIT))
+#define  HPERF_RT_TOP_DISP1_RTLIMIT	(0x000C)
+#define rHPERF_RT_TOP_DISP1_RTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_DISP1_RTLIMIT))
+#define  HPERF_RT_TOP_ISP_RTLIMIT	(0x0018)
+#define rHPERF_RT_TOP_ISP_RTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_ISP_WTLIMIT))
+#define  HPERF_RT_TOP_ISP_WTLIMIT	(0x001C)
+#define rHPERF_RT_TOP_ISP_WTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_ISP_RTLIMIT))
+#define  HPERF_RT_TOP_TOP_RTLIMIT	(0x0020)
+#define rHPERF_RT_TOP_TOP_RTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_TOP_WTLIMIT))
+#define  HPERF_RT_TOP_TOP_WTLIMIT	(0x0024)
+#define rHPERF_RT_TOP_TOP_WTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_TOP_RTLIMIT))
+
+#define  HPERF_RT_TOP_AR_CHAN_ARB_MI	(0x0408)
+#define rHPERF_RT_TOP_AR_CHAN_ARB_MI	(*(volatile u_int32_t *)(RT_TOP_PL301_BASE_ADDR + HPERF_RT_TOP_AR_CHAN_ARB_MI0))
+#define  HPERF_RT_TOP_AW_CHAN_ARB_MI	(0x040C)
+#define rHPERF_RT_TOP_AW_CHAN_ARB_MI	(*(volatile u_int32_t *)(RT_TOP_PL301_BASE_ADDR + HPERF_RT_TOP_AW_CHAN_ARB_MI0))
+
+
+enum remap_select {
+  REMAP_SRAM = 0,
+  REMAP_SDRAM
+};
+
+extern void miu_select_remap(enum remap_select sel);
+extern void miu_bypass_prep(void);
+extern void miu_update_device_tree(DTNode *pmgr_node);
+
+#endif /* ! __PLATFORM_SOC_MIU_H */

platform/s5l8940x/include/platform/soc/pmgr.h

@@ -0,0 +1,465 @@
+/*
+ * Copyright (C) 2009-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_PMGR_H
+#define __PLATFORM_SOC_PMGR_H
+
+#include <lib/devicetree.h>
+#include <platform/soc/hwregbase.h>
+
+#define	rPMGR_PLL0_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0000))
+#define	rPMGR_PLL0_PARAM		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0004))
+#define	rPMGR_PLL1_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0008))
+#define	rPMGR_PLL1_PARAM		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x000C))
+#define	rPMGR_PLL2_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0010))
+#define	rPMGR_PLL2_PARAM		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0014))
+#define	rPMGR_PLL3_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0018))
+#define	rPMGR_PLL3_PARAM		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x001C))
+#define	rPMGR_PLL4_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0020))
+#define	rPMGR_PLL4_PARAM		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0024))
+#define	rPMGR_PLLUSB_CTL		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0028))
+#define	rPMGR_PLLUSB_PARAM		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x002C))
+
+#define	rPMGR_PLL_ENABLE			(1 << 31)
+#define	rPMGR_PLL_EXT_BYPASS			(1 << 30)
+#define	rPMGR_PLL_REAL_LOCK			(1 << 29)
+#define	rPMGR_PLL_LOAD				(1 << 27)
+#define	rPMGR_PLL_BYPASS			(1 << 23)
+#define	rPMGR_PLL_P(_p)				(((_p) & 0x03f) << 14)
+#if (SUB_PLATFORM_S5L8942X || SUB_PLATFORM_S5L8947X)
+#define rPMGR_PLL_VSEL(_p)			(((_p) & 1) << 13)
+#endif
+#define	rPMGR_PLL_M(_m)				(((_m) & 0x3ff) <<  3)
+#define	rPMGR_PLL_S(_s)				(((_s) & 0x007) <<  0)
+
+#define rPMGR_PARAM_EXT_AFC(_n)			((_n) << 17)
+#define rPMGR_PARAM_AFC_EN			(1 << 16)
+#define rPMGR_PARAM_LOCK_TIME(_n)		((_n) << 0)
+
+#define	rPMGR_PLL_GATES			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0030))
+
+#define	rPMGR_DOUBLER_CTL		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0034))
+
+#define	rPMGR_DOUBLER_ENABLE			(1 << 31)
+#define	rPMGR_DOUBLER_EXT_BYPASS		(1 << 30)
+
+#define	rPMGR_CPU_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0038))
+#define	rPMGR_MCU_FIXED_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x003C))
+#define	rPMGR_MCU_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0040))
+#define	rPMGR_PCLK1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0044))
+
+#define	rPMGR_PREDIV0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0048))
+#define	rPMGR_PREDIV1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x004C))
+#define	rPMGR_PREDIV2_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0050))
+#define	rPMGR_PREDIV3_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0054))
+#define	rPMGR_PREDIV4_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0058))
+#define	rPMGR_PREDIV5_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x005C))
+#define	rPMGR_PREDIV6_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0060))
+
+#define	rPMGR_MANAGED0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0064))
+#define	rPMGR_MANAGED1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0068))
+#define	rPMGR_MANAGED2_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x006C))
+#define	rPMGR_MANAGED3_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0070))
+#define	rPMGR_MANAGED4_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0074))
+
+#define	rPMGR_VID1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0078))
+#define	rPMGR_MEDIUM0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x007C))
+#define	rPMGR_VID0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0080))
+#define	rPMGR_I2C_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0084))
+#define	rPMGR_SDIO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0088))
+#define	rPMGR_MIPI_DSI_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x008C))
+#define	rPMGR_AUDIO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0090))
+#define	rPMGR_HPARK_PCLK0_CLK_CFG	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0094))
+#define	rPMGR_HPARK_TCLK_CLK_CFG	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0098))
+#define	rPMGR_UPERF_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x009C))
+#define	rPMGR_DEBUG_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00A0))
+
+#define	rPMGR_HPERFRT_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00A4))
+#define	rPMGR_GFX_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00A8))
+#define	rPMGR_GFX_SLC_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00AC))
+
+#define	rPMGR_HPERFNRT_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00B0))
+#define	rPMGR_ISP_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00B4))
+#define	rPMGR_IOP_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00B8))
+#define	rPMGR_CDIO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00BC))
+
+#define	rPMGR_LPERFS_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00C0))
+#define	rPMGR_PCLK0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00C4))
+#define	rPMGR_PCLK2_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00C8))
+#define	rPMGR_PCLK3_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00CC))
+
+#define	rPMGR_MEDIUM1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00D0))
+#define	rPMGR_SPI0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00D4))
+#define	rPMGR_SPI1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00D8))
+#define	rPMGR_SPI2_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00DC))
+#define	rPMGR_SPI3_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00E0))
+#define	rPMGR_SPI4_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00E4))
+#define	rPMGR_SLEEP_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00E8))
+#define	rPMGR_USBPHY_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00EC))
+#define	rPMGR_USBOHCI_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00F0))
+#define	rPMGR_USB12_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00F4))
+#define	rPMGR_NCO_REF0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00F8))
+#define	rPMGR_NCO_REF1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00FC))
+#define	rPMGR_VENC_MTX_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0100))
+#define	rPMGR_VENC_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0104))
+
+#define	PMGR_FIRST_CLK_CFG		(&rPMGR_CPU_CLK_CFG)
+#define	PMGR_LAST_CLK_CFG		(&rPMGR_VENC_CLK_CFG)
+#define	PMGR_CLK_CFG_COUNT		(((((u_int32_t)(PMGR_LAST_CLK_CFG)) - ((u_int32_t)(PMGR_FIRST_CLK_CFG))) / 4) + 1)
+#define	PMGR_CLK_NUM(_r)		(((u_int32_t)&(rPMGR_ ## _r ## _CLK_CFG) - ((u_int32_t)(PMGR_FIRST_CLK_CFG))) / 4)
+
+#define	rPMGR_I2S0_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0110))
+#define	rPMGR_I2S0_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0114))
+#define	rPMGR_I2S0_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0118))
+
+#define	rPMGR_I2S1_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0120))
+#define	rPMGR_I2S1_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0124))
+#define	rPMGR_I2S1_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0128))
+
+#define	rPMGR_I2S2_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0130))
+#define	rPMGR_I2S2_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0134))
+#define	rPMGR_I2S2_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0138))
+
+#define	rPMGR_I2S3_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0140))
+#define	rPMGR_I2S3_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0144))
+#define	rPMGR_I2S3_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0148))
+
+#define	rPMGR_SPDIF_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0150))
+#define	rPMGR_SPDIF_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0154))
+#define	rPMGR_SPDIF_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0158))
+
+#define	rPMGR_DP_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0160))
+#define	rPMGR_DP_NCO_N1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0164))
+#define	rPMGR_DP_NCO_N2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0168))
+
+#define	rPMGR_MCA0_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0170))
+#define	rPMGR_MCA0_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0174))
+#define	rPMGR_MCA0_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0178))
+
+#define	rPMGR_CLK_CFG_ENABLE			(1 << 31)
+#define	rPMGR_CLK_CFG_PENDING			(1 << 30)
+#define	rPMGR_CLK_CFG_SRC_SEL(_s)		(((_s) & 0x3) << 28)
+#define	rPMGR_CLK_CFG_SRC_SEL_MASK		rPMGR_CLK_CFG_SRC_SEL(3)
+#define	rPMGR_CLK_CFG_DIVIDER(_d)		(((_d) & 0x1f) << 0)
+#define	rPMGR_CLK_CFG_DIV_MASK			rPMGR_CLK_CFG_DIVIDER(0x1f)
+
+#define	PMGR_PERF_STATE_COUNT		(16)
+#define	rPMGR_PERF_STATE_A(_s)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0200 + ((_s) * 0x10)))
+#define	rPMGR_PERF_STATE_B(_s)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0204 + ((_s) * 0x10)))
+#define	rPMGR_PERF_STATE_C(_s)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0208 + ((_s) * 0x10)))
+#define	rPMGR_PERF_STATE_CTL		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0300))
+
+#define	PMGR_PERF_STATE_SEL(_s)			(((_s) & 0xF) << 0)
+#define	PMGR_PERF_STATE_PENDING			(0xFF << 16)
+
+#define	kPERF_STATE_BYPASS			(0)
+#define	kPERF_STATE_SECUREROM			(1)
+#define	kPERF_STATE_IBOOT			(2)
+#define	kPERF_STATE_IBOOT_CNT			(5)
+
+#define	rPMGR_MCU_CLK_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0400))
+
+#define	rPMGR_CPU0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1008))
+#define	rPMGR_CPU1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x100C))
+#define	rPMGR_SCU_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1010))
+#define	rPMGR_L2RAM0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1014))
+#define	rPMGR_L2RAM1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1018))
+#define	rPMGR_CPU_REGS_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x101C))
+#define	rPMGR_MCU_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1020))
+#define	rPMGR_GFX_SYS_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1024))
+#define	rPMGR_GFX_CORES_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1028))
+#define	rPMGR_HPERFNRT_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x102C))
+#define	rPMGR_VDEC_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1030))
+#define	rPMGR_SCALER0_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1034))
+#define	rPMGR_SCALER1_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1038))
+#define	rPMGR_JPG_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x103C))
+#define	rPMGR_VENCD_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1040))
+#define	rPMGR_HPERFRT_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1044))
+#define	rPMGR_ISP_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1048))
+#define	rPMGR_DISP0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1054))
+#define	rPMGR_DISP1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1058))
+#define	rPMGR_DISPOUT_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x105C))
+#define	rPMGR_MIPI_DSI_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1060))
+#define	rPMGR_CLCD_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1064))
+#define	rPMGR_TVOUT_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1068))
+#define	rPMGR_RGBOUT_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x106C))
+#define	rPMGR_DPLINK_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1070))
+#define	rPMGR_CDIO_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1074))
+#define	rPMGR_CDMA_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1078))
+#define	rPMGR_IOP_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x107C))
+#define	rPMGR_UPERF_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1080))
+#define	rPMGR_USBOTG0_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1084))
+#define	rPMGR_USB20_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1088))
+#define	rPMGR_USB11_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x108C))
+#define	rPMGR_USBOHCI0_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1090))
+#define	rPMGR_USBOHCI1_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1094))
+#define	rPMGR_USBREG_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1098))
+#define	rPMGR_AUDIO_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x109C))
+#define	rPMGR_I2S0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10A0))
+#define	rPMGR_I2S1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10A4))
+#define	rPMGR_I2S2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10A8))
+#define	rPMGR_I2S3_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10AC))
+#define	rPMGR_SPDIF_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10B0))
+#define	rPMGR_HPARK_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10B4))
+#define	rPMGR_SDIO_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10B8))
+#define	rPMGR_SHA1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10BC))
+#define	rPMGR_SHA2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10C0))
+#define	rPMGR_FMI0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10C4))
+#define	rPMGR_FMI0BCH_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10C8))
+#define	rPMGR_FMI1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10CC))
+#define	rPMGR_FMI1BCH_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10D0))
+#define	rPMGR_FMI2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10D4))
+#define	rPMGR_FMI2BCH_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10D8))
+#define	rPMGR_FMI3_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10DC))
+#define	rPMGR_FMI3BCH_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10E0))
+#define	rPMGR_SPI0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10E4))
+#define	rPMGR_SPI1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10E8))
+#define	rPMGR_SPI2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10EC))
+#define	rPMGR_SPI3_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10F0))
+#define	rPMGR_SPI4_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10F4))
+#define	rPMGR_UART0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10F8))
+#define	rPMGR_UART1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10FC))
+#define	rPMGR_UART2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1100))
+#define	rPMGR_UART3_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1104))
+#define	rPMGR_UART4_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1108))
+#define	rPMGR_UART5_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x110C))
+#define	rPMGR_UART6_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1110))
+#define	rPMGR_PKE_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1114))
+#define	rPMGR_I2C0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1118))
+#define	rPMGR_I2C1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x111C))
+#define	rPMGR_I2C2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1120))
+#define	rPMGR_PWM_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1124))
+#define	rPMGR_SCRT_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1128))
+#define	rPMGR_GPIO_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x112C))
+#define	rPMGR_SWI_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1130))
+#define	rPMGR_DWI_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1134))
+#define	rPMGR_DEBUG_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1138))
+#define	rPMGR_AIC_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x113C))
+#define	rPMGR_MCA0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1140))
+#ifdef SUB_PLATFORM_S5L8947X
+#define	rPMGR_ETH_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1144))
+#define	rPMGR_HDMI_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1148))
+#define	rPMGR_ADC_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x114C))
+#define	rPMGR_USBOTG1_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1150))
+#define	rPMGR_USB20_1_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1154))
+#define	rPMGR_USBOHCI0_1_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1158))
+#define	rPMGR_USBREG1_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x115C))
+#endif
+#define rPMGR_PS_RESET				(1 << 31)
+
+#define	PMGR_FIRST_PS			(&rPMGR_CPU0_PS)
+#if SUB_PLATFORM_S5L8942X
+#define	PMGR_LAST_PS			(&rPMGR_MCA0_PS)
+#elif SUB_PLATFORM_S5L8947X
+#define	PMGR_LAST_PS			(&rPMGR_USBREG1_PS)
+#else
+#define	PMGR_LAST_PS			(&rPMGR_AIC_PS)
+#endif
+#define	PMGR_DEV_PS_COUNT		(((((u_int32_t)(PMGR_LAST_PS)) - ((u_int32_t)(PMGR_FIRST_PS))) / 4) + 1)
+#define	PMGR_PS_NUM(_r)			(((u_int32_t)&(rPMGR_ ## _r ## _PS) - ((u_int32_t)(PMGR_FIRST_PS))) / 4)
+
+#define	rPMGR_CPU_CFG			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1180))
+
+#define	rPMGR_PWR_GATE_CTL_SET		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1200))
+#define	rPMGR_PWR_GATE_CTL_CLR		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1204))
+#define	rPMGR_PWR_GATE_IOP			(1 << 6)
+#define	rPMGR_PWR_GATE_GFX_MODE		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1208))
+
+#define	rPMGR_CORE_OFFLINE_SET		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1210))
+#define	rPMGR_CORE_OFFLINE_CLR		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1214))
+#define	rPMGR_WAKE_CORES		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1220))
+
+#define	PMGR_PWR_GATE_TIME_COUNT	(15)
+#define	rPMGR_PWR_GATE_TIME_A(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1238 + ((_n) * 8)))
+#define	rPMGR_PWR_GATE_TIME_B(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x123C + ((_n) * 8)))
+#define	rPMGR_PWR_GATE_DBG0		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x12E0))
+#define	rPMGR_PWR_GATE_DBG1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x12E4))
+
+#define	rPMGR_TEST_CLK			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2000))
+#define	rPMGR_PLL0_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2010))
+#define	rPMGR_PLL1_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2014))
+#define	rPMGR_PLL2_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2018))
+#define	rPMGR_PLL3_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x201C))
+#define	rPMGR_PLL4_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2020))
+#define	rPMGR_PLLUSB_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2024))
+#define	rPMGR_DOUBLER_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2028))
+
+#define	rPMGR_PLL0_TUNE			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2080))
+#define	rPMGR_PLL1_TUNE			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2084))
+#define	rPMGR_PLL2_TUNE			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2088))
+#define	rPMGR_PLL3_TUNE			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x208C))
+#define	rPMGR_PLL4_TUNE			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2090))
+#define	rPMGR_PLLUSB_TUNE		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2094))
+
+#define rPMGR_PLL_DEBUG_ENABLED			(1 << 31)
+#define rPMGR_PLL_DEBUG_BYP_ENABLED		(1 << 30)
+#define rPMGR_PLL_DEBUG_DBG_STPCLK_EN		(1 << 24)
+#define rPMGR_PLL_DEBUG_LOST_LOCK		(1 << 16)
+#define rPMGR_PLL_DEBUG_STATE(_r)		(((_r) >> 0) & 0xff)
+
+#define rPMGR_EMA_CTL_CPU		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2100))
+#define rPMGR_EMA_CTL_CPU_SPIN			(0x01 << 16)
+#define rPMGR_EMA_CTL_SOC		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2104))
+#define rPMGR_EMA_CTL_SOC_SEL			(0x1f << 0)
+#define rPMGR_EMA_CTL_SOC_SPIN			(0x01 << 16)
+
+#define	rPMGR_SRAM_EMA_B0_Pn_LO(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2120 + ((_n) * 8)))
+#define	rPMGR_SRAM_EMA_B0_Pn_HI(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2124 + ((_n) * 8)))
+#define	rPMGR_SRAM_EMA_B1_Pn_LO(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x21C0 + ((_n) * 8)))
+#define	rPMGR_SRAM_EMA_B1_Pn_HI(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x21C4 + ((_n) * 8)))
+#if (SUB_PLATFORM_S5L8942X || SUB_PLATFORM_S5L8947X)
+#define	rPMGR_SRAM_EMA_B2_Pn_LO(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2200 + ((_n) * 8)))
+#define	rPMGR_SRAM_EMA_B2_Pn_HI(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2204 + ((_n) * 8)))
+#endif
+
+enum {
+  EMA_CPU = 0,
+  EMA_MCU = 1,
+  EMA_GFX_PIPES_SYS = 2,
+  EMA_GFX_HYDRA = 3,
+  EMA_VDEC = 4,
+  EMA_VENC = 5,
+  EMA_ISP = 6,
+  EMA_DISP = 7,
+  EMA_NRT = 8,
+  EMA_CIF = 9,
+  EMA_IOP = 10,
+  EMA_SAUDIO = 11,
+  EMA_CDMA = 12,
+  EMA_FMI = 13,
+  EMA_HPARK = 14,
+};
+
+#define	rPMGR_WDOG_TMR			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3020))
+#define	rPMGR_WDOG_RST			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3024))
+#define	rPMGR_WDOG_INT			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3028))
+#define	rPMGR_WDOG_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x302C))
+
+#define	rPMGR_EVENT_TMR			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3100))
+#define	rPMGR_EVENT_PERIOD		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3104))
+#define	rPMGR_EVENT_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3108))
+
+#define	rPMGR_PERF_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4000))
+#define	rPMGR_PERF_STATUS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4004))
+#define	rPMGR_PERF_CTR0_LO		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4020))
+#define	rPMGR_PERF_CTR0_HI		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4024))
+#define	rPMGR_PERF_CFG0_LO		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4028))
+#define	rPMGR_PERF_CFG0_MID		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x402C))
+#define	rPMGR_PERF_CFG0_HI		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4030))
+#define	rPMGR_PERF_CTR1_LO		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4040))
+#define	rPMGR_PERF_CTR1_HI		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4044))
+#define	rPMGR_PERF_CFG1_LO		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4048))
+#define	rPMGR_PERF_CFG1_MID		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x404C))
+#define	rPMGR_PERF_CFG1_HI		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4050))
+
+#define	rPMGR_SCRATCH0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6000))
+#define	rPMGR_SCRATCH1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6004))
+#define	rPMGR_SCRATCH2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6008))
+#define	rPMGR_SCRATCH3			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x600C))
+#define	rPMGR_SCRATCH4			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6010))
+#define	rPMGR_SCRATCH5			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6014))
+#define	rPMGR_SCRATCH6			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6018))
+#define	rPMGR_SCRATCH7			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x601C))
+#define	rPMGR_SCRATCH8			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6020))
+#define	rPMGR_SCRATCH9			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6024))
+#define	rPMGR_SCRATCH10			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6028))
+#define	rPMGR_SCRATCH11			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x602C))
+#define	rPMGR_SCRATCH12			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6030))
+#define	rPMGR_SCRATCH13			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6034))
+#define	rPMGR_SCRATCH14			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6038))
+#define	rPMGR_SCRATCH15			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x603C))
+
+#define	rPMGR_DAC_FS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x7000))
+
+#define	rPMGR_USB_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x8000))
+
+#define	rPMGR_SHA_SEL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x9000))
+
+#define	rPMGR_SECURITY			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xA000))
+
+#define	rPMGR_GFX_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xB000))
+
+#define PGMR_GET_PERF_STATE_INDEX(_n, _x)	(((_x) >> ((_n) * 4)) & 0xF)
+#define PGMR_SET_PERF_STATE_INDEX(_n, _i)	(((_i) & 0xF) << ((_n) * 4))
+#define PMGR_PERF_STATE_V(_n)			(_n)
+#define PMGR_PERF_STATE_P			(3)
+#define PMGR_PERF_STATE_M(_n)			(4 + (_n))
+
+enum {
+	PMGR_CLK_OSC = 0,
+	PMGR_CLK_PLL0,
+	PMGR_CLK_PLL1,
+	PMGR_CLK_PLL2,
+	PMGR_CLK_PLL3,
+	PMGR_CLK_PLL4,
+	PMGR_CLK_PLLUSB,
+	PMGR_CLK_DOUBLER,
+	PMGR_CLK_CPU,
+	PMGR_CLK_MEM,
+	PMGR_CLK_PIO,
+	PMGR_CLK_ACP,
+	PMGR_CLK_MCU_FIXED,
+	PMGR_CLK_MCU,
+	PMGR_CLK_PREDIV0,
+	PMGR_CLK_PREDIV1,
+	PMGR_CLK_PREDIV2,
+	PMGR_CLK_PREDIV3,
+	PMGR_CLK_PREDIV4,
+	PMGR_CLK_PREDIV5,
+	PMGR_CLK_PREDIV6,
+	PMGR_CLK_MANAGED0,
+	PMGR_CLK_MANAGED1,
+	PMGR_CLK_MANAGED2,
+	PMGR_CLK_MANAGED3,
+	PMGR_CLK_MANAGED4,
+	PMGR_CLK_MEDIUM0,
+	PMGR_CLK_MEDIUM1,
+	PMGR_CLK_VID0,
+	PMGR_CLK_VID1,
+	PMGR_CLK_I2C,
+	PMGR_CLK_SDIO,
+	PMGR_CLK_MIPI_DSI,
+	PMGR_CLK_AUDIO,
+	PMGR_CLK_HPARK_PCLK,
+	PMGR_CLK_HPARK_TCLK,
+	PMGR_CLK_UPERF,
+	PMGR_CLK_DEBUG,
+	PMGR_CLK_HPERFRT,
+	PMGR_CLK_GFX,
+	PMGR_CLK_GFX_SLC,
+	PMGR_CLK_HPERFNRT,
+	PMGR_CLK_ISP,
+	PMGR_CLK_IOP,
+	PMGR_CLK_CDIO,
+	PMGR_CLK_LPERFS,
+	PMGR_CLK_PCLK0,
+	PMGR_CLK_PCLK1,
+	PMGR_CLK_PCLK2,
+	PMGR_CLK_PCLK3,
+	PMGR_CLK_SPI0,
+	PMGR_CLK_SPI1,
+	PMGR_CLK_SPI2,
+	PMGR_CLK_SPI3,
+	PMGR_CLK_SPI4,
+	PMGR_CLK_SLOW,
+	PMGR_CLK_SLEEP,
+	PMGR_CLK_USBPHY,
+	PMGR_CLK_USBOHCI,
+	PMGR_CLK_USB12,
+	PMGR_CLK_NCO_REF0,
+	PMGR_CLK_NCO_REF1,
+	PMGR_CLK_VENC_MTX,
+	PMGR_CLK_VENC,
+	PMGR_CLK_COUNT
+};
+
+extern void pmgr_update_device_tree(DTNode *pmgr_node);
+
+#endif /* ! __PLATFORM_SOC_PMGR_H */

platform/s5l8940x/include/platform/trampoline.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_TRAMPOLINE_H
+#define __PLATFORM_TRAMPOLINE_H
+
+#include <platform/memmap.h>
+#include <platform/soc/hwregbase.h>
+
+#define SECURITY_REG		(PMGR_BASE_ADDR + 0xA000)
+#define ROM_READ_DISABLE	(1 << 0)
+
+#endif /* ! __PLATFORM_TRAMPOLINE_H */

platform/s5l8940x/include/platform/usbconfig.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2008-2009 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_USBCONFIG_H
+#define __PLATFORM_USBCONFIG_H
+
+#define USBPHY_CLK_TYPE		(3) /* Use CLKCORE */
+
+#if SUB_PLATFORM_S5L8940X
+#define USBPHY_UOTGTUNE1        (0x349)
+#define USBPHY_UOTGTUNE2        (0xF13)
+#elif SUB_PLATFORM_S5L8942X | SUB_PLATFORM_S5L8947X
+#define USBPHY_UOTGTUNE1        (0x349)
+#define USBPHY_UOTGTUNE2        (0x6FF3)
+#endif
+
+#define USBOTG_AHB_DMA_BURST	(DWCUSB_GAHBCFG_HBST_INCR8)
+
+#ifdef WITH_TARGET_USB_CONFIG
+#include <target/usbconfig.h>
+#endif /* WITH_TARGET_USB_CONFIG */
+
+#endif /* ! __PLATFORM_USBCONFIG_H */

platform/s5l8940x/iop_init.c

@@ -0,0 +1,208 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <arch.h>
+#include <arch/arm/arm.h>
+#include <debug.h>
+#include <drivers/a5iop/a5iop.h>
+#include <platform.h>
+#include <platform/clocks.h>
+#include <platform/int.h>
+#include <platform/memmap.h>
+#include <platform/timer.h>
+#include <platform/soc/hwisr.h>
+#include <platform/soc/pmgr.h>
+#include <sys.h>
+#include <sys/boot.h>
+#include <sys/callout.h>
+
+/*
+ * Platform memory layout.
+ *
+ * The IOP sees SDRAM at its physical location uncached, and has an cached aperture
+ * visible elsewhere.  SDRAM size of up to 1GB is currently supported.
+ * SRAM is not visible/legally usable.
+ *
+ * For some platforms/targets, SDRAM_LEN is not constant and so we 
+ * have to compute a maximum via other means.
+ *
+ * Note that the AE2 Sparrow shares this code.
+ */
+#define MEM_CACHED_BASE		(SDRAM_BASE | 0xc0000000)
+#define SDRAM_MAX_LEN		(SDRAM_BANK_LEN * SDRAM_BANK_COUNT)
+struct mem_static_map_entry mem_static_map_entries[] = {
+        {
+                MEM_CACHED_BASE,                        /* cached */
+                SDRAM_BASE,                             /* uncached */
+                SDRAM_BASE,                             /* physical */
+                SDRAM_MAX_LEN                           /* length */
+        },
+        {MAP_NO_ENTRY, MAP_NO_ENTRY, MAP_NO_ENTRY, 0}
+};
+
+void platform_mmu_setup(bool resume)
+{
+	if (false == resume) {
+		/* Remap text base to zero, outer uncacheable, shared */
+		arm_mmu_map_section(0, TEXT_BASE, kARMMMUInnerNormalOuterNoncached, true);
+#ifdef MAP_SRAM_CACHED
+		/* Map the SRAM as cacheable, shared */
+		arm_mmu_map_section(SRAM_BASE, SRAM_BASE, kARMMMUNormal, true);
+#endif // MAP_SRAM_CACHED
+		/* Remap all of SDRAM through the cacheable aperture, outer uncacheable, shared */
+		arm_mmu_map_section_range(MEM_CACHED_BASE, SDRAM_BASE, ROUNDUP(SDRAM_BANK_LEN * SDRAM_BANK_COUNT, MB)/MB,
+					  kARMMMUInnerNormalOuterNoncached, true, false);
+		/* Remap all of SDRAM through the uncacheable aperture (existing mappings should be there, but be sure) */
+		arm_mmu_map_section_range(SDRAM_BASE, SDRAM_BASE, ROUNDUP(SDRAM_BANK_LEN * SDRAM_BANK_COUNT, MB)/MB,
+					  kARMMMUStronglyOrdered, false, false);
+	}
+}
+
+bool platform_get_production_mode(void)
+{
+	return(true);
+}
+
+bool platform_get_secure_mode(void)
+{
+	return(true);
+}
+
+void platform_reset(bool panic)
+{
+	for (;;)
+		;
+}
+
+/*
+ * Early init is done every time the IOP starts.
+ */
+int
+platform_early_init()
+{
+#if PLATFORM_VARIANT_IOP
+	/* In general we want power-gating to be disabled. */
+	rPMGR_PWR_GATE_CTL_CLR = rPMGR_PWR_GATE_IOP;
+	while (rPMGR_PWR_GATE_CTL_CLR & rPMGR_PWR_GATE_IOP) ;
+#endif
+
+	interrupt_init();
+
+	timer_init(0);
+	
+	return(0);
+}
+
+/*
+ * Halt waiting for an interrupt.
+ */
+void
+platform_halt(void)
+{
+	arch_halt();
+}
+
+#if SUPPORT_SLEEP
+
+#if WITH_IOP_POWER_GATING
+
+/*
+ * Deep idle sleep with power gating
+ */
+void
+platform_deep_idle(void)
+{
+	rPMGR_PWR_GATE_CTL_SET = rPMGR_PWR_GATE_IOP;
+	while (!(rPMGR_PWR_GATE_CTL_SET & rPMGR_PWR_GATE_IOP)) ;
+	a5iop_sleep(1);
+	rPMGR_PWR_GATE_CTL_CLR = rPMGR_PWR_GATE_IOP;
+	while (rPMGR_PWR_GATE_CTL_CLR & rPMGR_PWR_GATE_IOP) ;
+}
+
+#endif
+
+void
+platform_sleep(void)
+{
+	/* We assume power-gating is disabled, which it need to be so
+	 * the IOP wrapper registers don't disappear. */
+	a5iop_sleep(0);
+}
+
+#endif
+
+/*
+ * Cache control
+ */
+void
+platform_cache_operation(int operation, void *address, u_int32_t length)
+{
+	a5iop_cache_operation(operation, address, length);
+}
+
+/*
+ * Host doorbell uses a SWI in the AIC.
+ */
+static void	(* _doorbell_handler)(void *arg);
+static void
+platform_doorbell_handler(void *arg)
+{
+	/* clear the doorbell before passing up */
+	interrupt_clear_ipc(INT_IOP);
+	_doorbell_handler(arg);
+}
+
+void
+platform_init_iop_doorbell(void (* handler)(void *arg), void *arg)
+{
+	_doorbell_handler = handler;
+	install_int_handler(INT_IOP, platform_doorbell_handler, arg);
+	set_int_type(INT_IOP, INT_TYPE_IRQ | INT_TYPE_LEVEL);
+	unmask_int(INT_IOP);
+}
+
+void
+platform_mask_doorbell(void)
+{
+	mask_int(INT_IOP);
+}
+
+void
+platform_unmask_doorbell(void)
+{
+	unmask_int(INT_IOP);
+}
+
+void
+platform_ring_host_doorbell(void)
+{
+	interrupt_generate_ipc(INT_HOST);
+}
+
+int
+platform_init_nmi(void (*handler)(void *arg), void *arg)
+{
+#ifdef INT_IOP_NMI
+	install_int_handler(INT_IOP_NMI, handler, arg);
+	set_int_type(INT_IOP_NMI, INT_TYPE_FIQ | INT_TYPE_LEVEL);
+	unmask_int(INT_IOP_NMI);
+#endif
+
+	return(0);
+}
+
+/*
+ * Clock management.
+ *
+ * Currently the IOP does none for this platform.
+ */
+void clock_gate(int device, bool enable)
+{
+}

platform/s5l8940x/miu/miu.c

@@ -0,0 +1,319 @@
+/*
+ * Copyright (C) 2007-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <debug.h>
+#include <drivers/miu.h>
+#include <platform.h>
+#include <platform/memmap.h>
+#include <platform/miu.h>
+#include <platform/soc/miu.h>
+#include <platform/soc/pmgr.h>
+#include <platform/clocks.h>
+#include <platform/soc/hwclocks.h>
+
+static void miu_configure_bridge(const u_int32_t *bridge_settings);
+
+#define BRIDGE_SHIFT		(16)
+#define BRIDGE_MASK		(0xFFFF)
+#define NRT_DART_WIDGETS	(0 << BRIDGE_SHIFT)
+#define NRT_DART_BRIDGE		(1 << BRIDGE_SHIFT)
+#define NRT_TOP_WIDGETS		(2 << BRIDGE_SHIFT)
+#define NRT_TOP_BRIDGE		(3 << BRIDGE_SHIFT)
+#define RT_TOP_WIDGETS		(4 << BRIDGE_SHIFT)
+#define RT_TOP_BRIDGE		(5 << BRIDGE_SHIFT)
+#define UPERF_WIDGETS		(6 << BRIDGE_SHIFT)
+#define UPERF_BRIDGE		(7 << BRIDGE_SHIFT)
+#define CDIO_WIDGETS		(8 << BRIDGE_SHIFT)
+#define CDIO_BRIDGE		(9 << BRIDGE_SHIFT)
+
+static const u_int32_t bridge_registers[] = {
+	NRT_DART_WIDGETS_BASE_ADDR,	NRT_DART_PL301_BASE_ADDR,
+	NRT_TOP_WIDGETS_BASE_ADDR,	NRT_TOP_PL301_BASE_ADDR,
+	RT_TOP_WIDGETS_BASE_ADDR,	RT_TOP_PL301_BASE_ADDR,
+	UPERF_WIDGETS_BASE_ADDR,	UPERF_PL301_BASE_ADDR,
+	CDIO_WIDGETS_BASE_ADDR,		CDIO_PL301_BASE_ADDR,
+};
+
+#if APPLICATION_SECUREROM || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
+// The following settings are based on H4P Tunables Revision 0.12
+
+static const u_int32_t bridge_settings_static[] = {
+	// Configure recommended transaction limits in CDIO
+	CDIO_WIDGETS | CDIO_IOP_RTLIMIT,	0x00000808,
+	CDIO_WIDGETS | CDIO_IOP_WTLIMIT,	0x00000808,
+	CDIO_WIDGETS | CDIO_CDMA_RTLIMIT,	0x00000808,
+	CDIO_WIDGETS | CDIO_CDMA_WTLIMIT,	0x00000808,
+	CDIO_WIDGETS | CDIO_UPERF_RTLIMIT,	0x00000404,
+	CDIO_WIDGETS | CDIO_UPERF_WTLIMIT,	0x00000404,
+	CDIO_WIDGETS | CDIO_AUDIO_RTLIMIT,	0x00000808,
+	CDIO_WIDGETS | CDIO_AUDIO_WTLIMIT,	0x00000808,
+	CDIO_WIDGETS | CDIO_PIO_RTLIMIT,	0x00000808,
+	CDIO_WIDGETS | CDIO_PIO_WTLIMIT,	0x00000404,
+
+	// Configure recommended bridge settings in CDIO
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0,	0x00000000,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0,	0x01000001,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0,	0x02000002,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0,	0x03000003,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0,	0x04000004,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0,	0x00000000,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0,	0x01000001,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0,	0x02000002,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0,	0x03000003,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0,	0x04000004,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1,	0x00000000,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1,	0x01000001,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1,	0x02000002,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1,	0x03000003,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1,	0x04000004,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1,	0x00000000,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1,	0x01000001,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1,	0x02000002,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1,	0x03000003,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1,	0x04000004,
+
+	// Configure recommended features in CDIO
+	CDIO_WIDGETS | CDIO_IOP_WREQSP,		0x00000003,
+	CDIO_WIDGETS | CDIO_CDMA_WGATHER,	0x00000100,
+	CDIO_WIDGETS | CDIO_UPERF_WGATHER,	0x00000100,
+	CDIO_WIDGETS | CDIO_AUDIO_WGATHER,	0x00000100,
+
+	// Configure recommended traffic attributes in UPERF
+	//	AxCACHE = Cacheable
+	//	AxUSER = enable Shared bit
+	UPERF_WIDGETS | UPERF_OTG_QOS,		0x01010101,
+	UPERF_WIDGETS | UPERF_OTG_CACHE,	0x01020102,
+	UPERF_WIDGETS | UPERF_EHCI_QOS,		0x01010101,
+	UPERF_WIDGETS | UPERF_EHCI_CACHE,	0x01020102,
+	UPERF_WIDGETS | UPERF_OHCI0_QOS,	0x01010101,
+	UPERF_WIDGETS | UPERF_OHCI0_CACHE,	0x01020102,
+	UPERF_WIDGETS | UPERF_OHCI1_QOS,	0x01010101,
+	UPERF_WIDGETS | UPERF_OHCI1_CACHE,	0x01020102,
+
+	0, 0,
+	0, 0
+};
+#endif	// APPLICATION_SECUREROM || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
+
+#if WITH_DEVICETREE || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
+static const u_int32_t bridge_settings_dynamic[] = {
+	// Configure recommended transaction limits in HPerf-NRT DART
+	NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER0_RTLIMIT,	0x00000707,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER0_WTLIMIT,	0x00000404,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER1_RTLIMIT,	0x00000707,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER1_WTLIMIT,	0x00000404,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_DART_RTLIMIT,		0x00000808,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_DART_WTLIMIT,		0x00000808,
+
+	// Configure recommended bridge settings in HPerf-NRT DART
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI,	0x00000000,	// JPEG0 High Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI,	0x01000001,	// JPEG1 High Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI,	0x02000102,	// Scaler0 Reduced Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI,	0x03000103,	// Sclaer1 Reduced Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI,	0x00000000,	// JPEG0 High Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI,	0x01000001,	// JPEG1 High Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI,	0x02000102,	// Scaler0 Reduced Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI,	0x03000103,	// Sclaer1 Reduced Priority
+
+	// Configure recommended bridge settings in HPerf-NRT DART
+	NRT_DART_WIDGETS | HPERF_NRT_DART_JPEG0_QOS,		0x01010101,	// JPEG0 LLT Traffic for R&W
+	NRT_DART_WIDGETS | HPERF_NRT_DART_JPEG1_QOS,		0x01010101,	// JPEG0 LLT Traffic for R&W
+	0, 0,
+
+	// Configure recommended transaction limits in HPerf-NRT Top
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_VENC_RTLIMIT,		0x00001010,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_VENC_WTLIMIT,		0x00000808,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_VDEC_RTLIMIT,		0x00001010,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_VDEC_WTLIMIT,		0x00000808,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_TOP_RTLIMIT,		0x00003F3F,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_TOP_WTLIMIT,		0x00000F0F,
+
+	// Configure recommended bridge settings in HPerf-NRT Top
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI,		0x00000000,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI,		0x01000001,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI,		0x02000002,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI,		0x03000003,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI,		0x00000000,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI,		0x01000001,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI,		0x02000002,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI,		0x03000003,
+
+	// Configure recommended features in HPerf-NRT Top
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_DART_WGATHER,		0x00000000,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_VENC_WREQSP,		0x00000003,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_VDEC_WREQSP,		0x00000003,
+	0, 0,
+
+	// Configure recommended transaction limits in HPerf-RT Top
+	RT_TOP_WIDGETS | HPERF_RT_TOP_TOP_RTLIMIT,		0x00003F3F,
+	RT_TOP_WIDGETS | HPERF_RT_TOP_TOP_WTLIMIT,		0x00000F0F,
+	RT_TOP_WIDGETS | HPERF_RT_TOP_DISP0_RTLIMIT,		0x00000C0C,
+	RT_TOP_WIDGETS | HPERF_RT_TOP_DISP1_RTLIMIT,		0x00001010,
+	RT_TOP_WIDGETS | HPERF_RT_TOP_ISP_RTLIMIT,		0x00000C0C,
+	RT_TOP_WIDGETS | HPERF_RT_TOP_ISP_WTLIMIT,		0x00001010,
+
+	// Configure recommended bridge settings in HPerf-RT Top
+	RT_TOP_BRIDGE | HPERF_RT_TOP_AR_CHAN_ARB_MI,		0x00000000,
+	RT_TOP_BRIDGE | HPERF_RT_TOP_AR_CHAN_ARB_MI,		0x01000001,
+	RT_TOP_BRIDGE | HPERF_RT_TOP_AR_CHAN_ARB_MI,		0x02000002,
+	0, 0,
+
+	0, 0
+};
+#endif	// WITH_DEVICETREE || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
+
+int miu_initialize_internal_ram(void)
+{
+#if APPLICATION_SECUREROM
+	// Ensure that rPMGR_SCRATCH0-3 get cleared
+	rPMGR_SCRATCH0 = 0;
+	rPMGR_SCRATCH1 = 0;
+	rPMGR_SCRATCH2 = 0;
+	rPMGR_SCRATCH3 = 0;
+#endif /* APPLICATION_SECUREROM */
+
+	// Save the Security Epoch in the top byte of PMGR_SCRATCH0
+	rPMGR_SCRATCH0 &= ~0xFF000000;
+	rPMGR_SCRATCH0 |= (platform_get_security_epoch()) << 24;
+
+	return 0;
+}
+
+int miu_init(void)
+{
+#if APPLICATION_IBOOT && !PRODUCT_IBEC
+	// Verify that the Security Epoch in PMGR_SCRATCH0 matches
+	if ((rPMGR_SCRATCH0 >> 24) != platform_get_security_epoch()) {
+		panic("miu_init: Epoch Mismatch\n");
+	}
+#endif
+
+#if APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC
+	// Configure recommended transaction limits in CIF
+	rCIF_RTLIMIT = 0x00000808;
+	rCIF_WTLIMIT = 0x00000808;
+
+	// Tunables recommendation, for SCU clock-gating
+	// (will change to 0x80 for <rdar://problem/8267114>)
+	rCIF_IDLETMR = 0x00000010;
+#endif
+
+#if APPLICATION_SECUREROM || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
+	// Configure bridges that are statically powered
+	clock_gate(CLK_UPERF, true);
+	miu_configure_bridge(bridge_settings_static);
+	clock_gate(CLK_UPERF, false);
+#endif
+
+#if APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC
+	// Configure bridges that are dynamically powered
+	clock_gate(CLK_HPERFNRT, true);
+	clock_gate(CLK_HPERFRT, true);
+	miu_configure_bridge(bridge_settings_dynamic);
+	clock_gate(CLK_HPERFNRT, false);
+	clock_gate(CLK_HPERFRT, false);
+	
+	/* Enable the SCU.  Note that we explicitly do NOT touch the
+	 * "power status" register, since the default is supposed to
+	 * be correct, and the real control is in the CPU's "SMP"
+	 * bit. */
+	rSCU_TAG_INVAL = 0xff;	/* invalidate SCU tags for all CPUs */
+
+	/* Enable SCU, standby, speculative linefills, and parity */
+	rSCU_CONTROL = (1 << 5) | (1 << 3) | (1 << 2) | (1 << 0);
+#endif
+
+	/* remap whatever bank of ram we're in to zero */
+	if (TEXT_BASE == SRAM_BASE)
+		miu_select_remap(REMAP_SRAM);
+	else if ((TEXT_BASE >= SDRAM_BASE) && (TEXT_BASE < SDRAM_END))
+		miu_select_remap(REMAP_SDRAM);
+
+	return 0;
+}
+
+static void miu_configure_bridge(const u_int32_t *bridge_settings)
+{
+	volatile u_int32_t *reg;
+	u_int32_t cnt = 0, bridge, offset, data;
+
+	while ((bridge_settings[cnt] != 0) || (bridge_settings[cnt + 1] != 0)) {
+		while ((bridge_settings[cnt] != 0) || (bridge_settings[cnt + 1] != 0)) {
+			bridge = bridge_settings[cnt] >> BRIDGE_SHIFT;
+			offset = bridge_settings[cnt] & BRIDGE_MASK;
+			data = bridge_settings[cnt + 1];
+			reg = (volatile u_int32_t *)(bridge_registers[bridge] + offset);
+			*reg = data;
+			cnt += 2;
+		}
+		cnt += 2;
+	}
+}
+
+void miu_suspend(void)
+{
+	/* XXX ? */
+}
+
+int miu_initialize_dram(bool resume)
+{
+#if APPLICATION_IBOOT
+	mcu_initialize_dram(resume);
+#endif
+	return 0;
+}
+
+void miu_select_remap(enum remap_select sel)
+{
+	switch (sel) {
+		case REMAP_SRAM:
+			rREMAP_CTL = (rREMAP_CTL & ~3) | (1 << 0); // remap_sel = 1
+			rPL310_FILTER_START = 0x1;
+			break;
+		case REMAP_SDRAM:
+			rREMAP_CTL = (rREMAP_CTL & ~3) | (2 << 0); // remap_sel = 2
+			// Leave low megabyte heading to DRAM for wake-from-sleep,
+			// Otherwise send everything below DRAM to the PIO block.
+			// Currently this is for testing only; it is not POR.
+			rPL310_FILTER_END   = 0x80000000;
+			rPL310_FILTER_START = 0x00100001;
+			break;
+	}
+
+	/* read remap register to ensure it has been updated */
+	rREMAP_CTL;
+}
+
+void miu_bypass_prep(void)
+{
+#if APPLICATION_IBOOT
+	extern void mcu_bypass_prep(void);
+	mcu_bypass_prep();
+#endif
+}
+
+#if WITH_DEVICETREE
+
+void miu_update_device_tree(DTNode *pmgr_node)
+{
+	u_int32_t propSize;
+	char *propName;
+	void *propData;
+
+	// Fill in the bridge-settings property
+	propName = "bridge-settings";
+	if (FindProperty(pmgr_node, &propName, &propData, &propSize)) {
+		if (propSize >= sizeof(bridge_settings_dynamic)) {
+			memcpy(propData, bridge_settings_dynamic, sizeof(bridge_settings_dynamic));
+		}
+	}
+}
+
+#endif

platform/s5l8940x/miu/rules.mk

@@ -0,0 +1,15 @@
+# Copyright (C) 2007 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_MIU=1
+
+ALL_OBJS += $(LOCAL_DIR)/miu.o

platform/s5l8940x/pinconfig_s5l8940x.c

@@ -0,0 +1,317 @@
+/*
+ * Copyright (C) 2009-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <drivers/apple/gpio.h>
+#include <platform.h>
+#include <platform/soc/hwregbase.h>
+#include <target.h>
+
+/* Default S5L8940X SoC Pin Configuration */
+
+#define FMI_DRIVE_STR	DRIVE_X3
+
+#if !WITH_TARGET_CONFIG
+static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
+/* Port  0 */
+	CFG_IN,								// GPIO0		-> MENU_KEY
+	CFG_IN,								// GPIO1		-> HOLD_KEY
+	CFG_DISABLED,							// GPIO2		->
+	CFG_DISABLED,							// GPIO3		->
+	CFG_DISABLED,							// GPIO4		->
+	CFG_DISABLED | PULL_DOWN,					// GPIO5		->
+	CFG_DISABLED,							// GPIO6		->
+	CFG_DISABLED | PULL_DOWN,					// GPIO7		->
+
+/* Port  1 */
+	CFG_DISABLED,							// GPIO8		->
+	CFG_DISABLED,							// GPIO9		->
+	CFG_DISABLED,							// GPIO10		->
+	CFG_DISABLED,							// GPIO11		->
+	CFG_DISABLED,							// GPIO12		->
+	CFG_DISABLED,							// GPIO13		->
+	CFG_DISABLED,							// GPIO14		->
+	CFG_DISABLED,							// GPIO15		->
+
+/* Port  2 */
+	CFG_DISABLED,							// GPIO16		-> BOARD_ID[3]
+	CFG_DISABLED,							// GPIO17		->
+	CFG_DISABLED,							// GPIO18		-> BOOT_CONFIG[0]
+	CFG_DISABLED | PULL_DOWN,					// GPIO19		->
+	CFG_DISABLED,							// GPIO20		->
+	CFG_DISABLED,							// GPIO21		->
+	CFG_DISABLED | PULL_DOWN,					// GPIO22		->
+	CFG_DISABLED,							// GPIO23		->
+
+/* Port  3 */
+	CFG_DISABLED | PULL_DOWN,					// GPIO24		->
+	CFG_DISABLED,							// GPIO25		-> BOOT_CONFIG[1]
+	CFG_IN | PULL_DOWN,						// GPIO26		-> FORCE_DFU
+	CFG_DISABLED | PULL_DOWN,					// GPIO27		-> DFU_STATUS
+	CFG_DISABLED,							// GPIO28		-> BOOT_CONFIG[2]
+	CFG_DISABLED,							// GPIO29		-> BOOT_CONFIG[3]
+	CFG_DISABLED,							// GPIO30		->
+	CFG_DISABLED,							// GPIO31		->
+
+/* Port  4 */
+	CFG_DISABLED,							// GPIO32		->
+	CFG_DISABLED,							// GPIO33		->
+	CFG_DISABLED,							// GPIO34		->
+	CFG_DISABLED,							// GPIO35		->
+	CFG_DISABLED,							// GPIO36		->
+	CFG_DISABLED,							// GPIO37		->
+	CFG_DISABLED,							// GPIO38		->
+	CFG_DISABLED,							// GPIO39		->
+
+/* Port  5 */
+	CFG_DISABLED,							// EHCI_PORT_PWR[0]	->
+	CFG_DISABLED,							// EHCI_PORT_PWR[1]	->
+	CFG_DISABLED,							// EHCI_PORT_PWR[2]	->
+	CFG_DISABLED,							// UART1_TXD		->
+	CFG_DISABLED,							// UART1_RXD		->
+	CFG_DISABLED,							// UART1_RTSN		->
+	CFG_DISABLED,							// UART1_CTSN		->
+	CFG_DISABLED,							// UART2_TXD		->
+
+/* Port  6 */
+	CFG_DISABLED,							// UART2_RXD		->
+	CFG_DISABLED,							// UART2_RTSN		->
+	CFG_DISABLED,							// UART2_CTSN		->
+	CFG_DISABLED,							// UART3_TXD		->
+	CFG_DISABLED,							// UART3_RXD		->
+	CFG_DISABLED,							// UART3_RTSN		->
+	CFG_DISABLED,							// UART3_CTSN		->
+	CFG_DISABLED,							// UART5_RTXD		->
+
+/* Port  7 */
+	CFG_DISABLED,							// UART6_TXD		->
+	CFG_DISABLED,							// UART6_RXD		->
+	CFG_DISABLED,							// UART6_RTSN		->
+	CFG_DISABLED,							// UART6_CTSN		->
+	CFG_DISABLED,							// UART4_TXD/SPI4_MOSI	->
+	CFG_DISABLED,							// UART4_RXD/SPI4_MISO	->
+	CFG_DISABLED,							// UART4_RTSN/SPI4_SCLK	->
+	CFG_DISABLED,							// UART4_CTSN/SPI4_SSIN	->
+
+/* Port  8 */
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN3		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN2		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN1		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_WEN		->
+
+/* Port  9 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO5		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO4		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO2		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO1		->
+
+/* Port 10 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO0		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN3		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN2		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN1		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_REN		->
+
+/* Port 11 */
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO5		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO4		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO2		->
+
+/* Port 12 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO1		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO0		->
+	CFG_DISABLED,							// FMI2_CEN3		->
+	CFG_DISABLED,							// FMI2_CEN2		->
+	CFG_DISABLED,							// FMI2_CEN1		->
+	CFG_DISABLED,							// FMI2_CEN0		->
+	CFG_DISABLED,							// FMI2_CLE		->
+	CFG_DISABLED,							// FMI2_ALE		->
+
+/* Port 13 */
+	CFG_DISABLED,							// FMI2_REN		->
+	CFG_DISABLED,							// FMI2_WEN		->
+	CFG_DISABLED,							// FMI2_IO7		->
+	CFG_DISABLED,							// FMI2_IO6		->
+	CFG_DISABLED,							// FMI2_IO5		->
+	CFG_DISABLED,							// FMI2_IO4		->
+	CFG_DISABLED,							// FMI2_DQS		->
+	CFG_DISABLED,							// FMI2_IO3		->
+
+/* Port 14 */
+	CFG_DISABLED,							// FMI2_IO2		->
+	CFG_DISABLED,							// FMI2_IO1		->
+	CFG_DISABLED,							// FMI2_IO0		->
+	CFG_DISABLED,							// FMI0_CEN7		->
+	CFG_DISABLED,							// FMI0_CEN6		->
+	CFG_DISABLED,							// FMI0_CEN5		->
+	CFG_DISABLED,							// FMI0_CEN4		->
+	CFG_DISABLED,							// FMI1_CEN7		->
+
+/* Port 15 */
+	CFG_DISABLED,							// FMI1_CEN6		->
+	CFG_DISABLED,							// FMI1_CEN5		->
+	CFG_DISABLED,							// FMI1_CEN4		->
+	CFG_DISABLED,							// FMI3_CEN3		->
+	CFG_DISABLED,							// FMI3_CEN2		->
+	CFG_DISABLED,							// FMI3_CEN1		->
+	CFG_DISABLED,							// FMI3_CEN0		->
+	CFG_DISABLED,							// FMI3_CLE		->
+
+/* Port 16 */
+	CFG_DISABLED,							// FMI3_ALE		->
+	CFG_DISABLED,							// FMI3_REN		->
+	CFG_DISABLED,							// FMI3_WEN		->
+	CFG_DISABLED,							// FMI3_IO7		->
+	CFG_DISABLED,							// FMI3_IO6		->
+	CFG_DISABLED,							// FMI3_IO5		->
+	CFG_DISABLED,							// FMI3_IO4		->
+	CFG_DISABLED,							// FMI3_DQS		->
+
+/* Port 17 */
+	CFG_DISABLED,							// FMI3_IO3		->
+	CFG_DISABLED,							// FMI3_IO2		->
+	CFG_DISABLED,							// FMI3_IO1		->
+	CFG_DISABLED,							// FMI3_IO0		->
+	CFG_DISABLED,							// FMI2_CEN7		->
+	CFG_DISABLED,							// FMI2_CEN6		->
+	CFG_DISABLED,							// FMI2_CEN5		->
+	CFG_DISABLED,							// FMI2_CEN4		->
+
+/* Port 18 */
+	CFG_DISABLED,							// FMI3_CEN7		->
+	CFG_DISABLED,							// FMI3_CEN6		->
+	CFG_DISABLED,							// FMI3_CEN5		->
+	CFG_DISABLED,							// FMI3_CEN4		->
+	CFG_DISABLED,							// SPI3_MOSI		-> 
+	CFG_DISABLED,							// SPI3_MISO		-> 
+	CFG_DISABLED,							// SPI3_SCLK		-> 
+	CFG_DISABLED,							// SPI3_SSIN		-> 
+
+/* Port 19 */
+	CFG_DISABLED,							// ISP0_PRE_FLASH	->
+	CFG_DISABLED,							// ISP0_FLASH		->
+	CFG_DISABLED,							// ISP1_PRE_FLASH	->
+	CFG_DISABLED,							// ISP1_FLASH		->
+	CFG_DISABLED,							// SPI1_SCLK		->
+	CFG_DISABLED,							// SPI1_MOSI		->
+	CFG_DISABLED,							// SPI1_MISO		->
+	CFG_DISABLED,							// SPI1_SSIN		->
+
+/* Port 20 */
+	CFG_DISABLED,							// I2C2_SDA		->
+	CFG_DISABLED,							// I2C2_SCL		->
+	CFG_DISABLED,							// SPI0_SCLK		-> SPI0_SCLK/BOARD_ID[0]
+	CFG_DISABLED,							// SPI0_MOSI		-> SPI0_MOSI/BOARD_ID[1]
+	CFG_DISABLED,							// SPI0_MISO		-> SPI0_MISO/BOARD_ID[2]
+	CFG_DISABLED | PULL_UP,						// SPI0_SSIN		-> SPI0_SSIN
+	CFG_DISABLED,							// SPI2_SCLK		->
+	CFG_DISABLED,							// SPI2_MOSI		->
+
+/* Port 21 */
+	CFG_DISABLED,							// SPI2_MISO		->
+	CFG_DISABLED,							// SPI2_SSIN		->
+	CFG_DISABLED,							// I2C0_SDA		->
+	CFG_DISABLED,							// I2C0_SCL		->
+	CFG_DISABLED,							// I2C1_SDA		->
+	CFG_DISABLED,							// I2C1_SCL		->
+	CFG_DISABLED,							// ISP0_SDA		->
+	CFG_DISABLED,							// ISP0_SCL		->
+
+/* Port 22 */
+	CFG_DISABLED,							// ISP1_SDA		->
+	CFG_DISABLED,							// ISP1_SCL		->
+	CFG_DISABLED,							// SDIO_CLK		->
+	CFG_DISABLED,							// SDIO_CMD		->
+	CFG_DISABLED,							// SDIO_DATA0		->
+	CFG_DISABLED,							// SDIO_DATA1		->
+	CFG_DISABLED,							// SDIO_DATA2		->
+	CFG_DISABLED,							// SDIO_DATA3		->
+
+/* Port 23 */
+	CFG_DISABLED,							// MIPI_VSYNC		->
+	CFG_DISABLED,							// TMR32_PWM0		->
+	CFG_DISABLED,							// TMR32_PWM1		->
+	CFG_DISABLED,							// TMR32_PWM2		->
+	CFG_DISABLED,							// SWI_DATA		->
+	CFG_DISABLED,							// DWI_DI		->
+	CFG_DISABLED,							// DWI_DO		->
+	CFG_DISABLED,							// DWI_CLK		->
+
+/* Port 24 */
+	CFG_DISABLED,							// SENSOR0_RST		->
+	CFG_DISABLED,							// SENSOR0_CLK		->
+	CFG_DISABLED,							// SENSOR1_RST		->
+	CFG_DISABLED,							// SENSOR1_CLK		->
+	CFG_DISABLED,							// I2S0_MCK		->
+	CFG_DISABLED,							// I2S0_LRCK		->
+	CFG_DISABLED,							// I2S0_BCLK		->
+	CFG_DISABLED,							// I2S0_DOUT		->
+
+/* Port 25 */
+	CFG_DISABLED,							// I2S0_DIN		->
+	CFG_DISABLED,							// I2S1_MCK		->
+	CFG_DISABLED,							// I2S1_LRCK		->
+	CFG_DISABLED,							// I2S1_BCLK		->
+	CFG_DISABLED,							// I2S1_DOUT		->
+	CFG_DISABLED,							// I2S1_DIN		->
+	CFG_DISABLED,							// I2S2_MCK		->
+	CFG_DISABLED,							// I2S2_LRCK		->
+
+/* Port 26 */
+	CFG_DISABLED,							// I2S2_BCLK		->
+	CFG_DISABLED,							// I2S2_DOUT		->
+	CFG_DISABLED,							// I2S2_DIN		->
+	CFG_DISABLED,							// I2S3_MCK		->
+	CFG_DISABLED,							// I2S3_LRCK		->
+	CFG_DISABLED,							// I2S3_BCLK		->
+	CFG_DISABLED,							// I2S3_DOUT		->
+	CFG_DISABLED,							// I2S3_DIN		->
+
+/* Port 27 */
+	CFG_DISABLED,							// SPDIF		->
+	CFG_DISABLED | PULL_DOWN,					// GPIO217		->
+	CFG_DISABLED,							// GPIO218		->
+	CFG_DISABLED,							// DP_HPD		->
+	CFG_DISABLED,							// UART0_TXD		->
+	CFG_DISABLED,							// UART0_RXD		->
+	CFG_DISABLED,							// TST_CLKOUT		->
+	CFG_DISABLED,							// TST_STPCLK		->
+
+/* Port 28 */
+	CFG_DISABLED,							// WDOG			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+};
+
+const uint32_t *platform_get_default_gpio_cfg(uint32_t gpioc)
+{
+	return gpio_default_cfg;
+}
+#endif

platform/s5l8940x/pinconfig_s5l8942x.c

@@ -0,0 +1,288 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <drivers/apple/gpio.h>
+#include <platform.h>
+#include <platform/soc/hwregbase.h>
+#include <target.h>
+
+/* Default S5L8942X SoC Pin Configuration */
+
+#define FMI_DRIVE_STR	DRIVE_X2
+#define FMI_SLEW_RATE	SLEW_RATE_SLOW
+
+#if !WITH_TARGET_CONFIG
+static const u_int32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
+/* Port  0 */
+	CFG_IN,								// GPIO0		-> MENU_KEY
+	CFG_IN,								// GPIO1		-> HOLD_KEY
+	CFG_DISABLED,							// GPIO2		->
+	CFG_DISABLED,							// GPIO3		->
+	CFG_DISABLED,							// GPIO4		->
+	CFG_DISABLED,							// GPIO5		->
+	CFG_DISABLED,							// GPIO6		->
+	CFG_DISABLED,							// GPIO7		->
+
+/* Port  1 */
+	CFG_DISABLED,							// GPIO8		->
+	CFG_DISABLED,							// GPIO9		->
+	CFG_DISABLED,							// GPIO10		->
+	CFG_DISABLED,							// GPIO11		->
+	CFG_DISABLED,							// GPIO12		->
+	CFG_DISABLED,							// GPIO13		->
+	CFG_DISABLED,							// GPIO14		->
+	CFG_DISABLED,							// GPIO15		->
+
+/* Port  2 */
+	CFG_DISABLED,							// GPIO16		-> BOARD_ID[3]
+	CFG_DISABLED,							// GPIO17		->
+	CFG_DISABLED,							// GPIO18		-> BOOT_CONFIG[0]
+	CFG_DISABLED,							// GPIO19		-> KEEPACT
+	CFG_DISABLED,							// GPIO20		->
+	CFG_DISABLED,							// GPIO21		->
+	CFG_DISABLED,							// GPIO22		->
+	CFG_DISABLED,							// GPIO23		->
+
+/* Port  3 */
+	CFG_DISABLED,							// GPIO24		->
+	CFG_DISABLED,							// GPIO25		-> BOOT_CONFIG[1]
+	CFG_IN | PULL_DOWN,						// GPIO26		-> FORCE_DFU
+	CFG_DISABLED | PULL_DOWN,					// GPIO27		-> DFU_STATUS
+	CFG_DISABLED,							// GPIO28		-> BOOT_CONFIG[2]
+	CFG_DISABLED,							// GPIO29		-> BOOT_CONFIG[3]
+	CFG_DISABLED,							// GPIO30		->
+	CFG_DISABLED,							// GPIO31		->
+
+/* Port  4 */
+	CFG_DISABLED,							// GPIO32		->
+	CFG_DISABLED,							// GPIO33		->
+	CFG_DISABLED,							// GPIO34		->
+	CFG_DISABLED,							// GPIO35		->
+	CFG_DISABLED,							// GPIO36		->
+	CFG_DISABLED,							// EHCI_PORT_PWR[0]	-> BOARD_REV[0]
+	CFG_DISABLED,							// EHCI_PORT_PWR[1]	-> BOARD_REV[1]
+	CFG_DISABLED,							// EHCI_PORT_PWR[2]	-> BOARD_REV[2]
+
+/* Port  5 */
+	CFG_DISABLED,							// UART1_TXD		->
+	CFG_DISABLED,							// UART1_RXD		->
+	CFG_DISABLED,							// UART1_RTSN		->
+	CFG_DISABLED,							// UART1_CTSN		->
+	CFG_DISABLED,							// UART2_TXD		->
+	CFG_DISABLED,							// UART2_RXD		->
+	CFG_DISABLED,							// UART2_RTSN		->
+	CFG_DISABLED,							// UART2_CTSN		->
+
+/* Port  6 */
+	CFG_DISABLED,							// UART3_TXD		->
+	CFG_DISABLED,							// UART3_RXD		->
+	CFG_DISABLED,							// UART3_RTSN		->
+	CFG_DISABLED,							// UART3_CTSN		->
+	CFG_DISABLED,							// I2C0_SDA		->
+	CFG_DISABLED,							// I2C0_SCL		->
+	CFG_DISABLED,							// I2C1_SDA		->
+	CFG_DISABLED,							// I2C1_SCL		->
+
+/* Port  7 */
+	CFG_DISABLED,							// ISP0_SDA		->
+	CFG_DISABLED,							// ISP0_SCL		->
+	CFG_DISABLED,							// ISP1_SDA		->
+	CFG_DISABLED,							// ISP1_SCL		->
+	CFG_DISABLED,							// UART5_TXD/MIPI_VSYNC	->
+	CFG_DISABLED,							// TMR32_PWM0
+	CFG_DISABLED,							// TMR32_PWM1
+	CFG_DISABLED,							// TMR32_PWM2
+
+/* Port  8 */
+	CFG_DISABLED,							// SWI_DATA		->
+	CFG_DISABLED,							// DWI_DI		->
+	CFG_DISABLED,							// DWI_DO		->
+	CFG_DISABLED,							// DWI_CLK		->
+	CFG_DISABLED,							// SENSOR0_RST		->
+	CFG_DISABLED,							// SENSOR0_CLK		->
+	CFG_DISABLED,							// SENSOR1_RST		->
+	CFG_DISABLED,							// SENSOR1_CLK		->
+
+/* Port  9 */
+	CFG_DISABLED,							// ISP0_PRE_FLASH	->
+	CFG_DISABLED,							// ISP0_FLASH		->
+	CFG_DISABLED,							// ISP1_PRE_FLASH	->
+	CFG_DISABLED,							// ISP1_FLASH		->
+	CFG_DISABLED,							// I2S0_MCK		->
+	CFG_DISABLED,							// I2S0_LRCK		->
+	CFG_DISABLED,							// I2S0_SCLK		->
+	CFG_DISABLED,							// I2S0_DOUT		->
+
+/* Port 10 */
+	CFG_DISABLED,							// I2S0_DIN		->
+	CFG_DISABLED,							// I2S1_MCK		->
+	CFG_DISABLED,							// I2S1_LRCK		->
+	CFG_DISABLED,							// I2S1_SCLK		->
+	CFG_DISABLED,							// I2S1_DOUT		->
+	CFG_DISABLED,							// I2S1_DIN		->
+	CFG_DISABLED,							// I2S2_MCK		->
+	CFG_DISABLED,							// I2S2_LRCK		->
+
+/* Port 11 */
+	CFG_DISABLED,							// I2S2_BCLK		->
+	CFG_DISABLED,							// I2S2_DOUT		->
+	CFG_DISABLED,							// I2S2_DIN		->
+	CFG_DISABLED,							// I2S2_MCK		->
+	CFG_DISABLED,							// I2S3_LRCK		->
+	CFG_DISABLED,							// I2S3_BCLK		->
+	CFG_DISABLED,							// I2S3_DOUT		->
+	CFG_DISABLED,							// I2S3_DIN		->
+
+/* Port 12 */
+	CFG_DISABLED,							// SPI0_SCLK		-> BOARD_ID[0]
+	CFG_DISABLED,							// SPI0_MOSI		-> BOARD_ID[1]
+	CFG_DISABLED,							// SPI0_MISO		-> BOARD_ID[2]
+	CFG_DISABLED | PULL_UP,						// SPI0_SSIN		->
+	CFG_DISABLED,							// SPI1_SCLK		->
+	CFG_DISABLED,							// SPI1_MOSI		->
+	CFG_DISABLED,							// SPI1_MISO		->
+	CFG_DISABLED,							// SPI1_SSIN		->
+
+/* Port 13 */
+	CFG_DISABLED,							// SPI2_SCLK		->
+	CFG_DISABLED,							// SPI2_MOSI		->
+	CFG_DISABLED,							// SPI2_MISO		->
+	CFG_DISABLED,							// SPI2_SSIN		->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 14 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 15 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 16 */
+	CFG_DISABLED,							// UART4_TXD		-> SPI3_SCLK/FMI0_CEN7
+	CFG_DISABLED,							// UART4_RXD		-> SPI3_MOSI/FMI0_CEN6
+	CFG_DISABLED,							// UART4_RTSN		-> SPI3_MISO/FMI0_CEN5
+	CFG_DISABLED,							// UART4_CTSN		-> SPI3_SSIN/FMI0_CEN4
+	CFG_DISABLED,							// SDIO0_DATA3		-> FMI1_CEN7
+	CFG_DISABLED,							// SDIO0_DATA2		-> FMI1_CEN6
+	CFG_DISABLED,							// SDIO0_DATA1		-> FMI1_CEN5
+	CFG_DISABLED,							// SDIO0_DATA0		-> FMI1_CEN4
+
+/* Port 17 */
+	CFG_DISABLED,							// SDIO0_CMD		->
+	CFG_DISABLED,							// SDIO0_CLK		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN3		-> FMI0_RBN0
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN2		-> FMI0_RBN1
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN1		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_ALE		->
+
+/* Port 18 */
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO5		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO4		->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 19 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 20 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO2		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO1		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO0		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN3		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN2		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN1		->
+
+/* Port 21 */
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO5		->
+
+/* Port 22 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO4		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO2		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO1		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO0		->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 23 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 24 */
+	CFG_DISABLED,							// I2C2_SDA		->
+	CFG_DISABLED,							// I2C2_SCL		->
+	CFG_DISABLED,							// UART0_TXD		->
+	CFG_DISABLED,							// UART0_RXD		->
+	CFG_DISABLED,							// UART5_RTXD		-> UART5_RXD
+	CFG_DISABLED,							// DP_HPD		->
+	CFG_DISABLED,							// TST_CLKOUT		->
+	CFG_DISABLED,							// TST_STPCLK		->
+
+/* Port 25 */
+	CFG_DISABLED,							// WDOG			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+};
+
+const uint32_t *platform_get_default_gpio_cfg(uint32_t gpioc)
+{
+	return gpio_default_cfg;
+}
+#endif

platform/s5l8940x/pinconfig_s5l8947x.c

@@ -0,0 +1,208 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <drivers/apple/gpio.h>
+#include <platform.h>
+#include <platform/soc/hwregbase.h>
+#include <target.h>
+
+/* Default S5L8947X SoC Pin Configuration */
+
+#define FMI_DRIVE_STR	DRIVE_X2
+#define FMI_SLEW_RATE	SLEW_RATE_SLOW
+
+#if !WITH_TARGET_CONFIG
+static const u_int32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
+/* Port  0 */
+	CFG_DISABLED,							// I2S0_MCK		->
+	CFG_IN,								// I2S0_LRCK		->
+	CFG_DISABLED,							// I2S0_BCLK		->
+	CFG_DISABLED,							// I2S0_DOUT		->
+	CFG_DISABLED,							// I2S0_DIN		->
+	CFG_DISABLED,							// UART0_TXD		->
+	CFG_DISABLED,							// UART0_RXD		->
+	CFG_DISABLED,							// UART1_TXD		->
+
+/* Port  1 */
+	CFG_DISABLED,							// UART1_RXD		->
+	CFG_DISABLED,							// I2C1_SDA		->
+	CFG_DISABLED,							// I2C1_SCL		->
+	CFG_DISABLED,							// HDMI_HPD		->
+	CFG_DISABLED,							// HDMI_CEC		->
+	CFG_DISABLED,							// I2C2_SDA		->
+	CFG_DISABLED,							// I2C2_SCL		->
+	CFG_DISABLED,							// SPDIF		->
+
+/* Port  2 */
+	CFG_DISABLED,							// GPIO22		->
+	CFG_DISABLED,							// GPIO23		->
+	CFG_DISABLED,							// UART2_TXD		->
+	CFG_DISABLED,							// UART2_RXD		->
+	CFG_DISABLED,							// UART2_RTSN		->
+	CFG_DISABLED,							// UART2_CTSN		->
+	CFG_DISABLED,							// UART3_TXD		->
+	CFG_DISABLED,							// UART3_RXD		->
+
+/* Port  3 */
+	CFG_DISABLED,							// UART4_TXD		->
+	CFG_DISABLED,							// UART4_RXD		->
+	CFG_DISABLED,							// TST_CLKOUT		->
+	CFG_DISABLED | PULL_DOWN,					// TST_STPCLK		->
+	CFG_DISABLED,							// WDOG			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port  4 */
+	CFG_DISABLED,							// ENET_MDC		->
+	CFG_DISABLED,							// ENET_MDIO		->
+	CFG_DISABLED,							// RMII_CLK		->
+	CFG_DISABLED,							// RMII_RXER		->
+	CFG_DISABLED,							// RMII_TXD[0]		->
+	CFG_DISABLED,							// RMII_CRSDV		->
+	CFG_DISABLED,							// RMII_RXD[0]		->
+	CFG_DISABLED,							// RMII_RXD[1]		->
+
+/* Port  5 */
+	CFG_DISABLED,							// RMII_TXD[1]		->
+	CFG_DISABLED,							// RMII_TXEN		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN[1]		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN[0]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_WEN		->
+
+/* Port  6 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[7]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[6]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[5]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[4]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[3]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[2]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[1]		->
+
+/* Port  7 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[0]		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN[1]		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN[0]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[7]		->
+
+/* Port  8 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[6]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[5]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[4]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[3]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[2]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[1]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[0]		->
+
+/* Port  9 */
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+
+/* Port 10 */
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+
+/* Port 11 */
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+
+/* Port 12 */
+	CFG_IN,								// GPIO0		-> MENU_KEY
+	CFG_IN,								// GPIO1		-> HOLD_KEY
+	CFG_DISABLED,							// GPIO2		->
+	CFG_DISABLED,							// GPIO3		->
+	CFG_DISABLED,							// GPIO4		->
+	CFG_DISABLED,							// GPIO5		->
+	CFG_DISABLED,							// GPIO6		->
+	CFG_DISABLED,							// GPIO7		->
+
+/* Port 13 */
+	CFG_DISABLED,							// GPIO8		->
+	CFG_DISABLED,							// GPIO9		->
+	CFG_DISABLED,							// GPIO10		->
+	CFG_DISABLED,							// GPIO11		->
+	CFG_DISABLED,							// GPIO12		->
+	CFG_DISABLED,							// GPIO13		->
+	CFG_DISABLED,							// GPIO14		->
+	CFG_DISABLED,							// GPIO15		->
+
+/* Port 14 */
+	CFG_DISABLED,							// GPIO16		-> BOARD_ID[3]
+	CFG_DISABLED,							// GPIO17		->
+	CFG_DISABLED,							// GPIO18		-> BOOT_CONFIG[0]
+	CFG_DISABLED,							// GPIO19		-> KEEPACT
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 15 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 16 */
+	CFG_DISABLED,							// GPIO20		->
+	CFG_DISABLED,							// GPIO21		->
+	CFG_DISABLED,							// GPIO24		->
+	CFG_DISABLED,							// GPIO25		-> BOOT_CONFIG[1]
+	CFG_IN | PULL_DOWN,						// GPIO26		-> FORCE_DFU
+	CFG_DISABLED | PULL_DOWN,					// GPIO27		-> DFU_STATUS
+	CFG_DISABLED,							// GPIO28		-> BOOT_CONFIG{2]
+	CFG_DISABLED,							// GPIO29		-> BOOT_CONFIG[3]
+
+/* Port 17 */
+	CFG_DISABLED,							// I2C0_SDA		->
+	CFG_DISABLED,							// I2C0_SCL		->
+	CFG_DISABLED,							// TMR32_PWM0		->
+	CFG_DISABLED,							// SPI0_SCLK		-> SPI0_SCLK/BOARD_ID[0]
+	CFG_DISABLED,							// SPI0_MOSI		-> SPI0_MOSI/BOARD_ID[1]
+	CFG_DISABLED,							// SPI0_MISO		-> SPI0_MISO/BOARD_ID[2]
+	CFG_DISABLED | PULL_UP,						// SPI0_SSIN		->
+	CFG_DISABLED,							// SWI_DATA		->
+};
+
+const uint32_t *platform_get_default_gpio_cfg(uint32_t gpioc)
+{
+	return gpio_default_cfg;
+}
+#endif

platform/s5l8940x/pmgr/rules.mk

@@ -0,0 +1,17 @@
+# Copyright (C) 2008 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_CLOCKS=1 \
+	WITH_HW_PLATFORM_POWER=1 \
+	WITH_HW_POWER_GATING=0
+
+ALL_OBJS += $(LOCAL_DIR)/pmgr.o

platform/s5l8940x/rules.mk

@@ -0,0 +1,124 @@
+# Copyright (C) 2009-2013 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR	:= $(GET_LOCAL_DIR)
+
+GLOBAL_INCLUDES += $(LOCAL_DIR)/include
+
+# modules implied by this platform
+MODULES		+= \
+	platform/defaults \
+	platform/generic \
+	arch/$(ARCH)
+
+##############################################################################
+# Code running on the main CPU
+#
+ifeq ($(PLATFORM_VARIANT),)
+
+ARM_CPU		:= cortex-a9
+
+MAX_DFU_SIZE	:= 180224
+
+ifeq ($(TEXT_BANK),srom)
+TEXT_BASE	:= 0x00000000
+endif
+ifeq ($(TEXT_BANK),sram)
+TEXT_BASE	:= 0x34000000
+endif
+ifeq ($(TEXT_BANK),sdram)
+TEXT_BASE	:= 0x9FF00000
+endif
+
+# Platform target can override any of these sizes by specifying in target config file (apps/iBoot/$target-config.mk)
+ifeq ($(DISPLAY_SIZE),)
+ DISPLAY_SIZE       := 15*1024*1024
+endif
+
+OPTIONS		+= \
+	AIC_CPU_ID=0 \
+	WITH_CLASSIC_SUSPEND_TO_RAM=1 \
+	WITH_LEGACY_PANIC_LOGS=1 \
+	WITH_NO_RANDOM_HEAP_COOKIE=1 \
+	WITH_NO_RANDOM_STACK_COOKIE=1 \
+	WITH_NON_COHERENT_DMA=1 \
+	WITH_ROM_TRAMPOLINE=1 \
+	PLATFORM_ENTROPY_RATIO=200 \
+	PLATFORM_IRQ_COUNT=192 \
+	TEXT_BASE="$(TEXT_BASE)" \
+	DISPLAY_SIZE="($(DISPLAY_SIZE)ULL)" \
+	TEXT_FOOTPRINT="$(TEXT_FOOTPRINT)" \
+	DISPLAY_BASE_NONALIGNED
+
+#	L2_CACHE_SIZE=1048576 \
+#
+
+GLOBAL_LDFLAGS	+= \
+	-seg1addr $(TEXT_BASE)
+
+ifeq ($(APPLICATION),SecureROM)
+# This selects the start of the DATA segment and the end of the INSECURE_MEMORY area
+DATA_BASE	:= 0x3402C000
+
+OPTIONS		+= \
+	DATA_BASE="$(DATA_BASE)"
+
+GLOBAL_LDFLAGS	+= \
+	-segaddr __DATA $(DATA_BASE)
+endif
+
+ALL_OBJS	+= $(LOCAL_DIR)/init.o \
+		   $(LOCAL_DIR)/pinconfig_$(SUB_PLATFORM).o
+
+endif
+
+##############################################################################
+# Code running on the IOP
+#
+ifeq ($(PLATFORM_VARIANT),IOP)
+
+OPTIONS		+= \
+	PLATFORM_VARIANT_IOP=1 \
+	AIC_CPU_ID=2 \
+	WITH_PLATFORM_HALT=1 \
+	SUPPORT_SLEEP=1 \
+	WITH_IOP_POWER_GATING=1 \
+	DEEP_IDLE_THRESHOLD_US=10000
+
+ARM_CPU		:=	cortex-a5
+
+TEXT_BASE	:=	0x0
+
+OPTIONS		+= \
+	TEXT_BASE="$(TEXT_BASE)"
+
+ALL_OBJS	+= $(LOCAL_DIR)/iop_init.o
+endif
+
+##############################################################################
+# Code running on the audio engine
+#
+ifeq ($(PLATFORM_VARIANT),Audio)
+
+OPTIONS		+= \
+	PLATFORM_VARIANT_AUDIO=1 \
+	WITH_PLATFORM_HALT=1 \
+	SUPPORT_SLEEP=1
+
+ARM_CPU		:=	cortex-a5
+
+TEXT_BASE	:=	0x0
+
+OPTIONS		+= \
+	TEXT_BASE="$(TEXT_BASE)" \
+	TEXT_FOOTPRINT="$(TEXT_FOOTPRINT)"
+
+ALL_OBJS	+= $(LOCAL_DIR)/iop_init.o
+
+endif