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@@ -0,0 +1,269 @@
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/*
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* Copyright (C) 2009-2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <drivers/amc/amc.h>
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#include <drivers/amc/amc_phy.h>
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#include <drivers/amc/amc_regs.h>
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#include <drivers/dram.h>
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#include <drivers/miu.h>
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#include <sys.h>
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#include <debug.h>
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int mcu_initialize_dram (bool resume)
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{
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return amc_init(resume);
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}
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void mcu_bypass_prep (int step)
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{
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amc_phy_bypass_prep(step);
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}
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uint64_t mcu_get_memory_size (void)
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{
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return amc_get_memory_size();
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}
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void amc_configure_address_decoding_and_mapping (void)
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{
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amc_configure_default_address_decoding_and_mapping();
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}
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void amc_enable_slow_boot (bool enable)
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{
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int slow_freqsel;
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if (enable) {
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if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
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rAMC_FREQSEL = amc_params.freqsel;
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return;
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}
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slow_freqsel = 3;
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rAMC_BOOTCLK = (amc_params.bootclkdivsr << 8) | 1;
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spin(5);
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rAMC_FREQSEL = slow_freqsel;
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amc_phy_scale_dll(slow_freqsel, amc_params.bootclkdivsr);
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} else {
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if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
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return;
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}
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rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_small;
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spin(2);
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rAMC_BOOTCLK &= ~1;
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spin(5);
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rAMC_FREQSEL = amc_params.freqsel;
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amc_phy_scale_dll(amc_params.freqsel, 1);
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rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_guided;
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}
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}
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void amc_finalize (bool resume)
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{
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uint8_t odts;
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#if SUPPORT_FPGA
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rAMC_PWRMNGTEN |= 0x00000001; // Sharing clocks between channels so do not enable clock stopping for PD or SR
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#else // SUPPORT_FPGA
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rAMC_PWRMNGTEN |= 0x00001001;
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#endif // SUPPORT_FPGA
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amc_mrcmd(MR_READ, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x4, (uintptr_t)&odts);
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rAMC_ODTS = 0x00010080; // [16] => TempDrtEn, [9:0] RdIntrvl XXX based on tREFI
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rAMC_PWRMNGTEN |= 0x00010000; // Enable srclkoff as well
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if (!resume) {
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amc_enable_autorefresh();
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}
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#if !SUPPORT_FPGA
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// Turn of Fast Critical Word Forwarding feature and AIU CWF feature
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// Disabled for NRT <rdar://problem/9416881>
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rAMC_AIUPRT_RD_CWF = 0x0001011f;
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rAMC_QBRPARAM = 0x00020200;
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rAMC_QBREN = 0x00111001;
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#endif
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}
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void amc_dram_workarounds (bool resume)
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{
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const struct amc_memory_device_info *dev_info;
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uint32_t chip_id = platform_get_chip_id();
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uint8_t i;
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dev_info = amc_get_memory_device_info();
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switch (dev_info->vendor_id) {
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case JEDEC_MANUF_ID_SAMSUNG:
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// <rdar://problem/9454992> H4P Samsung 35nm LPDDR2 Transition for N94
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// TMRS for Samsung 46nm part only
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if ((chip_id == 0x8940) && (!resume) && (dev_info->rev_id == 0)) {
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// Test MRS Entry
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xff);
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// Apply Samsung workaround <rdar://problem/9032765>
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// Column Select Line pull in (230ps) TMRS(1)
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x80);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x04);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x08);
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// Latch command
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
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// Column Select Line pull in (230ps) TMRS(2)
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x40);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x01);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
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// Latch command
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
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}
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// <rdar://problem/11060879> Samsung 3xnm DRAMs - not functional
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else if ((chip_id == 0x8942) && (!resume) && (dev_info->rev_id == 1) && (dev_info->rev_id2 == 0)) {
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// Test MRS Entry
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xff);
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// PDL_M(-500ps)
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x80);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x01);
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// Latch Command
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
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}
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break;
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case JEDEC_MANUF_ID_HYNIX:
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if (dev_info->rev_id == 0) {
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if (!resume) {
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// Test MRS Exit "just in case" <rdar://problem/8769095>
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
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// Apply Hynix cold clamp disable workaround <rdar://problem/8907487>
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// (but only for revid2 == 0 <rdar://problem/8943860>)
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if ((chip_id == 0x8940) && (dev_info->rev_id2 == 0)) {
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// Test MRS Entry
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xb0);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xe0);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x90);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xa2);
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}
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// IOSTBP Start Time control (600ps delay)
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if ((chip_id == 0x8942) && (dev_info->density == JEDEC_DENSITY_1Gb)) {
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// Test MRS Entry
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xb0);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xe0);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x90);
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for (i = 0; i < 13; i++) {
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x99);
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}
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}
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}
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#if !SUB_TARGET_K93 && !SUB_TARGET_K94 && !SUB_TARGET_K95 && !SUB_TARGET_J33
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// <rdar://problem/9585266> H4G UM Update: Modified setting for tMRR timing parameter
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// override tMRR to 3 cycles (only if performing dynamic calibration)
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if (dev_info->density == JEDEC_DENSITY_2Gb) {
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rAMC_MODE_FREQ(0) = amc_params.freq[0].modereg | 0x3;
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}
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#endif
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} else if ((dev_info->rev_id == 1) && (dev_info->rev_id2 == 0)) {
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// <rdar://problem/11059277> Hynix 3xnm workaround solution
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if ((chip_id == 0x8942) && (!resume)) {
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// Test MRS Entry
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xb0);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xe0);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x90);
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// Yi Enable +1 step
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for (i = 0; i < 4; i++) {
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xf1);
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}
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// Yi Pulse +1 step
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for (i = 0; i < 4; i++) {
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x94);
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}
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}
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}
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break;
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default:
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break;
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}
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}
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// Shift dq offset as needed.
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// In the future, it's possible the shift value changes based on SOC or DRAM vendor.
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// Thus, we need to have this function per SOC.
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void amc_dram_shift_dq_offset (int8_t *dq_offset, uint8_t num_bytes) {
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int8_t shift_val;
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uint8_t i;
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const struct amc_memory_device_info *dev_info;
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uint32_t chip_id = platform_get_chip_id();
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// Do nothing for H4P
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if (chip_id == 0x8940)
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return;
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// <rdar://problem/11802718> H4A: Need additional DQ WR/RD static offsets
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dev_info = amc_get_memory_device_info();
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shift_val = 0;
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switch (dev_info->vendor_id) {
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case JEDEC_MANUF_ID_SAMSUNG:
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case JEDEC_MANUF_ID_HYNIX:
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// -3 step shift for DRAMs not used in K93A or J33
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if (dev_info->rev_id > 0)
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shift_val = -3;
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break;
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case JEDEC_MANUF_ID_ELPIDA:
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// -3 step shift for DRAMs not used in K93A or J33
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if (dev_info->rev_id > 1)
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shift_val = -3;
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break;
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default:
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dprintf(DEBUG_INFO, "Not applyig any shift to dq offsets for vendor: %d\n", dev_info->vendor_id);
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break;
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}
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for (i = 0; i < num_bytes; i++)
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dq_offset[i] += shift_val;
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}
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@@ -0,0 +1,135 @@
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/*
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* Copyright (C) 2010-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
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* Apple Inc.
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||||
*/
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#include <drivers/amc/amc.h>
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#include <drivers/amc/amc_phy.h>
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#include <drivers/amc/amc_regs.h>
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#include <drivers/dram.h>
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#include <drivers/miu.h>
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#include <sys.h>
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int mcu_initialize_dram (bool resume)
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{
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return amc_init(resume);
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}
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void mcu_bypass_prep (int step)
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{
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amc_phy_bypass_prep(step);
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}
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uint64_t mcu_get_memory_size (void)
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{
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return amc_get_memory_size();
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}
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void amc_configure_address_decoding_and_mapping (void)
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{
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amc_configure_default_address_decoding_and_mapping();
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}
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void amc_enable_slow_boot (bool enable)
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{
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int slow_freqsel;
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if (enable) {
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if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
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rAMC_FREQSEL = amc_params.freqsel;
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return;
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}
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slow_freqsel = 3;
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rAMC_BOOTCLK = (amc_params.bootclkdivsr << 8) | 1;
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spin(5);
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rAMC_FREQSEL = slow_freqsel;
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amc_phy_scale_dll(slow_freqsel, amc_params.bootclkdivsr);
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} else {
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if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
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return;
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}
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rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_small;
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spin(2);
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rAMC_BOOTCLK &= ~1;
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spin(5);
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rAMC_FREQSEL = amc_params.freqsel;
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amc_phy_scale_dll(amc_params.freqsel, 1);
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rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_guided;
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}
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}
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void amc_finalize (bool resume)
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{
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uint8_t odts;
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#if SUPPORT_FPGA
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rAMC_PWRMNGTEN |= 0x00000001; // Sharing clocks between channels so do not enable clock stopping for PD or SR
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#else
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rAMC_PWRMNGTEN |= 0x00011011;
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#endif
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rAMC_AREFPARAM |= (0x00001000); // Turn on freq change waiting for refresh and self-refresh exit
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amc_mrcmd(MR_READ, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x4, (uintptr_t)&odts);
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rAMC_ODTS = 0x00010320; // [16] => TempDrtEn, [9:0] RdIntrvl XXX based on tREFI
|
||||
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if (!resume) {
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amc_enable_autorefresh();
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}
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||||
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||||
#if SUPPORT_FPGA
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rAMC_FREQSEL = amc_params.freqsel;
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#endif
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||||
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#if !SUPPORT_FPGA
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// Turn of Fast Critical Word Forwarding feature and AIU CWF feature
|
||||
// Disabled for NRT <rdar://problem/9416881>
|
||||
rAMC_AIUPRT_RD_CWF = 0x00161600;
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rAMC_QBRPARAM = 0x00810000;
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rAMC_QBREN = 0x00111001;
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#endif
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}
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void amc_dram_workarounds (bool resume)
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{
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// XXX - Possibly look in s5l8950x amc.c to see possible workarounds.
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return;
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}
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||||
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||||
// Shift dq offset as needed.
|
||||
// In the future, it's possible the shift value changes based on SOC or DRAM vendor.
|
||||
// Thus, we need to have this function per SOC.
|
||||
void amc_dram_shift_dq_offset (int8_t *dq_offset, uint8_t num_bytes) {
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int8_t shift_val;
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uint8_t i;
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const struct amc_memory_device_info *dev_info;
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dev_info = amc_get_memory_device_info();
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||||
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||||
switch (dev_info->vendor_id) {
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||||
case JEDEC_MANUF_ID_HYNIX:
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||||
case JEDEC_MANUF_ID_SAMSUNG:
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||||
case JEDEC_MANUF_ID_ELPIDA:
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||||
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// shift 2 steps
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||||
shift_val = -2;
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||||
break;
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||||
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default:
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shift_val = 0;
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break;
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||||
}
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||||
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||||
for (i = 0; i < num_bytes; i++)
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||||
dq_offset[i] += shift_val;
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||||
}
|
||||
@@ -0,0 +1,21 @@
|
||||
# Copyright (C) 2009-2011 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_AMC=1
|
||||
|
||||
ifneq ($(SUB_PLATFORM), s5l8947x)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/amc_s5l8940x.o
|
||||
else
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/amc_s5l8947x.o
|
||||
endif
|
||||
Reference in new issue
Block a user