first and last commit

2023-07-08 13:03:17 -07:00
commit 1bf4efd552
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2010-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#include <drivers/amc/amc.h>
+#include <drivers/amc/amc_phy.h>
+#include <drivers/amc/amc_regs.h>
+#include <drivers/dram.h>
+#include <drivers/miu.h>
+#include <sys.h>
+
+int mcu_initialize_dram (bool resume)
+{
+	return amc_init(resume);
+}
+
+void mcu_bypass_prep (int step)
+{
+	amc_phy_bypass_prep(step);
+}
+
+uint64_t mcu_get_memory_size (void)
+{
+	return amc_get_memory_size();
+}
+
+void amc_configure_address_decoding_and_mapping (void)
+{
+	amc_configure_default_address_decoding_and_mapping();
+}
+
+void amc_enable_slow_boot (bool enable)
+{
+	int slow_freqsel;
+	
+	if (enable) {
+		if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
+			rAMC_FREQSEL = amc_params.freqsel;
+			return;
+		}
+
+		slow_freqsel = 3;
+		rAMC_BOOTCLK = (amc_params.bootclkdivsr << 8) | 1;
+		spin(1);
+		rAMC_FREQSEL = slow_freqsel;
+		amc_phy_scale_dll(slow_freqsel, amc_params.bootclkdivsr);		
+	} else {
+		if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
+			return;
+		}
+		
+		rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_small;
+		spin(2);
+
+		rAMC_BOOTCLK &= ~1;
+		spin(1);
+		rAMC_FREQSEL = amc_params.freqsel;
+		amc_phy_scale_dll(amc_params.freqsel, 1);
+
+		rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_guided;
+	}
+}
+
+void amc_finalize (bool resume)
+{
+	uint8_t odts;
+
+#if SUPPORT_FPGA
+	rAMC_PWRMNGTEN |= 0x00000001;			// Sharing clocks between channels so do not enable clock stopping for PD or SR
+#else
+	rAMC_PWRMNGTEN |= 0x00011011;
+#endif
+
+	rAMC_AREFPARAM |= (0x00001000);			// Turn on freq change waiting for refresh and self-refresh exit
+
+	amc_mrcmd(MR_READ, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x4, (uintptr_t)&odts);
+	rAMC_ODTS      = 0x00010320;			// [16] => TempDrtEn, [9:0] RdIntrvl XXX based on tREFI
+
+	if (!resume) {
+		amc_enable_autorefresh();
+	}
+
+#if SUPPORT_FPGA
+	rAMC_FREQSEL = amc_params.freqsel;
+#endif
+
+#if !SUPPORT_FPGA
+	// Turn of Fast Critical Word Forwarding feature and AIU CWF feature
+	// Disabled for NRT <rdar://problem/9416881>
+	rAMC_AIUPRT_RD_CWF     = 0x00161600;
+	rAMC_QBRPARAM          = 0x00810000;
+	rAMC_QBREN             = 0x00111001;
+#endif
+}
+
+void amc_dram_workarounds (bool resume)
+{
+	const struct amc_memory_device_info *dev_info;
+	
+	dev_info = amc_get_memory_device_info();
+	
+	switch (dev_info->vendor_id) {			
+		case JEDEC_MANUF_ID_HYNIX:
+			
+			if (dev_info->rev_id == 1 && dev_info->rev_id2 == 0) {
+				if (!resume) {
+					// TestMRS entry
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xb0);
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xe0);
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x90);
+					
+					// <rdar://problem/10721112>					
+					// tRAS_min default
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xee);
+					
+					// <rdar://problem/11216915>					
+					// LSAEN delay default
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xef);
+				}
+			}
+			break;
+			
+		default:
+			break;
+	}
+	
+	return;
+}
+
+// Shift dq offset as needed.
+// In the future, it's possible the shift value changes based on SOC or DRAM vendor.
+// Thus, we need to have this function per SOC.
+void amc_dram_shift_dq_offset (int8_t *dq_offset, uint8_t num_bytes) {
+	int8_t shift_val;
+	uint8_t i;
+	const struct amc_memory_device_info *dev_info;
+	
+	dev_info = amc_get_memory_device_info();
+	
+	switch (dev_info->vendor_id) {			
+		case JEDEC_MANUF_ID_HYNIX:
+		case JEDEC_MANUF_ID_SAMSUNG:
+		case JEDEC_MANUF_ID_ELPIDA:
+			
+			// shift 2 steps
+			shift_val = -2;
+			break;
+			
+		default:
+			shift_val = 0;
+			break;
+	}
+	
+	for (i = 0; i < num_bytes; i++)
+		dq_offset[i] += shift_val;	
+}
@@ -0,0 +1,16 @@
+# Copyright (C) 2011 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_AMC=1
+
+ALL_OBJS += \
+	$(LOCAL_DIR)/amc.o
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2010-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <arch/arm/assembler.h>
+
+	.text
+
+ARM_FUNCTION _platform_start
+	
+	// Configure the first half of the cache as RAM
+	mov		r2, #0xFF000000			// L2CCONFIG0.AcpMask[7:0] = 0xFF
+	orr		r2, r2, #0x000F0000		// L2CCONFIG0.RamWayMask[7:0] = 0x0F
+	orr		r2, r2, #0x00000002		// L2CCONFIG0.RamEna = 1
+	mcr		p15, 1, r2, c15, c2, 0		// Write to L2CCONFIG0
+	isb						// Wait for the write to take effect
+	bx		lr
+
+	
+ARM_FUNCTION _miu_read_l2cadrmap
+	
+	mrc		p15, 1, r0, c15, c2, 4
+	bx		lr
+
+	
+ARM_FUNCTION _miu_write_l2cadrmap
+	
+	mcr		p15, 1, r0, c15, c2, 4
+	isb
+	bx 		lr
@@ -0,0 +1,251 @@
+/*
+ * Copyright (C) 2010-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <lib/env.h>
+#include <platform.h>
+#include <platform/soc/chipid.h>
+#include <platform/soc/hwclocks.h>
+
+#if SUPPORT_FPGA
+#define _rCFG_FUSE0				(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x00))
+#undef rCFG_FUSE0
+// XXX ECID (1 << 7)?
+// XXX double-check memory values
+#define rCFG_FUSE0		((0 << 31) | (3 << 28) | (0xE << 24) | (2 << 22) | \
+			 (0 << 9) | (1 << 8) | (3 << 4) | (kPlatformSecurityDomainDarwin << 2) | (0 << 1) | (0 << 0) | \
+			 _rCFG_FUSE0)
+#endif
+
+#if SUB_PLATFORM_S5L8950X
+// H5 Tunables rev 0.59 & H5P Test Plan rev 1.13
+#define MINIMUM_BINNING_VERSION	(1)
+static u_int32_t default_soc_voltages[CHIPID_SOC_VOLTAGE_COUNT] = { 950, 1000, 1100 };
+static u_int32_t default_cpu_voltages[CHIPID_CPU_VOLTAGE_COUNT] = { 810, 935, 1020, 1065, 1100, 1145, 0, 0 };
+static u_int32_t default_ram_voltages[CHIPID_RAM_VOLTAGE_COUNT] = { 950, 1000 };
+#endif
+
+static u_int32_t chipid_get_binning_revision(void);
+static u_int32_t chipid_get_base_voltage(void);
+
+bool chipid_get_production_mode(void)
+{
+	return ((rCFG_FUSE0 >> 0) & 1) != 0;
+}
+
+void chipid_clear_production_mode(void)
+{
+#if SUPPORT_FPGA
+	_rCFG_FUSE0 &= ~1;
+#else
+	rCFG_FUSE0 &= ~1;
+#endif
+}
+
+bool chipid_get_secure_mode(void)
+{
+	return ((rCFG_FUSE0 >> 1) & 1) != 0;
+}
+
+u_int32_t chipid_get_security_domain(void)
+{
+	return (rCFG_FUSE0 >> 2) & 3;
+}
+
+u_int32_t chipid_get_board_id(void)
+{
+	return (rCFG_FUSE0 >> 4) & 3;
+}
+
+bool chipid_get_ecid_image_personalization_required(void)
+{
+	return ((rCFG_FUSE0 >> 7) & 1) != 0;
+}
+
+u_int32_t chipid_get_minimum_epoch(void)
+{
+	return (rCFG_FUSE0 >> 9) & 0x7F;
+}
+
+u_int32_t chipid_get_chip_id(void)
+{
+#if SUB_PLATFORM_S5L8950X
+        return 0x8950;
+#endif
+}
+
+u_int32_t chipid_get_chip_revision(void)
+{
+	return (((rECIDHI >> 13) & 0x7) << 4) | (((rECIDHI >> 10) & 0x7) << 0);
+}
+
+u_int32_t chipid_get_osc_frequency(void)
+{
+	return OSC_FREQ;
+}
+
+u_int64_t chipid_get_ecid_id(void)
+{
+	u_int64_t ecid = 0;
+
+#if SUPPORT_FPGA
+	ecid = 0x000012345678ABCDULL;
+#else
+	ecid |= ((rECIDLO >>  0)) & ((1ULL << (21 -  0)) - 1);	// LOT_ID
+
+	ecid <<= (26 - 21);
+	ecid |= ((rECIDLO >> 21)) & ((1ULL << (26 - 21)) - 1);	// WAFER_NUM
+
+	ecid <<= (10 -  2);
+	ecid |= ((rECIDHI >>  2)) & ((1ULL << (10 -  2)) - 1);	// Y_POS
+
+	ecid <<= (32 - 26);
+	ecid |= ((rECIDLO >> 26)) & ((1ULL << (32 - 26)) - 1);	// X_POS_H
+
+	ecid <<= ( 2 -  0);
+	ecid |= ((rECIDHI >>  0)) & ((1ULL << ( 2 -  0)) - 1);	// X_POS_L
+#endif
+
+	return ecid;
+}
+
+u_int64_t chipid_get_die_id(void)
+{
+	return ((u_int64_t)rECIDHI << 32) | rECIDLO;
+}
+
+u_int32_t chipid_get_soc_voltage(u_int32_t index)
+{
+	u_int32_t soc_voltage;
+	u_int64_t soc_bin_data;
+
+	if (index > CHIPID_SOC_VOLTAGE_COUNT) return 0;
+
+	if (chipid_get_binning_revision() < MINIMUM_BINNING_VERSION) {
+		// This part is unbinned to the binning version is not supported
+		// Use the default voltage
+		soc_voltage = default_soc_voltages[index];
+	} else {
+		// Read the SoC bin data from the fuses
+		soc_bin_data = ((((u_int64_t)rCFG_FUSE1) << 32) | rCFG_FUSE0) >> 25;
+
+		// Start with the base voltage
+		soc_voltage = chipid_get_base_voltage();
+
+		// Add in the correct bin from the "array"
+		soc_voltage += 5 * ((soc_bin_data >> (index * 7)) & 0x7F);
+	}
+
+	return soc_voltage;
+}
+
+u_int32_t chipid_get_cpu_voltage(u_int32_t index)
+{
+	u_int32_t cpu_voltage;
+	u_int64_t cpu_bin_data;
+
+	if (index > CHIPID_CPU_VOLTAGE_COUNT) return 0;
+
+	if (chipid_get_binning_revision() < MINIMUM_BINNING_VERSION) {
+		// This part is unbinned to the binning version is not supported
+		// Use the default voltage
+		cpu_voltage = default_cpu_voltages[index];
+	} else {
+		// Read the CPU bin data from the fuses
+		cpu_bin_data = ((((u_int64_t)rDVFM_FUSE(1)) << 32) | rDVFM_FUSE(0)) >> 5;
+
+		// Start with the base voltage
+		cpu_voltage = chipid_get_base_voltage();
+
+		// Add in the correct bin from the "array"
+		cpu_voltage += 5 * ((cpu_bin_data >> (index * 7)) & 0x7F);
+	}
+
+	return cpu_voltage;
+}
+
+#ifndef TARGET_RAM_VOLTAGE_OFFSET
+#define TARGET_RAM_VOLTAGE_OFFSET 0
+#endif
+
+u_int32_t chipid_get_ram_voltage(u_int32_t index)
+{
+	u_int32_t ram_voltage;
+
+	if (index > CHIPID_RAM_VOLTAGE_COUNT) return 0;
+	
+	// RAM voltage is not binned, use the default voltage
+	ram_voltage = default_ram_voltages[index] + TARGET_RAM_VOLTAGE_OFFSET;
+
+	return ram_voltage;
+}
+
+bool chipid_get_fuse_lock(void)
+{
+	return (rCFG_FUSE1 & (1 << 31)) != 0;
+}
+
+void chipid_set_fuse_lock(bool locked)
+{
+	if (locked) rCFG_FUSE1 |= 1 << 31;
+}
+
+int32_t chipid_get_cpu_temp_offset(u_int32_t cpu_number)
+{
+	int32_t temp_cal;
+
+	switch (cpu_number) {
+		case 0 : temp_cal = (rDVFM_FUSE(9) >>  0) & 0x7F; break;
+		case 1 : temp_cal = (rDVFM_FUSE(9) >> 16) & 0x7F; break;
+		default : return 0;
+	}
+
+	return 0x3B - temp_cal;
+}
+
+u_int32_t chipid_get_fused_thermal_sensor_70C(u_int32_t sensorID)
+{
+	u_int32_t temp_cal;
+
+	switch (sensorID) {
+		case 0: temp_cal = (rCFG_FUSE4 >>  8) & 0x7F; break;
+		case 1: temp_cal = (rCFG_FUSE4 >> 24) & 0x7F; break;
+		default : return 0;
+	}
+	
+	return temp_cal;
+}
+
+u_int32_t chipid_get_fused_thermal_sensor_25C(u_int32_t sensorID)
+{
+	u_int32_t temp_cal;
+
+	switch (sensorID) {
+		case 0: temp_cal = (rCFG_FUSE4 >>  0) & 0x7F; break;
+		case 1: temp_cal = (rCFG_FUSE4 >> 16) & 0x7F; break;
+		default : return 0;
+	}
+	
+	return temp_cal;	
+}
+
+u_int32_t chipid_get_fuse_revision(void)
+{
+        return (rCFG_FUSE0 >> 18) & 0xf;
+}
+
+static u_int32_t chipid_get_binning_revision(void)
+{
+	return (rDVFM_FUSE(1) >> (61 - 32)) & 7;
+}
+
+static u_int32_t chipid_get_base_voltage(void)
+{
+	return 25 * (1 + ((rDVFM_FUSE(0) >> 0) & 0x1F));
+}
@@ -0,0 +1,15 @@
+# Copyright (C) 2010 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_PLATFORM_CHIPID=1
+
+ALL_OBJS += $(LOCAL_DIR)/chipid.o
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2010-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#if WITH_TARGET_AMC_PARAMS
+#include <target/amcconfig.h>
+#else
+static const struct amc_param amc_params = {
+	.flags     	 	= (FLAG_AMC_PARAM_BUSTAT23 | FLAG_AMC_PARAM_SLOW_BOOT | FLAG_AMC_PARAM_RECONFIG | FLAG_AMC_PARAM_ENABLE_AIU),
+
+	.tREFi      		= 0x5d,
+	.longsrcnt  		= 0x2008,
+	.tREFi_1Gb		= 0x5d,
+	.longsrcnt_1Gb		= 0x2008,
+	.rdlat      		= 8,
+	.wrlat      		= 4,
+	.phyrdlat   		= 8,
+	.phywrlat   		= 4,
+	.pdn        		= 0x33000503,
+	.read       		= 0x00000103,
+	.bustat     		= 0x00222212,
+	.bustat2    		= 0x00222212,
+	.derate     		= 0x30b3177b,
+	.mcphyupdate		= 0x05030000,
+	.autoref_params		= 0x22,		// <rdar://problem/9133484> MIF: tREFBW violation due to freq change
+	.pwrmngtparam_small	= 0x00011000,
+	.pwrmngtparam_guided	= 0x01801000,
+	.chnldec		= 0x00000100,
+	.chnldec2		= 0x003ffffd,
+	.arefparam		= 0x0600a000,
+	.bootclkdivsr		= 10,
+	.aref_freq0		= 0x00100100,
+	.aref_freq1		= 0x00100100,
+	.srextrarefcnt		= 0x00010000,
+	.readleveling           = 0x01000301,
+
+	.freq     		= {
+		{	// 522MHz
+			.cas         = 0x0000040a,
+			.pch         = 0x00040816,
+			.act         = 0x1a060b0a,
+			.autoref     = 0x1f439000,
+			.selfref     = 0x00048080,
+			.modereg     = 0x002f0502,
+			.mifcassch   = 0x001f0111,
+		},
+		{	// 400MHz
+			.cas         = 0x00000008,
+			.pch         = 0x00000012,
+			.act         = 0x14050a08,
+			.autoref     = 0x18340000,
+			.selfref     = 0x00038000,
+			.modereg     = 0x00240000,
+			.mifcassch   = 0x00000010,
+		},
+		{	// 200MHz
+			.cas         = 0x00000004,
+			.pch         = 0x00000009,
+			.act         = 0x0a030504,
+			.autoref     = 0x0c1a0000,
+			.selfref     = 0x0001c000,
+			.modereg     = 0x00120000,
+			.mifcassch   = 0x00000000,
+		},
+		{	// 50 & 24MHz
+			.cas         = 0x00000003,
+			.pch         = 0x00000003,
+			.act         = 0x08020303,
+			.autoref     = 0x03070000,
+			.selfref     = 0x00007000,
+			.modereg     = 0x00060000,
+			.mifcassch   = 0x00000010,
+		}
+	}
+};
+
+static const struct amc_tunable amc_tunables[] = {
+	// These settings are common across all H4x and H5P.  Channel decode and hashing
+	// is done in mainline init code.  Any tunables that match hardware defaults are
+	// omitted here.
+
+	{ &rAMC_AIUPRT_CFG,		0x00070000 },		// address error enable
+	{ &rAMC_AIUPRT_RD_GEN,		0x00000018 },		// fence read detect on GFX
+	{ &rAMC_AIUPRT_WR,		0x00000001 },		// out-of-order write, ignore B-bit
+
+	{ &rAMC_AIU_CHNLDEC2,		0x003FFFFD },
+	
+	{ &rAMC_AIU_RDBRSTLEN,		0x01010101 },		// burst len is 64B
+	{ &rAMC_AIU_WRBRSTLEN,		0x01010101 },		// burst len is 64B
+
+	{ &rAMC_AIU_CPUSPCREQ,		0x00000019 },		// CPU ageout timer
+	{ &rAMC_AIU_GFXSPCREQ,		0x00000032 },		// GFX ageout timer
+	{ &rAMC_AIU_NRTSPCREQ,		0x00000032 },		// Hperf-NRT ageout timer
+	{ &rAMC_AIU_RTSPCREQ,		0x00000019 },		// Hperf-RT ageout timer
+	{ &rAMC_AIU_PUSHEN,		0x00001100 },		// only supported for Hperf-RT
+
+	{ &rAMC_OPIDLETMR,		0x00200000 },
+	{ &rAMC_OPTMRADJEN,		0x00000001 },
+	{ &rAMC_OPTMRADJPARAM,		0x20400064 },
+
+	{ &rAMC_MIFACTSCH,		0x00000001 },
+
+	{ &rAMC_PSQRQTIMER0,		0x00000040 },		// RTG bypass up to 64 transactions
+	{ &rAMC_PSQRQTIMER1,		0x00000018 },		// RTY bypass up to 24 transactions
+	{ &rAMC_PSQRQTIMER2,		0x00000020 },		// RTG bypass up to 32 transactions
+	{ &rAMC_PSQRQBRST,		0x040c040c },		// RTR transactions don't affect read burst size
+	{ &rAMC_PSQRQSCHCRD,		0x002028f5 },		// read credits = 2 * write credits
+	{ &rAMC_PSQWQBRST,		0x0208040c },		// RTR reads cause reduced write burst size
+	{ &rAMC_PSQWQSCHCRD,		0x001014f5 },		// write credits = 1/2 * read credits
+	{ &rAMC_MCUQOS,			0x00010f04 },		// RTG=4, RTY=15, enable pick-oldest-RTY
+	{ &rAMC_PWRMNGTPARAM,		0x03001000 },		// SelfRef timer = 384 cycles
+
+	// Platform specific
+	
+	{ &rAMC_AIU_RDMAXCRD,		0x3012097f },		// RT:NRT:CPU:GFX = 48:18:09:MAX
+	{ &rAMC_AIU_RDREFL,		0x280f087f },		// 5/6 of AIURDMAXCRD fields
+	{ &rAMC_AIU_WRMAXCRD,		0x3012097f },		// RT:NRT:CPU:GFX = 48:18:09:MAX
+	{ &rAMC_AIU_WRREFL,		0x280f087f },		// 5/6 of AIUWRMAXCRD fields
+
+	{ &rAMC_AIU_ADDRBANKHASH0,	0x00006db6 },		// Enable bank hashing, bank[0] derived from bits 0,3,6,..
+	{ &rAMC_AIU_ADDRBANKHASH1,	0x00005b6d },		// Enable bank hashing, bank[1] derived from bits 1,4,7,..
+	{ &rAMC_AIU_ADDRBANKHASH2,	0x000036db },		// Enable bank hashing, bank[2] derived from bits 2,5,8,..
+	{ &rAMC_AIU_CHNLCRD,		0x00180018 },
+	{ &rAMC_AIU_LLTSCHCTL,		0x00000001 },		// Ensure LLT traffic from all ports is treated as medium priority request in the AIU arbitration
+	{ &rAMC_MCUQOSLLT,		0x00010108 },
+
+	{ &rAMC_AIU_CHNLTM,		0x40006101 },
+	{ &rAMC_AIU_WPQSCH,		0x08000800 },		// set starvation counts to 8
+	{ &rAMC_PSQRQCTL1,		0x0000132a },
+	{ &rAMC_PSQWQCTL0,		0x00010100 },		// enable write merging
+	{ &rAMC_PSQWQCTL1,		0x00000180 },		// ages write out faster than default (1/2 SelfRef)
+};
+#endif
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+/*
+ * The amc_param struct is defined in drivers/apple/amp/amp.h, and this
+ * file should only by included from that amp.c.
+ */
+
+#if WITH_TARGET_AMP_PARAMS
+#include <target/ampconfig.h>
+#else
+static const struct amp_params amc_phy_params = {
+	.flags = (FLAG_AMP_PARAM_SUPPORT_FMCLK_OFF | FLAG_AMP_PARAM_FULLDIFFMODE),
+	.freq = {
+		{
+			.scl = 0x08,
+			.rdcapcfg = 0x00010308,
+		},
+		{
+			.scl = 0x0b,
+			.rdcapcfg = 0x00010306,
+		},
+		{
+			.scl = 0x16,
+			.rdcapcfg = 0x00010303,
+		},
+		{
+			.scl = 0x3f,
+			.rdcapcfg = 0x00010301,
+		},
+	},
+};
+#endif
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2010-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_GPIODEF_H
+#define __PLATFORM_GPIODEF_H
+
+/* S5L8950X specific gpio -> pin mappings */
+
+#include <platform/gpio.h>
+#include <platform/soc/hwregbase.h>
+
+#if WITH_TARGET_CONFIG
+# include <target/gpiodef.h>
+#endif
+
+/* define platform-specific gpios in a generic fashion here. */
+#define GPIO_IIC0_SCL		GPIO( 7, 3)
+#define GPIO_IIC0_SDA		GPIO( 7, 2)
+#define GPIO_IIC1_SCL		GPIO( 7, 5)
+#define GPIO_IIC1_SDA		GPIO( 7, 4)
+#define GPIO_IIC2_SCL		GPIO(11, 1)
+#define GPIO_IIC2_SDA		GPIO(11, 0)
+
+#define GPIO_BOARD_ID0		GPIO( 6, 2)
+#define GPIO_BOARD_ID1		GPIO( 6, 3)
+#define GPIO_BOARD_ID2		GPIO( 6, 4)
+#define GPIO_BOARD_ID3		GPIO( 2, 0)
+
+#define GPIO_BOOT_CONFIG0	GPIO( 2, 2)
+#define GPIO_BOOT_CONFIG1	GPIO(25, 5)
+#define GPIO_BOOT_CONFIG2	GPIO(26, 0)
+#define GPIO_BOOT_CONFIG3	GPIO(26, 1)
+
+#define GPIO_REQUEST_DFU1	GPIO( 0, 1)	// formerly known as HOLD_KEY
+#define GPIO_REQUEST_DFU2	GPIO( 0, 0)	// formerly known as MENU_KEY
+#define GPIO_FORCE_DFU		GPIO(25, 6)
+#define GPIO_DFU_STATUS		GPIO(25, 7)
+
+#define SPI_NOR0		(0)
+#define SPI_NOR3		(3)
+
+#if SUPPORT_FPGA
+#define GPIO_SPI0_CS		GPIO(GPIO_PAD_SPI, 0)
+#define GPIO_SPI3_CS		GPIO(GPIO_PAD_SPI, 3)
+#else
+#define GPIO_SPI0_CS		GPIO( 6, 5)
+#define GPIO_SPI3_CS		GPIO(10, 7)
+#endif
+
+#define GPIO_UART1_TXD		GPIO( 3, 0)
+
+#define GPIO_SYSTEM_RESET	GPIO(12, 2)
+
+#endif /* ! __PLATFORM_GPIODEF_H */
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_IMAGE_DEVICES_H
+#define __PLATFORM_IMAGE_DEVICES_H
+
+static const struct image_device platform_image_devices[] = {
+#if defined(WITH_NAND_BOOT)
+    { "nand_firmware", 0x00000 }
+#else
+#if defined(WITH_SW_H2FMI)
+    { "sw-h2fmi", 0x0000 }
+#else
+    { "nor0", 0x00000 }
+#endif
+#endif
+};
+
+#if WITH_SYSCFG
+static const struct image_device platform_syscfg_devices[] = {
+#if defined(WITH_NAND_BOOT)
+       { "nand_syscfg", 0x00000 }
+#else
+       { "nor0", 0x00000 }
+#endif
+};
+#endif /* WITH_SYSCFG */
+
+#endif /* ! __PLATFORM_IMAGE_DEVICES_H */
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_MEMCONFIG_H
+#define __PLATFORM_MEMCONFIG_H
+
+/* S5L8950X SoC Mem Pin Configuration */
+
+static const gpio_t memory_interface_gpios[] = {
+	/* Not needed */
+};
+#endif /* ! __PLATFORM_MEMCONFIG_H */
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2010-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_MEMMAP_H
+#define __PLATFORM_MEMMAP_H
+
+#include <platform/memmap_defaults.h>
+
+/* S5L8950X specific memory map */
+#define SDRAM_BASE			(0x80000000ULL)
+#define SDRAM_BANK_LEN			(0x20000000ULL)
+#define SDRAM_BANK_COUNT		(2)
+#define SDRAM_END			(SDRAM_BASE + (SDRAM_BANK_LEN * SDRAM_BANK_COUNT))
+#define VROM_BASE			(0x3F000000ULL)
+#define VROM_BANK_LEN			(0x00100000ULL)
+#define VROM_LEN			(0x00010000ULL)
+#define SRAM_BASE			(0x10000000ULL)
+#define SRAM_BANK_LEN			(0x00100000ULL)
+#define SRAM_LEN			(0x00080000ULL)
+
+/* Sleep token is stored at first physical page in kernel memory */
+#define SLEEP_TOKEN_BUFFER_BASE		(SDRAM_BASE)
+
+/* reserved area for panic info */
+#define PANIC_SIZE		(0x00004000ULL)
+#define PANIC_BASE		(SDRAM_END - PANIC_SIZE)
+
+/* reserved area for iBoot */
+#define IBOOT_SIZE		(0x00100000 - PANIC_SIZE)
+#define IBOOT_BASE		(PANIC_BASE - IBOOT_SIZE)
+#define PROTECTED_REGION_SIZE	IBOOT_SIZE
+
+/* reserved area for display */
+#define DISPLAY_SIZE		(0x00F00000ULL)
+#define DISPLAY_BASE		(IBOOT_BASE - DISPLAY_SIZE)
+
+/* where to stick the mmu tt, default heap and insecure memory*/
+#if APPLICATION_SECUREROM
+#define MMU_TT_SIZE		(0x4000ULL)
+#define MMU_TT_BASE		(SRAM_BASE + SRAM_LEN - MMU_TT_SIZE)
+#define MMU_NONCACHE0_SIZE	(SRAM_BANK_LEN)
+#define MMU_NONCACHE0_PBASE	(SRAM_BASE)
+#define MMU_NONCACHE0_VBASE	(SRAM_BASE + SRAM_BANK_LEN)
+
+#define STACK_SIZE		(0x3000ULL)
+#define STACK_BASE		(MMU_TT_BASE - STACK_SIZE)
+
+#define HEAP_END		(STACK_BASE)
+
+#ifndef __ASSEMBLY__
+
+#define INSECURE_MEMORY_BASE	(SRAM_BASE)
+#define INSECURE_MEMORY_SIZE	((uintptr_t)__segment_start(__DATA) - INSECURE_MEMORY_BASE)
+
+#endif /* ! __ASSEMBLY__ */
+
+#endif /* APPLICATION_SECUREROM */
+
+#if APPLICATION_IBOOT
+#define MMU_TT_SIZE		(0x4000ULL)
+#define MMU_TT_BASE		(TEXT_BASE + TEXT_FOOTPRINT - MMU_TT_SIZE)
+#define MMU_NONCACHE0_SIZE	(SRAM_BANK_LEN)
+#define MMU_NONCACHE0_PBASE	(SRAM_BASE)
+#define MMU_NONCACHE0_VBASE	(SRAM_BASE + SRAM_BANK_LEN * 3)
+#define MMU_NONCACHE1_SIZE	(0x40000000ULL)
+#define MMU_NONCACHE1_PBASE	(0x80000000ULL)
+#define MMU_NONCACHE1_VBASE	(0xC0000000ULL)
+
+#if WITH_DFU_MODE
+#define STACK_SIZE		(0x3000ULL)
+
+#define INSECURE_MEMORY_SIZE	(0x00200000ULL)
+#define INSECURE_MEMORY_BASE	(SDRAM_BASE + SDRAM_BANK_LEN - INSECURE_MEMORY_SIZE)
+
+#define HEAP_EXT_SIZE		(0x00100000ULL)
+#define HEAP_EXT_BASE		(INSECURE_MEMORY_BASE - HEAP_EXT_SIZE)
+
+#else /* !WITH_DFU_MODE */
+#define STACK_SIZE		(0x1000ULL)
+
+#define INSECURE_MEMORY_BASE	(SDRAM_BASE)
+#define INSECURE_MEMORY_SIZE	(DEFAULT_KERNEL_ADDRESS - SDRAM_BASE)
+
+#define SECURE_MEMORY_BASE	(INSECURE_MEMORY_BASE + INSECURE_MEMORY_SIZE)
+/* If only 1 bank is populated, this only clears to the alias of
+ * DISPLAY_BASE in the first bank. If 2 banks are populated, this
+ * clears all the was to DISPLAY_BASE in the second bank. */
+#define SECURE_MEMORY_SIZE	(DISPLAY_BASE - SECURE_MEMORY_BASE - SDRAM_BANK_LEN * 2 + platform_get_memory_size())
+
+#define HEAP_EXT_BASE		(DEFAULT_FREE_ADDRESS)
+#define HEAP_EXT_SIZE		(DISPLAY_BASE - SDRAM_BANK_LEN - HEAP_EXT_BASE)
+#endif /* !WITH_DFU_MODE */
+
+#define STACK_BASE		(MMU_TT_BASE - STACK_SIZE)
+
+#define HEAP_END		(STACK_BASE)
+
+#endif /* APPLICATION_IBOOT */
+
+#if APPLICATION_EMBEDDEDIOP
+# if ARCH_ARMv7
+#  define MMU_TT_SIZE		(0x4000ULL)
+# endif
+
+/* We use the SRAM in the AE2 block on AE2 targets. */
+#ifdef SRAM_BASE
+#undef SRAM_BASE
+#endif
+#define SRAM_BASE		(0x34000000ULL)
+
+#ifdef SRAM_BANK_LEN
+#undef SRAM_BANK_LEN
+#endif
+#define SRAM_BANK_LEN		(0x00100000ULL)
+
+#ifdef SRAM_LEN
+#undef SRAM_LEN
+#endif
+#define SRAM_LEN		(0x00040000ULL)
+
+#define AUDIO_SRAM_RESERVE	(0x1000ULL)
+#define USB_SRAM_RESERVE	(0x10000ULL)
+
+#if TARGET_S5L8950XAE2
+#define HEAP_EXT_BASE		(SRAM_BASE + AUDIO_SRAM_RESERVE)
+#define HEAP_EXT_SIZE		(SRAM_LEN - AUDIO_SRAM_RESERVE - USB_SRAM_RESERVE)
+#endif /* TARGET_S5L8950XAE2 */
+
+#endif /* !APPLICATION_EMBEDDEDIOP */
+
+#define SCRATCH_BASE     (0x33600000ULL)
+#define SCRATCH_LEN      (2048)
+
+#endif /* ! __PLATFORM_MEMMAP_H */
@@ -0,0 +1,310 @@
+/*
+ * Copyright (C) 2010-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_PINCONFIG_H
+#define __PLATFORM_PINCONFIG_H
+
+/* Default S5L8950X SoC Pin Configuration */
+
+#define FMI_DRIVE_STR	DRIVE_X2 | SLOW_SLEW
+
+static const u_int32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
+/* Port  0 */
+	CFG_IN,								// GPIO0		-> MENU_KEY (REQUEST_DFU2)
+	CFG_IN,								// GPIO1		-> HOLD_KEY (REQUEST_DFU1)
+	CFG_DISABLED,							// GPIO2		->
+	CFG_DISABLED,							// GPIO3		->
+	CFG_DISABLED,							// GPIO4		->
+	CFG_DISABLED,							// GPIO5		->
+	CFG_DISABLED,							// GPIO6		->
+	CFG_DISABLED,							// GPIO7		->
+
+/* Port  1 */
+	CFG_DISABLED,							// GPIO8		->
+	CFG_DISABLED,							// GPIO9		->
+	CFG_DISABLED,							// GPIO10		->
+	CFG_DISABLED,							// GPIO11		->
+	CFG_DISABLED,							// GPIO12		->
+	CFG_DISABLED,							// GPIO13		->
+	CFG_DISABLED,							// GPIO14		->
+	CFG_DISABLED,							// GPIO15		->
+
+/* Port  2 */
+	CFG_DISABLED,							// GPIO16		-> BOARD_ID[3]
+	CFG_DISABLED,							// GPIO17		->
+	CFG_DISABLED,							// GPIO18		-> BOOT_CONFIG[0]
+	CFG_DISABLED,							// GPIO19		->
+	CFG_DISABLED,							// EHCI_PORT_PWR[0]	->
+	CFG_DISABLED,							// EHCI_PORT_PWR[1]	->
+	CFG_DISABLED,							// EHCI_PORT_PWR[2]	->
+	CFG_DISABLED,							// EHCI_PORT_PWR[3]	->
+
+/* Port  3 */
+	CFG_DISABLED,							// UART1_TXD		->
+	CFG_DISABLED,							// UART1_RXD		->
+	CFG_DISABLED,							// UART1_RTSN		->
+	CFG_DISABLED,							// UART1_CTSN		->
+	CFG_DISABLED,							// UART2_TXD		->
+	CFG_DISABLED,							// UART2_RXD		->
+	CFG_DISABLED,							// UART2_RTSN		->
+	CFG_DISABLED,							// UART2_CTSN		->
+
+/* Port  4 */
+	CFG_DISABLED,							// UART3_TXD		->
+	CFG_DISABLED,							// UART3_RXD		->
+	CFG_DISABLED,							// UART3_RTSN		->
+	CFG_DISABLED,							// UART3_CTSN		->
+	CFG_DISABLED,							// UART4_TXD/SPI4_MOSI	->
+	CFG_DISABLED,							// UART4_RXD/SPI4_MISO	->
+	CFG_DISABLED,							// UART4_RTSN/SPI4_SCLK	->
+	CFG_DISABLED,							// UART4_CTSN/SPI4_SSIN	->
+
+/* Port  5 */
+	CFG_DISABLED,							// UART6_TXD		->
+	CFG_DISABLED,							// UART6_RXD		->
+	CFG_DISABLED,							// UART6_RTSN		->
+	CFG_DISABLED,							// UART6_CTSN		->
+	CFG_DISABLED,							// UART5_RXD/UART5_RTXD	->
+	CFG_DISABLED,							// UART5_TXD		->
+	CFG_DISABLED,							// SPI1_SCLK		->
+	CFG_DISABLED,							// SPI1_MOSI		->
+
+/* Port  6 */
+	CFG_DISABLED,							// SPI1_MISO		->
+	CFG_DISABLED,							// SPI1_SSIN		->
+	CFG_DISABLED,							// SPI0_SCLK		-> SPI0_SCLK/BOARD_ID[0]
+	CFG_DISABLED,							// SPI0_MOSI		-> SPI0_MOSI/BOARD_ID[1]
+	CFG_DISABLED,							// SPI0_MISO		-> SPI0_MISO/BOARD_ID[2]
+	CFG_DISABLED | PULL_UP,						// SPI0_SSIN		-> SPI0_SSIN
+	CFG_DISABLED,							// SPI2_SCLK		->
+	CFG_DISABLED,							// SPI2_MOSI		->
+
+/* Port  7 */
+	CFG_DISABLED,							// SPI2_MISO		->
+	CFG_DISABLED,							// SPI2_SSIN		->
+	CFG_DISABLED,							// I2C0_SDA		->
+	CFG_DISABLED,							// I2C0_SCL		->
+	CFG_DISABLED,							// I2C1_SDA		->
+	CFG_DISABLED,							// I2C1_SCL		->
+	CFG_DISABLED,							// ISP0_SDA		->
+	CFG_DISABLED,							// ISP0_SCL		->
+
+/* Port  8 */
+	CFG_DISABLED,							// ISP1_SDA		->
+	CFG_DISABLED,							// ISP1_SCL		->
+	CFG_DISABLED,							// MIPI_VSYNC		->
+	CFG_DISABLED,							// TMR32_PWM0		->
+	CFG_DISABLED,							// TMR32_PWM1		->
+	CFG_DISABLED,							// TMR32_PWM2		->
+	CFG_DISABLED,							// SWI_DATA		->
+	CFG_DISABLED,							// DWI_DI		->
+
+/* Port  9 */
+	CFG_DISABLED,							// DWI_DO		->
+	CFG_DISABLED,							// DWI_CLK		->
+	CFG_DISABLED,							// SENSOR0_RST		->
+	CFG_DISABLED,							// SENSOR0_CLK		->
+	CFG_DISABLED,							// SENSOR1_RST		->
+	CFG_DISABLED,							// SENSOR1_CLK		->
+	CFG_FUNC0,							// CPU0_SWITCH		->
+	CFG_FUNC0,							// CPU1_SWITCH		->
+
+/* Port 10 */
+	CFG_DISABLED,							// ISP0_PRE_FLASH	->
+	CFG_DISABLED,							// ISP0_FLASH		->
+	CFG_DISABLED,							// ISP1_PRE_FLASH	->
+	CFG_DISABLED,							// ISP1_FLASH		->
+	CFG_DISABLED,							// SPI3_MOSI		-> 
+	CFG_DISABLED,							// SPI3_MISO		-> 
+	CFG_DISABLED,							// SPI3_SCLK		-> 
+	CFG_DISABLED,							// SPI3_SSIN		-> 
+
+/* Port 11 */
+	CFG_DISABLED,							// I2C2_SDA		->
+	CFG_DISABLED,							// I2C2_SCL		->
+	CFG_DISABLED,							// GPIO_3V0		->
+	CFG_DISABLED,							// GPIO_3V1		->
+	CFG_DISABLED,							// DP_HPD		->
+	CFG_DISABLED,							// LPDP_HPD		->
+	CFG_DISABLED,							// UART0_TXD		->
+	CFG_DISABLED,							// UART0_RXD		->
+
+/* Port 12 */
+	CFG_DISABLED,							// TST_CLKOUT		->
+	CFG_DISABLED,							// TST_STPCLK		->
+	CFG_DISABLED,							// WDOG			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 13 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 14 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 15 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 16 */
+	CFG_DISABLED,							// I2S0_MCK		->
+	CFG_DISABLED,							// I2S0_LRCK		->
+	CFG_DISABLED,							// I2S0_BCLK		->
+	CFG_DISABLED,							// I2S0_DOUT		->
+	CFG_DISABLED,							// I2S0_DIN		->
+	CFG_DISABLED,							// I2S1_MCK		->
+	CFG_DISABLED,							// I2S1_LRCK		->
+	CFG_DISABLED,							// I2S1_BCLK		->
+
+/* Port 17 */
+	CFG_DISABLED,							// I2S1_DOUT		->
+	CFG_DISABLED,							// I2S1_DIN		->
+	CFG_DISABLED,							// I2S2_MCK		->
+	CFG_DISABLED,							// I2S2_LRCK		->
+	CFG_DISABLED,							// I2S2_BCLK		->
+	CFG_DISABLED,							// I2S2_DOUT		->
+	CFG_DISABLED,							// I2S2_DIN		->
+	CFG_DISABLED,							// I2S3_MCK		->
+
+/* Port 18 */
+	CFG_DISABLED,							// I2S3_LRCK		->
+	CFG_DISABLED,							// I2S3_BCLK		->
+	CFG_DISABLED,							// I2S3_DOUT		->
+	CFG_DISABLED,							// I2S3_DIN		->
+	CFG_DISABLED,							// I2S4_MCK		->
+	CFG_DISABLED,							// I2S4_LRCK		->
+	CFG_DISABLED,							// I2S4_BCLK		->
+	CFG_DISABLED,							// I2S4_DOUT		->
+
+/* Port 19 */
+	CFG_DISABLED,							// I2S4_DIN		->
+	CFG_DISABLED,							// SPDIF		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN3		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN2		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN1		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_ALE		->
+
+/* Port 20 */
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_WENN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO5		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO4		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_DQS		->
+
+/* Port 21 */
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_DQSN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO2		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO1		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO0		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN7		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN6		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN5		->
+
+/* Port 22 */
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN4		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN3		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN2		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN1		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_REN		->
+
+/* Port 23 */
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_WENN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO5		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO4		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_DQS		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_DQSN		->
+
+/* Port 24 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO2		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO1		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO0		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN7		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN6		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN5		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN4		->
+
+/* Port 25 */
+	CFG_DISABLED,							// GPIO20		->
+	CFG_DISABLED,							// GPIO21		->
+	CFG_DISABLED,							// GPIO22		->
+	CFG_DISABLED,							// GPIO23		->
+	CFG_DISABLED,							// GPIO24		->
+	CFG_DISABLED,							// GPIO25		-> BOOT_CONFIG[1]
+	CFG_IN | PULL_DOWN,						// GPIO26		-> FORCE_DFU
+	CFG_DISABLED | PULL_DOWN,					// GPIO27		-> DFU_STATUS
+
+/* Port 26 */
+	CFG_DISABLED,							// GPIO28		-> BOOT_CONFIG[2]
+	CFG_DISABLED,							// GPIO29		-> BOOT_CONFIG[3]
+	CFG_DISABLED,							// GPIO30		->
+	CFG_DISABLED,							// GPIO31		->
+	CFG_DISABLED,							//			->
+	CFG_DISABLED,							//			->
+	CFG_DISABLED,							//			->
+	CFG_DISABLED,							//			->
+
+/* Port 27 */
+	CFG_DISABLED,							//			->
+	CFG_DISABLED,							//			->
+	CFG_DISABLED,							//			->
+	CFG_DISABLED,							//			->
+	CFG_DISABLED,							//			->
+	CFG_DISABLED,							//			->
+	CFG_DISABLED,							//			->
+	CFG_DISABLED,							//			->
+
+/* Port 28 */
+	CFG_DISABLED,							// GPIO32		->
+	CFG_DISABLED,							// GPIO33		->
+	CFG_DISABLED,							// GPIO34		->
+	CFG_DISABLED,							// GPIO35		->
+	CFG_DISABLED,							// GPIO36		->
+	CFG_DISABLED,							// GPIO37		->
+	CFG_DISABLED,							// GPIO38		->
+	CFG_DISABLED,							// GPIO39		->
+};
+
+#endif /* ! __PLATFORM_PINCONFIG_H */
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2010-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_CHIPID_H
+#define __PLATFORM_SOC_CHIPID_H
+
+#include <platform/chipid.h>
+#include <platform/soc/hwregbase.h>
+
+#define	rCFG_FUSE0			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x00))
+#define	rCFG_FUSE1			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x04))
+#define	rCFG_FUSE2			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x08))
+#define	rCFG_FUSE3			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x0C))
+#define	rCFG_FUSE4			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x10))
+#define	rCFG_FUSE5			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x14))
+
+#define	rECIDLO				(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x20))
+#define	rECIDHI				(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x24))
+
+#define rDVFM_FUSE(n)			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x40 + (n) * 4))
+
+#define rSCC_FUSE(n)			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x80 + (n) * 4))
+
+extern bool chipid_get_ecid_image_personalization_required(void);
+
+#define CHIPID_SOC_VOLTAGE_COUNT	(3)
+#define CHIPID_SOC_VOLTAGE_LOW		(0)
+#define CHIPID_SOC_VOLTAGE_MED		(1)
+#define CHIPID_SOC_VOLTAGE_HIGH		(2)
+extern u_int32_t chipid_get_soc_voltage(u_int32_t index);
+
+#define CHIPID_CPU_VOLTAGE_COUNT	(8)
+extern u_int32_t chipid_get_cpu_voltage(u_int32_t index);
+
+#define CHIPID_RAM_VOLTAGE_COUNT	(2)
+#define CHIPID_RAM_VOLTAGE_LOW		(0)
+#define CHIPID_RAM_VOLTAGE_HIGH		(1)
+extern u_int32_t chipid_get_ram_voltage(u_int32_t index);
+
+extern int32_t chipid_get_cpu_temp_offset(u_int32_t cpu_number);
+
+extern u_int32_t chipid_get_fused_thermal_sensor_70C(u_int32_t sensorID);
+extern u_int32_t chipid_get_fused_thermal_sensor_25C(u_int32_t sensorID);
+extern u_int32_t chipid_get_fuse_revision(void);
+#endif /* __PLATFORM_SOC_CHIPID_H */
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2012-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __APPLE_DISPLAY_H
+#define __APPLE_DISPLAY_H
+
+// Platform-specific displaypipe tunables
+static struct adfe_v1_tuneable adfe_tuneables[] = 
+{
+	{
+		.name = "default",
+		.disp_dpcclkcntl[0] = 			0,
+		.disp_dpbclklvl_clock_off_level[0] =	DPBCLKLVL_OFFLVL(0x03F8),
+		.disp_dpbclklvl_clock_on_level[0] =	DPBCLKLVL_ONLVL(0x0200),
+		.disp_dpusrcstrd[0] =			DPUSRCSTRD_SRCBURST_8BLOCKS,
+		.disp_dpcqoscnfg[0] =			(DPCQOSCNFG_QOS_TIMER(0x0040)	| \
+							 DPCQOSCNFG_UIFIFO_ENABLE	| \
+							 DPCQOSCNFG_VIDFIFO_ENABLE	| \
+							 DPCQOSCNFG_QOS_ENABLE),
+		.disp_dpbqoslvl_med_watermark[0] =	DPBQOSLVL_MED_WATERMARK(0x0180),
+		.disp_dpbqoslvl_high_watermark[0] =	DPBQOSLVL_HIGH_WATERMARK(0x00C0),
+		.disp_dpureqcfg[0] =			0,
+
+		.disp_dpcclkcntl[1] = 			0,
+		.disp_dpbclklvl_clock_off_level[1] =	DPBCLKLVL_OFFLVL(0x03F8),
+		.disp_dpbclklvl_clock_on_level[1] =	DPBCLKLVL_ONLVL(0x03C0),
+		.disp_dpusrcstrd[1] =			DPUSRCSTRD_SRCBURST_4BLOCKS,
+		.disp_dpcqoscnfg[1] =			(DPCQOSCNFG_QOS_TIMER(0x2000)	| \
+							 DPCQOSCNFG_UIFIFO_ENABLE	| \
+							 DPCQOSCNFG_VIDFIFO_ENABLE	| \
+							 DPCQOSCNFG_QOS_ENABLE),
+		.disp_dpbqoslvl_med_watermark[1] =	DPBQOSLVL_MED_WATERMARK(0x0280),
+		.disp_dpbqoslvl_high_watermark[1] =	DPBQOSLVL_HIGH_WATERMARK(0x0190),
+		.disp_dpureqcfg[1] =			0,
+	},
+};
+
+#endif	/* ! __APPLE_DISPLAY_H */
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2013-2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __APPLE_DISPLAY_TIMINGS_H
+#define __APPLE_DISPLAY_TIMINGS_H
+
+//Supported timings by this platform
+static struct display_timing timing_list[] =
+{
+#if DEBUG_BUILD || SUB_TARGET_N41 || SUB_TARGET_N42 || SUB_TARGET_N48 || SUB_TARGET_N49
+	{ 
+	.display_name = 	"n41",	
+	.host_clock_id = 	CLK_VCLK0, 
+	.pixel_clock = 		68400000, 
+	.dot_pitch = 		326, 
+	.h_active =		640,
+	.h_pulse_width = 	40, 
+	.h_back_porch = 	40, 
+	.h_front_porch =        40, 
+	.v_active = 		1136,
+	.v_pulse_width =  	3, 
+	.v_back_porch = 	13, 
+	.v_front_porch =        348, 
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	24, 
+	.display_type = 	DISPLAY_TYPE_PINOT, 
+	.display_config		= NULL,
+	},	// mipi_dsi_clk @ 513MHz, 4-lane
+#endif
+};
+#endif	/* ! __APPLE_DISPLAY_TIMINGS_H */
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2010-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWCLOCKS_H
+#define __PLATFORM_SOC_HWCLOCKS_H
+
+#include <platform/clocks.h>
+
+#if SUPPORT_FPGA
+#define OSC_FREQ			(10000000UL)
+#else
+#define OSC_FREQ			(24000000UL)
+#endif
+
+#define CLK_FCLK	(HWCLOCK_BASE+0)
+#define CLK_ACLK	(HWCLOCK_BASE+1)
+#define CLK_HCLK	(HWCLOCK_BASE+2)
+#define CLK_PCLK	(HWCLOCK_BASE+3)
+#define CLK_VCLK0	(HWCLOCK_BASE+4)
+#define CLK_VCLK1	(HWCLOCK_BASE+5)
+#define CLK_MCLK	(HWCLOCK_BASE+6)
+#define CLK_NCLK	(HWCLOCK_BASE+7)
+#define CLK_USBPHYCLK	(HWCLOCK_BASE+8)
+#define CLK_NCOREF	(HWCLOCK_BASE+9)
+#define CLK_FMI		(HWCLOCK_BASE+10)
+
+/* S5L8950X clock gate devices */
+enum {
+	CLK_rsvd0 = 0,
+	CLK_SCC,
+	CLK_CPU0,
+	CLK_CPU1,
+	CLK_L2_BIU,
+	CLK_L2,
+	CLK_rsvd1,
+	CLK_rsvd2,
+	CLK_MCU,
+	CLK_GFX_SYS,
+	CLK_GFX_CORES,
+	CLK_HPERFNRT,
+	CLK_VDEC,
+	CLK_SCALER0,
+	CLK_SCALER1,
+	CLK_JPG0,
+	CLK_JPG1,
+	CLK_rsvd3,
+	CLK_VENC,
+	CLK_HPERFRT,
+	CLK_ISP,
+	CLK_LPDP,
+	CLK_DISP0,
+	CLK_DISP1,
+	CLK_DISPOUT,
+	CLK_MIPI,
+	CLK_CLCD,
+	CLK_TVDAC,
+	CLK_RGBOUT,
+	CLK_DPLINK,
+	CLK_CDIO,
+	CLK_CDMA,
+	CLK_IOP,
+	CLK_UPERF,
+	CLK_USBOTG,
+	CLK_USB20,
+	CLK_USB11,
+	CLK_USBOHCI0,
+	CLK_USBOHCI1,
+	CLK_USBPHY,
+	CLK_AUDIO,
+	CLK_I2S0,
+	CLK_I2S1,
+	CLK_I2S2,
+	CLK_I2S3,
+	CLK_SPDIF,
+	CLK_ADSP,
+	CLK_SDIO,
+	CLK_SHA1,
+	CLK_SHA2,
+	CLK_FMI0,
+	CLK_FMI0BCH,
+	CLK_FMI1,
+	CLK_FMI1BCH,
+	CLK_FMI_DLL,
+	CLK_XMBIST,
+	CLK_MCA,
+	CLK_SPI0,
+	CLK_SPI1,
+	CLK_SPI2,
+	CLK_SPI3,
+	CLK_SPI4,
+	CLK_UART0,
+	CLK_UART1,
+	CLK_UART2,
+	CLK_UART3,
+	CLK_UART4,
+	CLK_UART5,
+	CLK_UART6,
+	CLK_PKE,
+	CLK_I2C0,
+	CLK_I2C1,
+	CLK_I2C2,
+	CLK_PWM,
+	CLK_SCRT,
+	CLK_GPIO,
+	CLK_SWI,
+	CLK_DWI,
+	CLK_DEBUG,
+	CLK_AIC,
+};
+
+#endif /* ! __PLATFORM_SOC_HWCLOCKS_H */
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2010-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWDMACHANNELS_H
+#define __PLATFORM_SOC_HWDMACHANNELS_H
+
+#define DMA_MEMORY_TX		(1)
+#define DMA_MEMORY_RX		(2)
+#define DMA_SDIO		(3)
+#define DMA_FMI0DATA		(5)
+#define DMA_FMI0CHECK		(6)
+#define DMA_FMI1DATA		(7)
+#define DMA_FMI1CHECK		(8)
+
+#define DMA_CHANNEL_COUNT	(44)
+
+#define DMA_CHANNEL_CONFIG						\
+{									\
+	/*	low	high	AES OK	reqID	FIFO address */		\
+	{	3,	4,	false,	0x00,	0x30000020	},	\
+	{	3,	4,	false,	0x01,	0x301000A0	},	\
+	{	3,	4,	false,	0x01,	0x30200020	},	\
+	{	5,	8,	true,	0x00,	0x31200014	},	\
+	{	5,	8,	true,	0x01,	0x31200018	},	\
+ 	{	5,	8,	true,	0x02,	0x31300014	},	\
+	{	5,	8,	true,	0x03,	0x31300018	},	\
+}
+
+
+#define DMA_SDIO_TIMEOUT_US (10 * 1000)
+
+
+#endif /* ! __PLATFORM_SOC_HWDMACHANNELS_H */
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWISR_H
+#define __PLATFORM_SOC_HWISR_H
+
+#define INT_SW0			0	// Software 0 Interrupt
+#define INT_SW1			1	// Software 1 Interrupt
+#define INT_SW2			2	// Software 2 Interrupt
+#define INT_SW3			3	// Software 3 Interrupt
+#define INT_WDT			4	// Watchdog Timer Interrupt
+#define INT_SWI			5	// SWI Interrupt
+#define INT_DWI			6	// DWI Interrupt
+#define INT_ISP0		7	// ISP 0 Interrupt
+#define INT_ISP1       		8	// ISP 1 Interrupt
+#define INT_SCALER0		9	// Scaler Interrupt
+#define INT_SCALER1		10	// Scaler Interrupt
+#define INT_USB_OTG		11	// USB OTG Interrupt
+#define INT_USB_EHCI		12	// USB EHCI Interrupt
+#define INT_USB_OHCI0		13	// USB OHCI 0 Interrupt
+#define INT_USB_OHCI1		14	// USB OHCI 1 Interrupt
+#define INT_USB_RES		15	// USB PHY Interrupt
+#define INT_PWM			16	// PWM Interrupt
+#define INT_PKE			17	// PKE Interrupt
+#define INT_IIC0		18	// I2C 0 Interrupt
+#define INT_IIC1		19	// I2C 1 Interrupt
+#define INT_IIC2		20	// I2C 2 Interrupt
+#define INT_UART0		21	// UART 0 Interrupt
+#define INT_UART1		22	// UART 1 Interrupt
+#define INT_UART2		23	// UART 2 Interrupt
+#define INT_UART3		24	// UART 3 Interrupt
+#define INT_UART4 		25	// UART 4 Interrupt
+#define INT_UART5 		26	// UART 5 Interrupt
+#define INT_UART6 		27	// UART 6 Interrupt
+#define INT_SPI0 		28	// SPI 0 Interrupt
+#define INT_SPI1		29	// SPI 1 Interrupt
+#define INT_SPI2		30	// SPI 2 Interrupt
+#define INT_SPI3		31	// SPI 3 Interrupt
+#define INT_SPI4		32	// SPI 4 Interrupt
+#define INT_FMI0		33	// FMI 0 Interrupt
+#define INT_FMI1		34	// FMI 1 Interrupt
+
+// Reserved 35 - 36
+
+#define INT_SHA1		37	// SHA-1 Interrupt
+#define INT_SHA2		38	// SHA-1 Interrupt
+#define INT_WIFI		39	// WiFi Interrupt
+#define INT_TVOUT		40	// TV Out Interrupt
+
+// Reserved 41
+
+#define INT_CLCD		42	// CLCD Interrupt
+#define INT_DISP0		43	// Display Pipe 0 Interrupt	
+#define INT_DISP1		44	// Display Pipe 1 Interrupt
+#define INT_RGBOUT		45	// RGB Out Interrupt
+#define INT_DPORT0		46	// DisplayPort 0 Interrupt
+#define INT_DPORT1		47	// DisplayPort 1 Interrupt
+#define INT_VENC		48	// Video Encoder Interrupt
+#define INT_SGX			49	// SGX Interrupt
+#define INT_VDEC		50	// Video Decoder Interrupt
+#define INT_CDMA_DMAC1		51	// CDMA DMA Channel 1 Interrupt
+#define INT_CDMA_DMAC2		52	// CDMA DMA Channel 2 Interrupt
+#define INT_CDMA_DMAC3		53	// CDMA DMA Channel 3 Interrupt
+#define INT_CDMA_DMAC4		54	// CDMA DMA Channel 4 Interrupt
+#define INT_CDMA_DMAC5		55	// CDMA DMA Channel 5 Interrupt
+#define INT_CDMA_DMAC6		56	// CDMA DMA Channel 6 Interrupt
+#define INT_CDMA_DMAC7		57	// CDMA DMA Channel 7 Interrupt
+#define INT_CDMA_DMAC8		58	// CDMA DMA Channel 8 Interrupt
+#define INT_CDMA_DMAC9		59	// CDMA DMA Channel 9 Interrupt
+#define INT_CDMA_DMAC10		60	// CDMA DMA Channel 10 Interrupt
+#define INT_CDMA_DMAC11		61	// CDMA DMA Channel 11 Interrupt
+#define INT_CDMA_DMAC12		62	// CDMA DMA Channel 12 Interrupt
+#define INT_CDMA_DMAC13		63	// CDMA DMA Channel 13 Interrupt
+#define INT_CDMA_DMAC14		64	// CDMA DMA Channel 14 Interrupt
+#define INT_CDMA_DMAC15		65	// CDMA DMA Channel 15 Interrupt
+#define INT_CDMA_DMAC16		66	// CDMA DMA Channel 16 Interrupt
+#define INT_CDMA_DMAC17		67	// CDMA DMA Channel 17 Interrupt
+#define INT_CDMA_DMAC18		68	// CDMA DMA Channel 18 Interrupt
+#define INT_CDMA_DMAC19		69	// CDMA DMA Channel 19 Interrupt
+#define INT_CDMA_DMAC20		70	// CDMA DMA Channel 20 Interrupt
+#define INT_CDMA_DMAC21		71	// CDMA DMA Channel 21 Interrupt
+#define INT_CDMA_DMAC22		72	// CDMA DMA Channel 22 Interrupt
+#define INT_CDMA_DMAC23		73	// CDMA DMA Channel 23 Interrupt
+#define INT_CDMA_DMAC24		74	// CDMA DMA Channel 24 Interrupt
+#define INT_CDMA_DMAC25		75	// CDMA DMA Channel 25 Interrupt
+#define INT_CDMA_DMAC26		76	// CDMA DMA Channel 26 Interrupt
+#define INT_CDMA_DMAC27		77	// CDMA DMA Channel 27 Interrupt
+#define INT_CDMA_DMAC28		78	// CDMA DMA Channel 28 Interrupt
+#define INT_CDMA_DMAC29		79	// CDMA DMA Channel 29 Interrupt
+#define INT_CDMA_DMAC30		80	// CDMA DMA Channel 30 Interrupt
+#define INT_CDMA_DMAC31		81	// CDMA DMA Channel 31 Interrupt
+#define INT_CDMA_DMAC32		82	// CDMA DMA Channel 32 Interrupt
+#define INT_CDMA_DMAC33		83	// CDMA DMA Channel 33 Interrupt
+#define INT_CDMA_DMAC34		84	// CDMA DMA Channel 34 Interrupt
+#define INT_CDMA_DMAC35		85	// CDMA DMA Channel 35 Interrupt
+#define INT_CDMA_DMAC36		86	// CDMA DMA Channel 36 Interrupt
+#define INT_CDMA_DMAC37		87	// CDMA DMA Channel 37 Interrupt
+#define INT_CDMA_DMAC38		88	// CDMA DMA Channel 38 Interrupt
+#define INT_CDMA_DMAC39		89	// CDMA DMA Channel 39 Interrupt
+#define INT_CDMA_DMAC40		90	// CDMA DMA Channel 40 Interrupt
+#define INT_CDMA_DMAC41		91	// CDMA DMA Channel 41 Interrupt
+#define INT_CDMA_DMAC42		92	// CDMA DMA Channel 42 Interrupt
+#define INT_CDMA_DMAC43		93	// CDMA DMA Channel 43 Interrupt
+
+// Reserved 94 - 96
+
+// Audio and Highland Park Interrupts 97 - 115
+
+#define INT_AUDIO_CPU_IRQ0	97	// 
+#define INT_AUDIO_CPU_IRQ1	98	// 
+
+#define INT_ADSP_F0		112	// DSP
+#define INT_ADSP_F1		113	// DSP
+#define INT_ADSP_T0		114	// DSP
+#define INT_ADSP_T1		115	// DSP
+
+#define INT_HPERFNRT_DART	116	// HPerf-NRT DART Interrupt
+#define INT_HPERFRT_DART	117	// HPerf-RT DART Interrupt
+#define INT_JPEG0		118	// JPEG 0 Interrupt
+#define INT_GPIO0		119	// GPIO 0 Interrupt
+#define INT_GPIO1		120	// GPIO 1 Interrupt
+#define INT_MCU			121	// MCU Interrupt
+#define INT_MCU0		122	// MCU Phy 0 Interrupt
+#define INT_MCU1		123	// MCU Phy 1 Interrupt
+#define INT_PIO0		124	// PIO 0 Interrupt
+#define INT_PIO1		125	// PIO 1 Interrupt
+#define INT_JPEG1		126	// JPEG 1 Interrupt
+#define INT_IOP_COMMRX		127	// IOP CommRx Interrupt
+#define INT_IOP_COMMTX		128	// IOP CommTx Interrupt
+#define INT_IOP_PMI		129	// IOP PerfMon Interrupt
+#define INT_IOP_CTIIRQ		130	// IOP CTIIRQ Interrupt
+#define INT_ISP_COMMRX		131	// IOP CommRx Interrupt
+#define INT_ISP_COMMTX		132	// IOP CommTx Interrupt
+#define INT_ISP_PMI		133	// IOP PerfMon Interrupt
+#define INT_ISP_CTIIRQ		134	// IOP CTIIRQ Interrupt
+
+// Reserved 135 - 136
+
+#define INT_CPU0_COMMRX		137	// IOP CommRx Interrupt
+#define INT_CPU0_COMMTX		138	// IOP CommTx Interrupt
+
+// Reserved 139 - 140
+
+#define INT_CPU1_COMMRX		141	// IOP CommRx Interrupt
+#define INT_CPU1_COMMTX		142	// IOP CommTx Interrupt
+
+// Reserved 143
+
+#define INT_LPDP		144	// Low Power Display Port Interrupt
+
+// Reserved 145 - 149
+
+#define INT_MCU2		150	// MCU Phy 2 Interrupt
+#define INT_MCU3		151	// MCU Phy 3 Interrupt
+#define INT_PMGR_PMI		152	// PMGR PerfMon Interrupt
+#define INT_HPERFNTR_PMI	153	// HPerf-NRT PerfMon Interrupt
+#define INT_HPERFRT_PMI		154	// HPerf-RT PerfMon Interrupt
+#define INT_DPIPE0_PMI		155	// Display Pipe 0 PerfMon Interrupt
+#define INT_DPIPE1_PMI		156	// Display Pipe 1 PerfMon Interrupt
+
+// Reserved 157 - 159
+
+#define INT_ETB_FULL		160	// ETB Full Interrupt
+
+// Reserved 161
+
+#define INT_CPU0_VTIMER		162	// CPU 0 Virtual Timer Interrupt
+#define INT_CPU0_DEBUG		163	// CPU 0 Debug Interrupt
+
+// Reserved 164
+
+#define INT_CPU1_VTIMER		165	// CPU 1 Virtual Timer Interrupt
+#define INT_CPU1_DEBUG		166	// CPU 1 Debug Interrupt
+
+// Reserved 167
+
+#define INT_MCA			168	// Multi-Channel Audio Interrupt
+#define INT_KEYGEN		169	// CDMA Keygen Interrupt
+#define INT_THERM_ALARM0	170	// Thermal Alarm 0 Interrupt
+#define INT_THERM_ALARM1	171	// Thermal Alarm 1 Interrupt
+#define INT_THERM_TEMP0		172	// Thermal Temp 0 Interrupt
+#define INT_THERM_TEMP1		173	// Thermal Temp 1 Interrupt
+
+// Reserved 174 - 191
+
+#if PLATFORM_VARIANT_IOP
+
+#include <drivers/aic/aic.h>
+
+#define INT_HOST		INT_SW2			// Host processor doorbell
+#define INT_IOP			INT_SW3			// I/O coprocessor doorbell
+#define INT_IOP_NMI		kAIC_VEC_SW_TMR		// I/O coprocessor NMI
+
+#elif PLATFORM_VARIANT_AUDIO
+
+#include <drivers/audio/audio.h>
+
+#define INT_HOST		AE2_INT_SW0		// Host processor doorbell
+#define INT_IOP			AE2_INT_SW0		// I/O coprocessor doorbell
+#define INT_IOP_NMI		AE2_INT_SW1		// I/O coprocessor NMI
+
+#endif
+
+#endif /* ! __PLATFORM_SOC_HWISR_H */
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWREGBASE_H
+#define __PLATFORM_SOC_HWREGBASE_H
+
+#define AIC_VERSION 			0
+#define AIC_INT_COUNT			(192)
+#define PMGR_WDG_VERSION		0
+
+/* S5L8950X Reg Base Defs */
+
+#define SDIO_BASE_ADDR			(0x30000000)
+
+#define SHA1_BASE_ADDR			(0x30100000)
+#define SHA2_BASE_ADDR			(0x30200000)
+
+#define NAND_DLL_BASE_ADDR		(0x31000000)
+#define FMI0_BASE_ADDR			(0x31200000)
+#define FMI1_BASE_ADDR			(0x31300000)
+#define FMI_VERSION			(5)
+
+#define SPI0_BASE_ADDR			(0x32000000)
+#define SPI1_BASE_ADDR			(0x32100000)
+#define SPI2_BASE_ADDR			(0x32200000)
+#define SPI3_BASE_ADDR			(0x32300000)
+#define SPI4_BASE_ADDR			(0x32400000)
+#define SPI_VERSION			(1)
+#define SPIS_COUNT			(5)
+
+#define UART0_BASE_ADDR			(0x32500000)
+#define UART1_BASE_ADDR			(0x32600000)
+#define UART2_BASE_ADDR			(0x32700000)
+#define UART3_BASE_ADDR			(0x32800000)
+#define UART4_BASE_ADDR			(0x32900000)
+#define UART5_BASE_ADDR			(0x32A00000)
+#define UART6_BASE_ADDR			(0x32B00000)
+#define UART_VERSION			(1)
+#define UARTS_COUNT			(7)
+
+#define PKE_BASE_ADDR			(0x33100000)
+
+#define IIC_BASE_ADDR			(0x33200000)
+#define IIC_SPACING			(0x00100000)
+#define IICS_COUNT			(3)
+
+#define AUDIO_BASE_ADDR			(0x34000000)
+
+#define USBPHY_BASE_ADDR		(0x36000000)
+#define USBPHY_VERSION			(4)
+#define USBOTG_BASE_ADDR		(0x36100000)
+#define UPERF_WIDGETS_BASE_ADDR		(0x36E00000)
+#define UPERF_PL301_BASE_ADDR		(0x36F00000)
+
+#define CDMA_BASE_ADDR			(0x37000000)
+#define CDMA_VERSION			5
+
+#define VENC_BASE_ADDR			(0x38000000)
+
+#define VDEC_BASE_ADDR			(0x38100000)
+
+#define JPEG0_BASE_ADDR			(0x38200000)
+#define JPEG1_BASE_ADDR			(0x38500000)
+
+#define SCALER_BASE_ADDR		(0x38300000)
+#define SCALER_SPACING			(0x00100000)
+
+#define NRT_DART_BASE_ADDR		(0x38B00000)
+
+#define NRT_DART_WIDGETS_BASE_ADDR	(0x38C00000)
+#define NRT_DART_PL301_BASE_ADDR	(0x38D00000)
+
+#define NRT_TOP_WIDGETS_BASE_ADDR	(0x38E00000)
+#define NRT_TOP_PL301_BASE_ADDR		(0x38F00000)
+
+#define CLCD_BASE_ADDR			(0x39200000)
+#define CLCD_VERSION			(1)
+#define DITHER_VERSION			(1)
+
+#define DITHER0_BASE_ADDR		(0x39300000)
+
+#define TVOUT_BASE_ADDR			(0x39400000)
+
+#define DSIM_BASE_ADDR			(0x39500000)
+#define DSIM_LANE_COUNT			(4)
+#define DSIM_VERSION			(1)
+
+#define RGBOUT_BASE_ADDR		(0x39600000)
+
+#define DP_BASE_ADDR			(0x39700000)
+#define DISPLAYPORT_VERSION		(1)
+
+#define DITHER1_BASE_ADDR		(0x39800000)
+
+#define LPDP_BASE_ADDR			(0x39900000)
+
+#define ISP_BASE_ADDR			(0x3A000000)
+
+#define DISP0_BASE_ADDR			(0x3A100000)
+#define DISP1_BASE_ADDR			(0x3A200000)
+#define CLCD_DISPLAYPIPE_BASE_ADDR	(DISP0_BASE_ADDR)
+#define RGBOUT_DISPLAYPIPE_BASE_ADDR	(DISP1_BASE_ADDR)
+#define DISP_VERSION			(3)
+
+#define RT_DART_BASE_ADDR		(0x3A400000)
+
+#define RT_TOP_WIDGETS_BASE_ADDR	(0x3A500000)
+#define RT_TOP_PL301_BASE_ADDR		(0x3A600000)
+
+#define ADSP_BASE_ADDR			(0x3B000000)
+
+#define AMP_BASE_ADDR			(0x3D000000)
+#define AMP_SPACING			(0x00100000)
+
+#define SCC_BASE_ADDR			(0x3D200000)
+
+#define PMGR_BASE_ADDR			(0x3F100000)
+
+#define AIC_BASE_ADDR			(0x3F200000)
+
+#define IOP_BASE_ADDR			(0x3F300000)
+
+#define ROSC_BASE_ADDR			(0x3F400000)
+#define ROSC_MASK			(0x57FF)
+#define ROSC_WITH_CLOCK			(0)
+
+#define CHIPID_BASE_ADDR		(0x3F500000)
+
+#define SWI_BASE_ADDR			(0x3F600000)
+#define DWI_BASE_ADDR			(0x3F700000)
+
+#define AMC_BASE_ADDR			(0x3F800000)
+
+#define GPIO_BASE_ADDR			(0x3FA00000)
+#define GPIO_VERSION			(2)
+#define GPIO_GROUP_COUNT		(29)
+#define GPIO_PAD_SPI			(GPIO_GROUP_COUNT)
+
+#define PIO_BASE_ADDR			(0x3FB00000)
+#define PIO_SPACING			(0x00100000)
+
+#define CIM_BASE_ADDR			(0x3FD00000)
+
+#define CDIO_WIDGETS_BASE_ADDR		(0x3FE00000)
+#define CDIO_PL301_BASE_ADDR		(0x3FF00000)
+
+#endif /* ! __PLATFORM_SOC_HWREGBASE_H */
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2010-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_MIU_H
+#define __PLATFORM_SOC_MIU_H
+
+#include <lib/devicetree.h>
+#include <platform/soc/hwregbase.h>
+
+#define	rREMAP_CTL			(*(volatile u_int32_t *)(PIO_BASE_ADDR + 0x0000))
+
+#define rCIM_TID_DEST_CONFIG(n)		(*(volatile u_int32_t *)(CIM_BASE_ADDR + 0x000 + (n) * 4))
+#define rCIM_CONFIG_REG			(*(volatile u_int32_t *)(CIM_BASE_ADDR + 0x040)
+#define rCIM_STATUS_REG0		(*(volatile u_int32_t *)(CIM_BASE_ADDR + 0x044)
+#define rCIM_STATUS_REG1		(*(volatile u_int32_t *)(CIM_BASE_ADDR + 0x048)
+
+#define  CDIO_IOP_RRLIMIT		(0x0000)
+#define rCDIO_IOP_RRLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_RRLIMIT))
+#define  CDIO_IOP_WRLIMIT		(0x0004)
+#define rCDIO_IOP_WRLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_WRLIMIT))
+#define  CDIO_IOP_RTLIMIT		(0x0008)
+#define rCDIO_IOP_RTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_RTLIMIT))
+#define  CDIO_IOP_WTLIMIT		(0x000C)
+#define rCDIO_IOP_WTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_WTLIMIT))
+#define  CDIO_IOP_WGATHER		(0x0010)
+#define rCDIO_IOP_WGATHER		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_WGATHER))
+#define  CDIO_IOP_C_REMAP_EN		(0x001C)
+#define rCDIO_IOP_C_REMAP_EN		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_C_REMAP_EN))
+#define  CDIO_IOP_RC_REMAP(n)		(0x0020 + ((n) * 4))
+#define rCDIO_IOP_RC_REMAP(n)		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_RC_REMAP(n)))
+#define  CDIO_IOP_WC_REMAP(n)		(0x0030 + ((n) * 4))
+#define rCDIO_IOP_WC_REMAP(n)		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_WC_REMAP(n)))
+#define  CDIO_CDMA_RRLIMIT		(0x1000)
+#define rCDIO_CDMA_RRLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_CDMA_RRLIMIT))
+#define  CDIO_CDMA_WRLIMIT		(0x1004)
+#define rCDIO_CDMA_WRLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_CDMA_WRLIMIT))
+#define  CDIO_CDMA_RTLIMIT		(0x1008)
+#define rCDIO_CDMA_RTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_CDMA_RTLIMIT))
+#define  CDIO_CDMA_WTLIMIT		(0x100C)
+#define rCDIO_CDMA_WTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_CDMA_WTLIMIT))
+#define  CDIO_CDMA_WGATHER		(0x1010)
+#define rCDIO_CDMA_WGATHER		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_CDMA_WGATHER))
+#define  CDIO_UPERF_RRLIMIT		(0x2000)
+#define rCDIO_UPERF_RRLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPERF_RRLIMIT))
+#define  CDIO_UPERF_WRLIMIT		(0x2004)
+#define rCDIO_UPERF_WRLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPERF_WRLIMIT))
+#define  CDIO_UPERF_RTLIMIT		(0x2008)
+#define rCDIO_UPERF_RTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPERF_RTLIMIT))
+#define  CDIO_UPERF_WTLIMIT		(0x200C)
+#define rCDIO_UPERF_WTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPERF_WTLIMIT))
+#define  CDIO_UPERF_WGATHER		(0x2010)
+#define rCDIO_UPERF_WGATHER		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPERF_WGATHER))
+#define  CDIO_AUDIO_RRLIMIT		(0x3000)
+#define rCDIO_AUDIO_RRLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_AUDIO_RRLIMIT))
+#define  CDIO_AUDIO_WRLIMIT		(0x3004)
+#define rCDIO_AUDIO_WRLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_AUDIO_WRLIMIT))
+#define  CDIO_AUDIO_RTLIMIT		(0x3008)
+#define rCDIO_AUDIO_RTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_AUDIO_RTLIMIT))
+#define  CDIO_AUDIO_WTLIMIT		(0x300C)
+#define rCDIO_AUDIO_WTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_AUDIO_WTLIMIT))
+#define  CDIO_AUDIO_WGATHER		(0x3010)
+#define rCDIO_AUDIO_WGATHER		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_AUDIO_WGATHER))
+#define  CDIO_DAP_QOS			(0x4014)
+#define rCDIO_DAP_QOS			(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_DAP_QOS))
+#define  CDIO_DAP_CACHE			(0x4018)
+#define rCDIO_DAP_CACHE			(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_DAP_CACHE))
+#define  CDIO_PIO_RTLIMIT		(0x5008)
+#define rCDIO_PIO_RTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_PIO_RTLIMIT))
+#define  CDIO_PIO_WTLIMIT		(0x500C)
+#define rCDIO_PIO_WTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_PIO_WTLIMIT))
+#define  CDIO_CIM_RTLIMIT		(0x6008)
+#define rCDIO_CIM_RTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_CIM_RTLIMIT))
+#define  CDIO_CIM_WTLIMIT		(0x600C)
+#define rCDIO_CIM_WTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_CIM_WTLIMIT))
+
+#define  CDIO_AR_CHAN_ARB_MI0		(0x0408)
+#define rCDIO_AR_CHAN_ARB_MI0		(*(volatile u_int32_t *)(CDIO_PL301_BASE_ADDR + CDIO_AR_CHAN_ARB_MI0))
+#define  CDIO_AW_CHAN_ARB_MI0		(0x040C)
+#define rCDIO_AW_CHAN_ARB_MI0		(*(volatile u_int32_t *)(CDIO_PL301_BASE_ADDR + CDIO_AW_CHAN_ARB_MI0))
+#define  CDIO_AR_CHAN_ARB_MI1		(0x0428)
+#define rCDIO_AR_CHAN_ARB_MI1		(*(volatile u_int32_t *)(CDIO_PL301_BASE_ADDR + CDIO_AR_CHAN_ARB_MI1))
+#define  CDIO_AW_CHAN_ARB_MI1		(0x042C)
+#define rCDIO_AW_CHAN_ARB_MI1		(*(volatile u_int32_t *)(CDIO_PL301_BASE_ADDR + CDIO_AW_CHAN_ARB_MI1))
+
+#define  UPERF_OTG_QOS			(0x0014)
+#define rUPERF_OTG_QOS			(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OTG_QOS))
+#define  UPERF_OTG_CACHE		(0x0018)
+#define rUPERF_OTG_CACHE		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OTG_CACHE))
+#define  UPERF_EHCI_QOS			(0x0034)
+#define rUPERF_EHCI_QOS			(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_EHCI_QOS))
+#define  UPERF_EHCI_CACHE		(0x0038)
+#define rUPERF_EHCI_CACHE		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_EHCI_CACHE))
+#define  UPERF_OHCI0_QOS		(0x0054)
+#define rUPERF_OHCI0_QOS		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OHCI0_QOS))
+#define  UPERF_OHCI0_CACHE		(0x0058)
+#define rUPERF_OHCI0_CACHE		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OHCI0_CACHE))
+#define  UPERF_OHCI1_QOS		(0x0074)
+#define rUPERF_OHCI1_QOS		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OHCI1_QOS))
+#define  UPERF_OHCI1_CACHE		(0x0078)
+#define rUPERF_OHCI1_CACHE		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OHCI1_CACHE))
+#define  UPERF_RTLIMIT			(0x0088)
+#define rUPERF_RTLIMIT			(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_RTLIMIT))
+#define  UPERF_WTLIMIT			(0x008C)
+#define rUPERF_WTLIMIT			(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_WTLIMIT))
+
+#define  UPERF_AR_CHAN_ARB_MI		(0x0408)
+#define rUPERF_AR_CHAN_ARB_MI		(*(volatile u_int32_t *)(UPERF_PL301_BASE_ADDR + UPERF_AR_CHAN_ARB_MI0))
+#define  UPERF_AW_CHAN_ARB_MI		(0x040C)
+#define rUPERF_AW_CHAN_ARB_MI		(*(volatile u_int32_t *)(UPERF_PL301_BASE_ADDR + UPERF_AW_CHAN_ARB_MI0))
+
+#define  HPERF_NRT_DART_DART_RTLIMIT	(0x0000)
+#define rHPERF_NRT_DART_DART_RTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_DART_RTLIMIT))
+#define  HPERF_NRT_DART_DART_WTLIMIT	(0x0004)
+#define rHPERF_NRT_DART_DART_WTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_DART_WTLIMIT))
+#define  HPERF_NRT_DART_DART_WGATHER	(0x0010)
+#define rHPERF_NRT_DART_DART_WGATHER	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_DART_WGATHER))
+#define  HPERF_NRT_DART_SCALER0_RTLIMIT	(0x0108)
+#define rHPERF_NRT_DART_SCALER0_RTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_SCALER0_RTLIMIT))
+#define  HPERF_NRT_DART_SCALER0_WTLIMIT	(0x010C)
+#define rHPERF_NRT_DART_SCALER0_WTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_SCALER0_WTLIMIT))
+#define  HPERF_NRT_DART_SCALER1_RTLIMIT	(0x0208)
+#define rHPERF_NRT_DART_SCALER1_RTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_SCALER1_RTLIMIT))
+#define  HPERF_NRT_DART_SCALER1_WTLIMIT	(0x020C)
+#define rHPERF_NRT_DART_SCALER1_WTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_SCALER1_WTLIMIT))
+#define  HPERF_NRT_DART_JPEG0_RTLIMIT	(0x0308)
+#define rHPERF_NRT_DART_JPEG0_RTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_JPEG0_RTLIMIT))
+#define  HPERF_NRT_DART_JPEG0_WTLIMIT	(0x030C)
+#define rHPERF_NRT_DART_JPEG0_WTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_JPEG0_WTLIMIT))
+#define  HPERF_NRT_DART_JPEG0_QOS	(0x0314)
+#define rHPERF_NRT_DART_JPEG0_QOS	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_JPEG0_QOS))
+#define  HPERF_NRT_DART_JPEG1_RTLIMIT	(0x0408)
+#define rHPERF_NRT_DART_JPEG1_RTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_JPEG0_RTLIMIT))
+#define  HPERF_NRT_DART_JPEG1_WTLIMIT	(0x040C)
+#define rHPERF_NRT_DART_JPEG1_WTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_JPEG0_WTLIMIT))
+#define  HPERF_NRT_DART_JPEG1_QOS	(0x0414)
+#define rHPERF_NRT_DART_JPEG1_QOS	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_JPEG0_QOS))
+
+#define  HPERF_NRT_DART_AR_CHAN_ARB_MI	(0x0408)
+#define rHPERF_NRT_DART_AR_CHAN_ARB_MI	(*(volatile u_int32_t *)(NRT_DART_PL301_BASE_ADDR + HPERF_NRT_DART_AR_CHAN_ARB_MI0))
+#define  HPERF_NRT_DART_AW_CHAN_ARB_MI	(0x040C)
+#define rHPERF_NRT_DART_AW_CHAN_ARB_MI	(*(volatile u_int32_t *)(NRT_DART_PL301_BASE_ADDR + HPERF_NRT_DART_AW_CHAN_ARB_MI0))
+
+#define  HPERF_NRT_TOP_TOP_RTLIMIT	(0x0008)
+#define rHPERF_NRT_TOP_TOP_RTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_TOP_RTLIMIT))
+#define  HPERF_NRT_TOP_TOP_WTLIMIT	(0x000C)
+#define rHPERF_NRT_TOP_TOP_WTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_TOP_WTLIMIT))
+#define  HPERF_NRT_TOP_VENC_RTLIMIT	(0x0108)
+#define rHPERF_NRT_TOP_VENC_RTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VENC_RTLIMIT))
+#define  HPERF_NRT_TOP_VENC_WTLIMIT	(0x010C)
+#define rHPERF_NRT_TOP_VENC_WTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VENC_WTLIMIT))
+#define  HPERF_NRT_TOP_VENC_WREQSP	(0x0110)
+#define rHPERF_NRT_TOP_VENC_WREQSP	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VENC_WREQSP))
+#define  HPERF_NRT_TOP_VDEC_RTLIMIT	(0x0208)
+#define rHPERF_NRT_TOP_VDEC_RTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VDEC_RTLIMIT))
+#define  HPERF_NRT_TOP_VDEC_WTLIMIT	(0x020C)
+#define rHPERF_NRT_TOP_VDEC_WTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VDEC_WTLIMIT))
+#define  HPERF_NRT_TOP_VDEC_WREQSP	(0x0210)
+#define rHPERF_NRT_TOP_VDEC_WREQSP	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VDEC_WREQSP))
+#define  HPERF_NRT_TOP_AUX_RTLIMIT	(0x0308)
+#define rHPERF_NRT_TOP_AUX_RTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VDEC_RTLIMIT))
+#define  HPERF_NRT_TOP_AUX_WTLIMIT	(0x030C)
+#define rHPERF_NRT_TOP_AUX_WTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VDEC_WTLIMIT))
+#define  HPERF_NRT_TOP_AUX_WGATHER	(0x0310)
+#define rHPERF_NRT_TOP_AUX_WGATHER	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_AUX_WGATHER))
+
+#define  HPERF_NRT_TOP_AR_CHAN_ARB_MI	(0x0408)
+#define rHPERF_NRT_TOP_AR_CHAN_ARB_MI	(*(volatile u_int32_t *)(NRT_TOP_PL301_BASE_ADDR + HPERF_NRT_TOP_AR_CHAN_ARB_MI0))
+#define  HPERF_NRT_TOP_AW_CHAN_ARB_MI	(0x040C)
+#define rHPERF_NRT_TOP_AW_CHAN_ARB_MI	(*(volatile u_int32_t *)(NRT_TOP_PL301_BASE_ADDR + HPERF_NRT_TOP_AW_CHAN_ARB_MI0))
+
+#define  HPERF_RT_TOP_DISP0_RTLIMIT	(0x0004)
+#define rHPERF_RT_TOP_DISP0_RTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_DISP0_RTLIMIT))
+#define  HPERF_RT_TOP_DISP1_RTLIMIT	(0x000C)
+#define rHPERF_RT_TOP_DISP1_RTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_DISP1_RTLIMIT))
+#define  HPERF_RT_TOP_ISP_RTLIMIT	(0x0018)
+#define rHPERF_RT_TOP_ISP_RTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_ISP_WTLIMIT))
+#define  HPERF_RT_TOP_ISP_WTLIMIT	(0x001C)
+#define rHPERF_RT_TOP_ISP_WTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_ISP_RTLIMIT))
+#define  HPERF_RT_TOP_TOP_RTLIMIT	(0x0020)
+#define rHPERF_RT_TOP_TOP_RTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_TOP_WTLIMIT))
+#define  HPERF_RT_TOP_TOP_WTLIMIT	(0x0024)
+#define rHPERF_RT_TOP_TOP_WTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_TOP_RTLIMIT))
+
+#define  HPERF_RT_TOP_AR_CHAN_ARB_MI	(0x0408)
+#define rHPERF_RT_TOP_AR_CHAN_ARB_MI	(*(volatile u_int32_t *)(RT_TOP_PL301_BASE_ADDR + HPERF_RT_TOP_AR_CHAN_ARB_MI0))
+#define  HPERF_RT_TOP_AW_CHAN_ARB_MI	(0x040C)
+#define rHPERF_RT_TOP_AW_CHAN_ARB_MI	(*(volatile u_int32_t *)(RT_TOP_PL301_BASE_ADDR + HPERF_RT_TOP_AW_CHAN_ARB_MI0))
+
+#define	rSCC_CCXPWRCTRL			(*(volatile u_int32_t *)(SCC_BASE_ADDR + 0x2603C))
+
+
+enum remap_select {
+  REMAP_SRAM = 0,
+  REMAP_SDRAM
+};
+
+extern void miu_select_remap(enum remap_select sel);
+extern void miu_bypass_prep(int step);
+extern void miu_update_device_tree(DTNode *pmgr_node);
+
+extern u_int32_t miu_read_l2cadrmap(void);
+extern void miu_write_l2cadrmap(u_int32_t value);
+
+#endif /* ! __PLATFORM_SOC_MIU_H */
@@ -0,0 +1,538 @@
+/*
+ * Copyright (C) 2010-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_PMGR_H
+#define __PLATFORM_SOC_PMGR_H
+
+#include <lib/devicetree.h>
+#include <platform/soc/hwregbase.h>
+
+#define PMGR_PLL_COUNT			(9)
+
+#define	rPMGR_PLL_CTL0(_n)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0000 + ((_n) * 0x18)))
+#define	 PMGR_PLL_ENABLE		(1 << 31)
+#define	 PMGR_PLL_EXT_BYPASS		(1 << 30)
+#define	 PMGR_PLL_REAL_LOCK		(1 << 29)
+#define	 PMGR_PLL_LOAD			(1 << 27)
+#define	 PMGR_PLL_BYPASS		(1 << 23)
+
+#define	rPMGR_PLL_CTL1(_n)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0004 + ((_n) * 0x18)))
+#define  PMGR_PLL_MASK			(0x1FF)
+#define  PMGR_PLL_M_SHIFT		(18)
+#define  PMGR_PLL_P_SHIFT		(9)
+#define  PMGR_PLL_S_SHIFT		(0)
+#define	 PMGR_PLL_P(_p)			(((_p) & PMGR_PLL_MASK) << PMGR_PLL_P_SHIFT)
+#define	 PMGR_PLL_M(_m)			(((_m) & PMGR_PLL_MASK) << PMGR_PLL_M_SHIFT)
+#define	 PMGR_PLL_S(_s)			(((_s) & PMGR_PLL_MASK) << PMGR_PLL_S_SHIFT)
+
+#define	rPMGR_PLL_PARAM(_n)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0008 + ((_n) * 0x18)))
+#define  PMGR_PARAM_LOCK_TIME_MASK	(0xFFFF)
+#define  PMGR_PARAM_LOCK_TIME(_n)	(((_n) & PMGR_PARAM_LOCK_TIME_MASK) << 0)
+
+#define	rPMGR_PLL_FD(_n)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x000C + ((_n) * 0x18)))
+
+#define	rPMGR_DOUBLER_CTL		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0100))
+#define	 PMGR_DOUBLER_ENABLE		(1 << 31)
+#define	 PMGR_DOUBLER_EXT_BYPASS	(1 << 30)
+
+#define	rPMGR_CPU_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0140))
+#define	rPMGR_PLL2_GATE_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0150))
+#define	rPMGR_PLL4_GATE_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0154))
+#define	rPMGR_PLL5_GATE_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0158))
+
+#define	rPMGR_MCU_FIXED_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0164))
+#define	rPMGR_MCU_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0168))
+#define	rPMGR_PCLK1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x016C))
+#define	rPMGR_GFX_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0170))
+#define	rPMGR_GFX_SLC_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0174))
+
+#define	rPMGR_PREDIV0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0190))
+#define	rPMGR_PREDIV1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0194))
+#define	rPMGR_PREDIV2_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0198))
+#define	rPMGR_PREDIV3_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x019C))
+#define	rPMGR_PREDIV4_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01A0))
+#define	rPMGR_PREDIV5_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01A4))
+#define	rPMGR_PREDIV6_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01A8))
+
+#define	rPMGR_VENC_MTX_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01D0))
+#define	rPMGR_VENC_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01D4))
+#define	rPMGR_HPERFRT_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01D8))
+#define	rPMGR_GFX_SYS_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01DC))
+#define	rPMGR_HPERFNRT_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01E0))
+#define	rPMGR_NRT_MEM_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01E4))
+#define	rPMGR_VDEC_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01E8))
+#define	rPMGR_ISP_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01EC))
+#define	rPMGR_IOP_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01F0))
+#define	rPMGR_CDIO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01F4))
+#define	rPMGR_LPERFS_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01F8))
+#define	rPMGR_PCLK0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01FC))
+#define	rPMGR_PCLK2_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0200))
+#define	rPMGR_PCLK3_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0204))
+#define	rPMGR_AES_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0208))
+
+#define	rPMGR_MEDIUM0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0230))
+#define	rPMGR_MEDIUM1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0234))
+#define	rPMGR_VID0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0238))
+#define	rPMGR_VID1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x023C))
+#define	rPMGR_DISPOUT_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0240))
+#define	rPMGR_I2C_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0244))
+#define	rPMGR_SDIO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0248))
+#define	rPMGR_MIPI_DSI_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x024C))
+#define	rPMGR_AUDIO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0250))
+#define	rPMGR_ADSP_PCLK0_CLK_CFG	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0254))
+#define	rPMGR_ADSP_TCLK_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0258))
+#define	rPMGR_ADSP_TSCLK_CLK_CFG	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x025C))
+#define	rPMGR_UPERF_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0260))
+#define	rPMGR_DEBUG_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0264))
+
+#define	rPMGR_SCC_PWR_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0268))
+#define	rPMGR_SCC_DMA_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x026C))
+
+#define	rPMGR_SPI0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0270))
+#define	rPMGR_SPI1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0274))
+#define	rPMGR_SPI2_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0278))
+#define	rPMGR_SPI3_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x027C))
+#define	rPMGR_SPI4_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0280))
+#define	rPMGR_SLOW_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0284))
+#define	rPMGR_SLEEP_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0288))
+
+#define	rPMGR_USBPHY_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x028C))
+#define	rPMGR_USBOHCI_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0290))
+#define	rPMGR_USB12_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0294))
+
+#define	rPMGR_NCO_REF0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0298))
+#define	rPMGR_NCO_REF1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x029C))
+
+#define	rPMGR_USBPHY1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02A4))
+#define	rPMGR_USBFREE_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02A8))
+
+#define	PMGR_FIRST_CLK_CFG		(&rPMGR_CPU_CLK_CFG)
+#define	PMGR_LAST_CLK_CFG		(&rPMGR_USBFREE_CLK_CFG)
+#define	PMGR_CLK_CFG_COUNT		(((((u_int32_t)(PMGR_LAST_CLK_CFG)) - ((u_int32_t)(PMGR_FIRST_CLK_CFG))) / 4) + 1)
+#define	PMGR_CLK_NUM(_r)		(((u_int32_t)&(rPMGR_ ## _r ## _CLK_CFG) - ((u_int32_t)(PMGR_FIRST_CLK_CFG))) / 4)
+#define	PMGR_FIRST_MANAGED_CLK_NUM	PMGR_CLK_NUM(VENC_MTX)
+
+#define	 PMGR_CLK_CFG_ENABLE		(1 << 31)
+#define	 PMGR_CLK_CFG_PENDING		(1 << 30)
+#define	 PMGR_CLK_CFG_AUTO_DISABLE	(1 << 25)
+#define	 PMGR_CLK_CFG_DIVIDER(_d)	(((_d) & 0x1F) << 0)
+#define	 PMGR_CLK_CFG_DIV_MASK		PMGR_CLK_CFG_DIVIDER(0x1F)
+
+#define rPMGR_MIPI_AGILE_CLK_MUX_CFG	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02A0))
+
+#define	rPMGR_I2S0_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02B0))
+#define	rPMGR_I2S0_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02B4))
+#define	rPMGR_I2S0_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02B8))
+
+#define	rPMGR_I2S1_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02C0))
+#define	rPMGR_I2S1_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02C4))
+#define	rPMGR_I2S1_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02C8))
+
+#define	rPMGR_I2S2_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02D0))
+#define	rPMGR_I2S2_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02D4))
+#define	rPMGR_I2S2_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02D8))
+
+#define	rPMGR_I2S3_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02E0))
+#define	rPMGR_I2S3_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02E4))
+#define	rPMGR_I2S3_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02E8))
+
+#define	rPMGR_SPDIF_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02F0))
+#define	rPMGR_SPDIF_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02F4))
+#define	rPMGR_SPDIF_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x02F8))
+
+#define	rPMGR_DP_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0300))
+#define	rPMGR_DP_NCO_N1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0304))
+#define	rPMGR_DP_NCO_N2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0308))
+
+#define	rPMGR_MCA_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0310))
+#define	rPMGR_MCA_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0314))
+#define	rPMGR_MCA_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0318))
+
+#define rPMGR_ENABLE_CLK_GATE		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0330))
+
+#define	kPERF_STATE_BYPASS		(0)
+#define	kPERF_STATE_SECUREROM		(1)
+#define	kPERF_STATE_IBOOT		(2)
+#define	kPERF_STATE_IBOOT_CNT		(5)
+
+#define	PMGR_PERF_STATE_COUNT		(16)
+#define	rPMGR_PERF_STATE_A(_s)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0400 + ((_s) * 0x20)))
+#define	rPMGR_PERF_STATE_B(_s)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0404 + ((_s) * 0x20)))
+#define	rPMGR_PERF_STATE_C(_s)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0408 + ((_s) * 0x20)))
+#define	rPMGR_PERF_STATE_D(_s)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x040C + ((_s) * 0x20)))
+#define	rPMGR_PERF_STATE_E(_s)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0410 + ((_s) * 0x20)))
+#define  PMGR_PERF_STATE_E_VOL_SHIFT	(0)
+#define  PMGR_PERF_STATE_E_VOL_MASK	(0xFF)
+
+#define	rPMGR_PERF_STATE_CTL		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0600))
+#define	 PMGR_PERF_STATE_SEL_SHIFT	(0)
+#define	 PMGR_PERF_STATE_SEL_MASK	(0xF)
+#define	 PMGR_PERF_STATE_SEL(_s)	(((_s) & PMGR_PERF_STATE_SEL_MASK) << PMGR_PERF_STATE_SEL_SHIFT)
+#define	 PMGR_PERF_STATE_PENDING	(0xFFFFFFF << 4)
+
+#define	rPMGR_PERF_STATE_DELAY		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0604))
+#define  PMGR_PERF_STATE_DELAY_VOL_CHG_FIX_DLY_SHIFT (8)
+#define  PMGR_PERF_STATE_DELAY_VOL_CHG_VAR_DLY_SHIFT (0)
+
+#define	rPMGR_MCU_CLK_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0620))
+
+#define	rPMGR_AUTOMATIC_CLK_GATE	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0640))
+#define  PMGR_ACG_CLK_GEN__ENABLE	(1 << 0)
+#define  PMGR_ACG_PS_ENABLE		(1 << 1)
+#define  PMGR_ACG_NCO_CLK_GEN_ENABLE	(1 << 2)
+
+#define rPMGR_FIRST_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1000))
+#define	rPMGR_SCC_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1004))
+#define	rPMGR_CPU0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1008))
+#define	rPMGR_CPU1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x100C))
+#define	rPMGR_L2_BIU_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1010))
+#define	rPMGR_L2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1014))
+#define	rPMGR_MCU_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1020))
+#define	rPMGR_GFX_SYS_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1024))
+#define	rPMGR_GFX_CORES_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1028))
+#define	rPMGR_HPERFNRT_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x102C))
+#define	rPMGR_VDEC_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1030))
+#define	rPMGR_SCALER0_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1034))
+#define	rPMGR_SCALER1_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1038))
+#define	rPMGR_JPG0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x103C))
+#define	rPMGR_JPG1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1040))
+#define	rPMGR_VENCD_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1048))
+#define	rPMGR_HPERFRT_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x104C))
+#define	rPMGR_ISP_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1050))
+#define	rPMGR_LPDP_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1054))
+#define	rPMGR_DISP0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1058))
+#define	rPMGR_DISP1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x105C))
+#define	rPMGR_DISPOUT_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1060))
+#define	rPMGR_MIPI_DSI_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1064))
+#define	rPMGR_CLCD_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1068))
+#define	rPMGR_TVOUT_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x106C))
+#define	rPMGR_RGBOUT_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1070))
+#define	rPMGR_DPLINK_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1074))
+#define	rPMGR_CDIO_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1078))
+#define	rPMGR_CDMA_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x107C))
+#define	rPMGR_IOP_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1080))
+#define	rPMGR_UPERF_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1084))
+#define	rPMGR_USBOTG0_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1088))
+#define	rPMGR_USB20_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x108C))
+#define	rPMGR_USB11_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1090))
+#define	rPMGR_USBOHCI0_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1094))
+#define	rPMGR_USBOHCI1_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1098))
+#define	rPMGR_USBREG_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x109C))
+#define	rPMGR_AUDIO_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10A0))
+#define	rPMGR_I2S0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10A4))
+#define	rPMGR_I2S1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10A8))
+#define	rPMGR_I2S2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10AC))
+#define	rPMGR_I2S3_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10B0))
+#define	rPMGR_SPDIF_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10B4))
+#define	rPMGR_ADSP_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10B8))
+#define	rPMGR_SDIO_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10BC))
+#define	rPMGR_SHA1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10C0))
+#define	rPMGR_SHA2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10C4))
+#define	rPMGR_FMI0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10C8))
+#define	rPMGR_FMI0BCH_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10CC))
+#define	rPMGR_FMI1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10D0))
+#define	rPMGR_FMI1BCH_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10D4))
+#define	rPMGR_FMI_DLL_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10D8))
+#define	rPMGR_XMBIST_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10DC))
+#define	rPMGR_MCA_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10E0))
+#define	rPMGR_SPI0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10E4))
+#define	rPMGR_SPI1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10E8))
+#define	rPMGR_SPI2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10EC))
+#define	rPMGR_SPI3_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10F0))
+#define	rPMGR_SPI4_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10F4))
+#define	rPMGR_UART0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10F8))
+#define	rPMGR_UART1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10FC))
+#define	rPMGR_UART2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1100))
+#define	rPMGR_UART3_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1104))
+#define	rPMGR_UART4_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1108))
+#define	rPMGR_UART5_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x110C))
+#define	rPMGR_UART6_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1110))
+#define	rPMGR_PKE_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1114))
+#define	rPMGR_I2C0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1118))
+#define	rPMGR_I2C1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x111C))
+#define	rPMGR_I2C2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1120))
+#define	rPMGR_PWM_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1124))
+#define	rPMGR_SCRT_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1128))
+#define	rPMGR_GPIO_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x112C))
+#define	rPMGR_SWI_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1130))
+#define	rPMGR_DWI_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1134))
+#define	rPMGR_DEBUG_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1138))
+#define	rPMGR_AIC_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x113C))
+
+#define  PMGR_PS_RESET			(1 << 31)
+
+#define	PMGR_FIRST_PS			(&rPMGR_FIRST_PS)
+#define	PMGR_LAST_PS			(&rPMGR_AIC_PS)
+#define	PMGR_PS_COUNT			(((((u_int32_t)(PMGR_LAST_PS)) - ((u_int32_t)(PMGR_FIRST_PS))) / 4) + 1)
+#define	PMGR_PS_NUM(_r)			(((u_int32_t)&(rPMGR_ ## _r ## _PS) - ((u_int32_t)(PMGR_FIRST_PS))) / 4)
+
+#define	rPMGR_PWR_GATE_CTL_SET		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1200))
+#define	rPMGR_PWR_GATE_CTL_CLR		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1204))
+#define	 PMGR_PWR_GATE_IOP		(1 << 6)
+
+#define	rPMGR_PWR_GATE_GFX_MODE		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1208))
+
+#define	rPMGR_CORE_OFFLINE_SET		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1210))
+#define	rPMGR_CORE_OFFLINE_CLR		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1214))
+#define	rPMGR_WAKE_CORES		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1220))
+
+#define	PMGR_PWR_GATE_TIME_COUNT	(14)
+#define	rPMGR_PWR_GATE_TIME_A(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1240 + (((_n) - 1) * 8)))
+#define	rPMGR_PWR_GATE_TIME_B(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1244 + (((_n) - 1) * 8)))
+#define	rPMGR_PWR_GATE_DBG0		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x12E0))
+#define	rPMGR_PWR_GATE_DBG1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x12E4))
+
+#define rPMGR_VOLMAN_CTL		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1380))
+#define  PMGR_VOLMAN_DISABLE_VOL_CHANGE	(1 << 10)
+#define  PMGR_VOLMAN_CPU_SW_OFF_TIME_VALUE(_x) ((_x) << 2)
+#define  PMGR_VOLMAN_BIT_ORDER_MSB	(0 << 1)
+#define  PMGR_VOLMAN_BIT_ORDER_LSB	(1 << 1)
+#define  PMGR_VOLMAN_BYTE_NO_SWAP	(0 << 0)
+#define  PMGR_VOLMAM_BYTE_SWAP		(1 << 0)
+
+#define	kDVFM_STATE_COUNT		(8)
+#define	kDVFM_STATE_BYPASS		(0)
+#define	kDVFM_STATE_SECUREROM		(1)
+#define	kDVFM_STATE_IBOOT		(2)
+
+#define	PMGR_DVFM_STATE_COUNT		(8)
+#define	rPMGR_DVFM_CFG0(_s)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1400 + ((_s) * 0x20)))
+#define	rPMGR_DVFM_CFG1(_s)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1404 + ((_s) * 0x20)))
+#define  PMGR_DVFM_CFG1_CLK_SRC_SHIFT	(18)
+#define  PMGR_DVFM_CFG1_MIN_VOL_SHIFT	(8)
+#define  PMGR_DVFM_CFG1_SAFE_VOL_SHIFT	(0)
+#define  PMGR_DVFM_CFG1_VOL_MASK	(0xFF)
+#define	rPMGR_DVFM_CFG2(_s)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1408 + ((_s) * 0x20)))
+#define  PMGR_DVFM_CFG2_SRAM_VOL_SHIFT	(24)
+#define  PMGR_DVFM_CFG2_SRAM_VOL_MASK	(0xFF)
+#define	rPMGR_DVFM_CFG3(_s)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x140C + ((_s) * 0x20)))
+#define	rPMGR_DVFM_CFG4(_s)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1410 + ((_s) * 0x20)))
+
+#define	rPMGR_DVFM_COMMON_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1600))
+#define	rPMGR_DVFM_STA_CTL		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1604))
+#define	rPMGR_DVFM_CFG_SEL		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1608))
+#define	rPMGR_DVFM_DELAY		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x160C))
+#define  PMGR_DVFM_DELAY_VOL_CHG_FIX_DLY_SHIFT (8)
+#define  PMGR_DVFM_DELAY_VOL_CHG_VAR_DLY_SHIFT (0)
+#define	rPMGR_DVFM_SRAM_VOL_DELAY	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1610))
+#define  PMGR_DVFM_SRAM_VOL_DELAY_VOL_CHG_FIX_DLY_SHIFT (8)
+#define  PMGR_DVFM_SRAM_VOL_DELAY_VOL_CHG_VAR_DLY_SHIFT (0)
+
+#define	rPMGR_SENSOR_CMD		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1680))
+#define	rPMGR_CORE0_TMP_SEN_RSLT	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1684))
+#define	rPMGR_CORE1_TMP_SEN_RSLT	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1688))
+#define	rPMGR_CORE0_SPD_SEN_RSLT	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x168C))
+#define	rPMGR_CORE1_SPD_SEN_RSLT	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1690))
+
+#define	rPMGR_APSC_STA_CTL		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1700))
+#define  PMGR_APSC_PENDING		(1 << 31)
+#define  PMGR_APSC_SCC_MANUAL_CHANGE	(1 << 25)
+#define  PMGR_APSC_SOC_MANUAL_CHANGE	(1 << 24)
+#define  PMGR_APSC_SCC_MANUAL_STATE(_d)	(((_d) & 0x7) << 20)
+#define  PMGR_APSC_SOC_MANUAL_STATE(_p)	(((_p) & 0xF) << 8)
+#define  PMGR_APSC_MANUAL_CHANGE(_d, _p) \
+	(PMGR_APSC_SCC_MANUAL_CHANGE | PMGR_APSC_SOC_MANUAL_CHANGE | \
+	 PMGR_APSC_SCC_MANUAL_STATE(_d) | PMGR_APSC_SOC_MANUAL_STATE(_p))
+
+#define	rPMGR_SCC_SLEEP_TIME_STAMP_HI	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1704))
+#define	rPMGR_SCC_SLEEP_TIME_STAMP_LO	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1708))
+#define	rPMGR_SCC_WAKE_TIME_STAMP_HI	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x170C))
+#define	rPMGR_SCC_WAKE_TIME_STAMP_LO	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1710))
+#define	rPMGR_SCC_MANUAL_TIME_STAMP_HI	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1714))
+#define	rPMGR_SCC_MANUAL_TIME_STAMP_LO	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1718))
+#define	rPMGR_SOC_SLEEP_TIME_STAMP_HI	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x171C))
+#define	rPMGR_SOC_SLEEP_TIME_STAMP_LO	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1720))
+#define	rPMGR_SOC_WAKE_TIME_STAMP_HI	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1724))
+#define	rPMGR_SOC_WAKE_TIME_STAMP_LO	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1728))
+#define	rPMGR_SOC_MANUAL_TIME_STAMP_HI	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x172C))
+#define	rPMGR_SOC_MANUAL_TIME_STAMP_LO	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1730))
+
+#define	rPMGR_TEST_CLK			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2000))
+
+#define	rPMGR_OSC_DEBUG			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x200C))
+#define	rPMGR_PLL_DEBUG(_n)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2010 + ((_n) * 4)))
+#define  PMGR_PLL_DEBUG_ENABLED			(1 << 31)
+#define  PMGR_PLL_DEBUG_BYP_ENABLED		(1 << 30)
+#define  PMGR_PLL_DEBUG_DBG_STPCLK_EN		(1 << 24)
+#define  PMGR_PLL_DEBUG_FSTATE			(1 << 12)
+#define  PMGR_PLL_DEBUG_STATE(_r)		(((_r) >> 0) & 0xFFF)
+
+#define	rPMGR_DOUBLER_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2034))
+#define  PMGR_DOUBLER_DEBUG_ENABLED	(1 << 31)
+#define  PMGR_DOUBLER_DEBUG_BYP_ENABLED	(1 << 30)
+
+#define	rPMGR_SRAM_EMA_B0_Pn_LO(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2128 + (((_n) - 1) * 8)))
+#define	rPMGR_SRAM_EMA_B0_Pn_HI(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x212C + (((_n) - 1) * 8)))
+
+enum {
+  EMA_MCU = 1,
+  EMA_GFX_PIPES_SYS = 2,
+  EMA_GFX_HYDRA = 3,
+  EMA_VDEC = 4,
+  EMA_VENC = 5,
+  EMA_ISP = 6,
+  EMA_DISP = 7,
+  EMA_NRT = 8,
+  EMA_PMGR = 9,
+  EMA_IOP = 10,
+  EMA_SAUDIO = 11,
+  EMA_CDIO = 12,
+  EMA_FMI = 13,
+  EMA_ADSP = 14,
+};
+
+#define	rPMGR_WDOG_TMR			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3020))
+#define	rPMGR_WDOG_RST			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3024))
+#define	rPMGR_WDOG_INT			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3028))
+#define	rPMGR_WDOG_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x302C))
+
+#define	rPMGR_PERF_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4000))
+#define	rPMGR_PERF_STATUS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4004))
+#define	rPMGR_PERF_CTR0_LO		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4020))
+#define	rPMGR_PERF_CTR0_HI		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4024))
+#define	rPMGR_PERF_CFG0_LO		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4028))
+#define	rPMGR_PERF_CFG0_MID		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x402C))
+#define	rPMGR_PERF_CFG0_HI		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4030))
+#define	rPMGR_PERF_CTR1_LO		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4040))
+#define	rPMGR_PERF_CTR1_HI		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4044))
+#define	rPMGR_PERF_CFG1_LO		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4048))
+#define	rPMGR_PERF_CFG1_MID		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x404C))
+#define	rPMGR_PERF_CFG1_HI		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4050))
+
+#define	rPMGR_SCRATCH0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6000))
+#define	rPMGR_SCRATCH1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6004))
+#define	rPMGR_SCRATCH2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6008))
+#define	rPMGR_SCRATCH3			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x600C))
+#define	rPMGR_SCRATCH4			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6010))
+#define	rPMGR_SCRATCH5			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6014))
+#define	rPMGR_SCRATCH6			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6018))
+#define	rPMGR_SCRATCH7			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x601C))
+#define	rPMGR_SCRATCH8			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6020))
+#define	rPMGR_SCRATCH9			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6024))
+#define	rPMGR_SCRATCH10			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6028))
+#define	rPMGR_SCRATCH11			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x602C))
+#define	rPMGR_SCRATCH12			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6030))
+#define	rPMGR_SCRATCH13			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6034))
+#define	rPMGR_SCRATCH14			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6038))
+#define	rPMGR_SCRATCH15			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x603C))
+
+#define	rPMGR_DAC_FS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x7000))
+
+#define	rPMGR_USB_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x8000))
+
+#define	rPMGR_SHA_SEL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x9000))
+
+#define	rPMGR_SECURITY			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xA000))
+
+#define	rPMGR_GFX_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xB000))
+
+
+#define rPMGR_THERMAL0_CTL0             (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC000))
+#define rPMGR_THERMAL0_CTL1             (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC004))
+#define rPMGR_THERMAL0_CTL2             (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC008))
+#define rPMGR_THERMAL0_CTL3             (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC00C))
+#define rPMGR_THERMAL0_RDBK0            (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC010))
+#define rPMGR_THERMAL0_RDBK1            (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC014))
+#define rPMGR_THERMAL0_SUM              (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC018))
+#define rPMGR_THERMAL0_SUM_CNT          (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC01C))
+#define rPMGR_THERMAL1_CTL0             (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC040))
+#define rPMGR_THERMAL1_CTL1             (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC044))
+#define rPMGR_THERMAL1_CTL2             (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC048))
+#define rPMGR_THERMAL1_CTL3             (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC04C))
+#define rPMGR_THERMAL1_RDBK0            (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC050))
+#define rPMGR_THERMAL1_RDBK1            (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC054))
+#define rPMGR_THERMAL1_SUM              (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC058))
+#define rPMGR_THERMAL1_SUM_CNT          (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC05C))
+
+
+#define PGMR_GET_PERF_STATE_INDEX(_n, _x)	(((_x) >> ((_n) * 4)) & 0xF)
+#define PGMR_SET_PERF_STATE_INDEX(_n, _i)	(((_i) & 0xF) << ((_n) * 4))
+#define PMGR_PERF_STATE_V(_n)			(_n)
+#define PMGR_PERF_STATE_P			(3)
+#define PMGR_PERF_STATE_M(_n)			(4 + (_n))
+
+
+enum {
+	PMGR_CLK_OSC = 0,
+	PMGR_CLK_PLL0,
+	PMGR_CLK_PLL1,
+	PMGR_CLK_PLL2,
+	PMGR_CLK_PLL3,
+	PMGR_CLK_PLL4,
+	PMGR_CLK_PLL5,
+	PMGR_CLK_PLL6,
+	PMGR_CLK_PLL7,
+	PMGR_CLK_PLLUSB,
+	PMGR_CLK_DOUBLER,
+	PMGR_CLK_PLL2_GATED,
+	PMGR_CLK_PLL4_GATED,
+	PMGR_CLK_PLL5_GATED,
+	PMGR_CLK_MCU_FIXED,
+	PMGR_CLK_MCU,
+	PMGR_CLK_CPU,
+	PMGR_CLK_PREDIV0,
+	PMGR_CLK_PREDIV1,
+	PMGR_CLK_PREDIV2,
+	PMGR_CLK_PREDIV3,
+	PMGR_CLK_PREDIV4,
+	PMGR_CLK_PREDIV5,
+	PMGR_CLK_PREDIV6,
+	PMGR_CLK_GFX,
+	PMGR_CLK_GFX_SLC,
+	PMGR_CLK_GFX_SYS,
+	PMGR_CLK_HPERFRT,
+	PMGR_CLK_DISPOUT,
+	PMGR_CLK_VID0,
+	PMGR_CLK_VID1,
+	PMGR_CLK_MIPI_DSI,
+	PMGR_CLK_HPERFNRT,
+	PMGR_CLK_NRT_MEM,
+	PMGR_CLK_VENC_MTX,
+	PMGR_CLK_VENC,
+	PMGR_CLK_VDEC,
+	PMGR_CLK_ISP,
+	PMGR_CLK_IOP,
+	PMGR_CLK_CDIO,
+	PMGR_CLK_LPERFS,
+	PMGR_CLK_PCLK0,
+	PMGR_CLK_PCLK1,
+	PMGR_CLK_PCLK2,
+	PMGR_CLK_PCLK3,
+	PMGR_CLK_AES,
+	PMGR_CLK_MEDIUM0,
+	PMGR_CLK_MEDIUM1,
+	PMGR_CLK_I2C,
+	PMGR_CLK_SDIO,
+	PMGR_CLK_AUDIO,
+	PMGR_CLK_ADSP_PCLK0,
+	PMGR_CLK_ADSP_TCLK,
+	PMGR_CLK_ADSP_TSCLK,
+	PMGR_CLK_UPERF,
+	PMGR_CLK_DEBUG,
+	PMGR_CLK_SCC_PWR,
+	PMGR_CLK_SCC_DMA,
+	PMGR_CLK_SPI0,
+	PMGR_CLK_SPI1,
+	PMGR_CLK_SPI2,
+	PMGR_CLK_SPI3,
+	PMGR_CLK_SPI4,
+	PMGR_CLK_SLOW,
+	PMGR_CLK_SLEEP,
+	PMGR_CLK_USBPHY,
+	PMGR_CLK_USBOHCI,
+	PMGR_CLK_USB12,
+	PMGR_CLK_NCO_REF0,
+	PMGR_CLK_NCO_REF1,
+	PMGR_CLK_COUNT
+};
+
+extern void pmgr_update_device_tree(DTNode *pmgr_node);
+
+#endif /* ! __PLATFORM_SOC_PMGR_H */
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_TRAMPOLINE_H
+#define __PLATFORM_TRAMPOLINE_H
+
+#include <platform/memmap.h>
+#include <platform/soc/hwregbase.h>
+
+#define SECURITY_REG		(PMGR_BASE_ADDR + 0xA000)
+#define ROM_READ_DISABLE	(1 << 0)
+
+#endif /* ! __PLATFORM_TRAMPOLINE_H */
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_USBCONFIG_H
+#define __PLATFORM_USBCONFIG_H
+
+#define USBPHY_CLK_TYPE		(3) /* Use CLKCORE */
+
+#define USBPHY_UOTGTUNE1        (0x749)
+#define USBPHY_UOTGTUNE2        (0x2FF3)
+
+#define USBOTG_AHB_DMA_BURST	(DWCUSB_GAHBCFG_HBST_INCR16)
+
+#ifdef WITH_TARGET_USB_CONFIG
+#include <target/usbconfig.h>
+#endif /* WITH_TARGET_USB_CONFIG */
+
+#endif /* ! __PLATFORM_USBCONFIG_H */
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <arch.h>
+#include <arch/arm/arm.h>
+#include <debug.h>
+#include <drivers/a5iop/a5iop.h>
+#include <platform.h>
+#include <platform/clocks.h>
+#include <platform/int.h>
+#include <platform/memmap.h>
+#include <platform/timer.h>
+#include <platform/soc/hwisr.h>
+#include <platform/soc/pmgr.h>
+#include <sys.h>
+#include <sys/boot.h>
+#include <sys/callout.h>
+
+/*
+ * Platform memory layout.
+ *
+ * The IOP sees SDRAM at its physical location uncached, and has an cached aperture
+ * visible elsewhere.  SDRAM size of up to 1GB is currently supported.
+ * SRAM is not visible/legally usable.
+ *
+ * For some platforms/targets, SDRAM_LEN is not constant and so we 
+ * have to compute a maximum via other means.
+ *
+ * Note that the AE2 Sparrow shares this code.
+ */
+#define MEM_CACHED_BASE		(SDRAM_BASE | 0xc0000000)
+#define SDRAM_MAX_LEN		(SDRAM_BANK_LEN * SDRAM_BANK_COUNT)
+struct mem_static_map_entry mem_static_map_entries[] = {
+        {
+                MEM_CACHED_BASE,                        /* cached */
+                SDRAM_BASE,                             /* uncached */
+                SDRAM_BASE,                             /* physical */
+                SDRAM_MAX_LEN                           /* length */
+        },
+        {MAP_NO_ENTRY, MAP_NO_ENTRY, MAP_NO_ENTRY, 0}
+};
+
+void platform_mmu_setup(bool resume)
+{
+	if (false == resume) {
+		/* Note: sharing settings aren't critical, as SCC doesn't see the AxUSER bits
+		 * and the AxCACHE widget does all the heavy lifting. */
+
+		/* Remap text base to zero, outer uncacheable, shared */
+		arm_mmu_map_section(0, TEXT_BASE, kARMMMUInnerNormalOuterNoncached, true);
+#if MAP_SRAM_CACHED
+		/* Map the SRAM as cacheable, shared */
+		arm_mmu_map_section(SRAM_BASE, SRAM_BASE, kARMMMUNormal, true);
+#endif // MAP_SRAM_CACHED
+		/* Remap all of SDRAM through the cacheable aperture, outer uncacheable, shared */
+		arm_mmu_map_section_range(MEM_CACHED_BASE, SDRAM_BASE, ROUNDUP(SDRAM_BANK_LEN * SDRAM_BANK_COUNT, MB)/MB,
+					  kARMMMUInnerNormalOuterNoncached, true, false);
+		/* Remap all of SDRAM through the uncacheable aperture (existing mappings should be there, but be sure) */
+		arm_mmu_map_section_range(SDRAM_BASE, SDRAM_BASE, ROUNDUP(SDRAM_BANK_LEN * SDRAM_BANK_COUNT, MB)/MB,
+					  kARMMMUStronglyOrdered, false, false);
+	}
+}
+
+bool platform_get_production_mode(void)
+{
+	return(true);
+}
+
+bool platform_get_secure_mode(void)
+{
+	return(true);
+}
+
+void platform_reset(bool panic)
+{
+	for (;;)
+		;
+}
+
+/*
+ * Early init is done every time the IOP starts.
+ */
+int
+platform_early_init()
+{
+#if PLATFORM_VARIANT_IOP
+	/* In general we want power-gating to be disabled. */
+	rPMGR_PWR_GATE_CTL_CLR = PMGR_PWR_GATE_IOP;
+	while (rPMGR_PWR_GATE_CTL_CLR & PMGR_PWR_GATE_IOP) ;
+#endif
+
+	interrupt_init();
+
+	timer_init(0);
+	
+	return(0);
+}
+
+/*
+ * Halt waiting for an interrupt.
+ */
+void
+platform_halt(void)
+{
+	arch_halt();
+}
+
+#if SUPPORT_SLEEP
+
+#if WITH_IOP_POWER_GATING
+
+/*
+ * Deep idle sleep with power gating
+ */
+void
+platform_deep_idle(void)
+{
+	rPMGR_PWR_GATE_CTL_SET = PMGR_PWR_GATE_IOP;
+	while (!(rPMGR_PWR_GATE_CTL_SET & PMGR_PWR_GATE_IOP)) ;
+	a5iop_sleep(1);
+	rPMGR_PWR_GATE_CTL_CLR = PMGR_PWR_GATE_IOP;
+	while (rPMGR_PWR_GATE_CTL_CLR & PMGR_PWR_GATE_IOP) ;
+}
+
+#endif
+
+void
+platform_sleep(void)
+{
+	/* We assume power-gating is disabled, which it need to be so
+	 * the IOP wrapper registers don't disappear. */
+	a5iop_sleep(0);
+}
+
+#endif
+
+/*
+ * Cache control
+ */
+void
+platform_cache_operation(int operation, void *address, u_int32_t length)
+{
+	a5iop_cache_operation(operation, address, length);
+}
+
+/*
+ * Host doorbell uses a SWI in the AIC.
+ */
+static void	(* _doorbell_handler)(void *arg);
+static void
+platform_doorbell_handler(void *arg)
+{
+	/* clear the doorbell before passing up */
+	interrupt_clear_ipc(INT_IOP);
+	_doorbell_handler(arg);
+}
+
+void
+platform_init_iop_doorbell(void (* handler)(void *arg), void *arg)
+{
+	_doorbell_handler = handler;
+	install_int_handler(INT_IOP, platform_doorbell_handler, arg);
+	set_int_type(INT_IOP, INT_TYPE_IRQ | INT_TYPE_LEVEL);
+	unmask_int(INT_IOP);
+}
+
+void
+platform_mask_doorbell(void)
+{
+	mask_int(INT_IOP);
+}
+
+void
+platform_unmask_doorbell(void)
+{
+	unmask_int(INT_IOP);
+}
+
+void
+platform_ring_host_doorbell(void)
+{
+	interrupt_generate_ipc(INT_HOST);
+}
+
+int
+platform_init_nmi(void (*handler)(void *arg), void *arg)
+{
+#ifdef INT_IOP_NMI
+	install_int_handler(INT_IOP_NMI, handler, arg);
+	set_int_type(INT_IOP_NMI, INT_TYPE_FIQ | INT_TYPE_LEVEL);
+	unmask_int(INT_IOP_NMI);
+#endif
+
+	return(0);
+}
+
+/*
+ * Clock management.
+ *
+ * Currently the IOP does none for this platform.
+ */
+void clock_gate(int device, bool enable)
+{
+}
@@ -0,0 +1,311 @@
+/*
+ * Copyright (C) 2010-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <debug.h>
+#include <drivers/miu.h>
+#include <platform.h>
+#include <platform/memmap.h>
+#include <platform/miu.h>
+#include <platform/soc/miu.h>
+#include <platform/soc/pmgr.h>
+#include <platform/clocks.h>
+#include <platform/soc/hwclocks.h>
+
+static void miu_configure_bridge(const u_int32_t *bridge_settings);
+
+#define BRIDGE_SHIFT		(16)
+#define BRIDGE_MASK		(0xFFFF)
+#define NRT_DART_WIDGETS	(0 << BRIDGE_SHIFT)
+#define NRT_DART_BRIDGE		(1 << BRIDGE_SHIFT)
+#define NRT_TOP_WIDGETS		(2 << BRIDGE_SHIFT)
+#define NRT_TOP_BRIDGE		(3 << BRIDGE_SHIFT)
+#define RT_TOP_WIDGETS		(4 << BRIDGE_SHIFT)
+#define RT_TOP_BRIDGE		(5 << BRIDGE_SHIFT)
+#define UPERF_WIDGETS		(6 << BRIDGE_SHIFT)
+#define UPERF_BRIDGE		(7 << BRIDGE_SHIFT)
+#define CDIO_WIDGETS		(8 << BRIDGE_SHIFT)
+#define CDIO_BRIDGE		(9 << BRIDGE_SHIFT)
+
+static const u_int32_t bridge_registers[] = {
+	NRT_DART_WIDGETS_BASE_ADDR,	NRT_DART_PL301_BASE_ADDR,
+	NRT_TOP_WIDGETS_BASE_ADDR,	NRT_TOP_PL301_BASE_ADDR,
+	RT_TOP_WIDGETS_BASE_ADDR,	RT_TOP_PL301_BASE_ADDR,
+	UPERF_WIDGETS_BASE_ADDR,	UPERF_PL301_BASE_ADDR,
+	CDIO_WIDGETS_BASE_ADDR,		CDIO_PL301_BASE_ADDR,
+};
+
+#if APPLICATION_SECUREROM || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
+// The following settings are based on H5P Tunables Revision 0.46
+
+static const u_int32_t bridge_settings_static[] = {
+	// Configure recommended transaction limits in CDIO
+	CDIO_WIDGETS | CDIO_IOP_RRLIMIT,	0x00000000,
+	CDIO_WIDGETS | CDIO_IOP_WRLIMIT,	0x00000000,
+	CDIO_WIDGETS | CDIO_IOP_RTLIMIT,	0x00003F3F,
+	CDIO_WIDGETS | CDIO_IOP_WTLIMIT,	0x00003F3F,
+	CDIO_WIDGETS | CDIO_CDMA_RRLIMIT,	0x00000000,
+	CDIO_WIDGETS | CDIO_CDMA_WRLIMIT,	0x00000000,
+	CDIO_WIDGETS | CDIO_CDMA_RTLIMIT,	0x00003F3F,
+	CDIO_WIDGETS | CDIO_CDMA_WTLIMIT,	0x00003F3F,
+	CDIO_WIDGETS | CDIO_UPERF_RRLIMIT,	0x00000000,
+	CDIO_WIDGETS | CDIO_UPERF_WRLIMIT,	0x00000000,
+	CDIO_WIDGETS | CDIO_UPERF_RTLIMIT,	0x00003F3F,
+	CDIO_WIDGETS | CDIO_UPERF_WTLIMIT,	0x00003F3F,
+	CDIO_WIDGETS | CDIO_AUDIO_RRLIMIT,	0x00000000,
+	CDIO_WIDGETS | CDIO_AUDIO_WRLIMIT,	0x00000000,
+	CDIO_WIDGETS | CDIO_AUDIO_RTLIMIT,	0x00003F3F,
+	CDIO_WIDGETS | CDIO_AUDIO_WTLIMIT,	0x00003F3F,
+	CDIO_WIDGETS | CDIO_PIO_RTLIMIT,	0x00003F3F,
+	CDIO_WIDGETS | CDIO_PIO_WTLIMIT,	0x00000404,
+	CDIO_WIDGETS | CDIO_CIM_RTLIMIT,	0x00003F3F,
+	CDIO_WIDGETS | CDIO_CIM_WTLIMIT, 	0x00000F0F,
+
+	// Configure recommended bridge settings in CDIO
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0,	0x00000000,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0,	0x00000000,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1,	0x00000000,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1,	0x00000000,
+
+	// Configure recommended features in CDIO
+	CDIO_WIDGETS | CDIO_IOP_WGATHER,	0x00000100,
+	CDIO_WIDGETS | CDIO_IOP_RC_REMAP(0),	0xffffbbbb,
+	CDIO_WIDGETS | CDIO_IOP_RC_REMAP(1),	0xfedcba98,
+	CDIO_WIDGETS | CDIO_IOP_RC_REMAP(2),	0xffffbbbb,
+	CDIO_WIDGETS | CDIO_IOP_RC_REMAP(3),	0xfedcba98,
+	CDIO_WIDGETS | CDIO_IOP_WC_REMAP(0),	0x76767676,
+	CDIO_WIDGETS | CDIO_IOP_WC_REMAP(1),	0xfedcfedc,
+	CDIO_WIDGETS | CDIO_IOP_WC_REMAP(2),	0x76767676,
+	CDIO_WIDGETS | CDIO_IOP_WC_REMAP(3),	0xfedcfedc,
+	CDIO_WIDGETS | CDIO_IOP_C_REMAP_EN,	0x00000003,
+	CDIO_WIDGETS | CDIO_CDMA_WGATHER,	0x00000100,
+	CDIO_WIDGETS | CDIO_UPERF_WGATHER,	0x00000100,
+	CDIO_WIDGETS | CDIO_AUDIO_WGATHER,	0x00000100,
+
+	// Configure recommended traffic attributes in UPERF
+	//	LLT Reads and Writes
+	//	AxCACHE = Cacheable
+	//	AxUSER = enable Shared bit
+	UPERF_WIDGETS | UPERF_OTG_QOS,		0x01010101,
+	UPERF_WIDGETS | UPERF_OTG_CACHE,	0x0107010B,
+	UPERF_WIDGETS | UPERF_EHCI_QOS,		0x01010101,
+	UPERF_WIDGETS | UPERF_EHCI_CACHE,	0x0107010B,
+	UPERF_WIDGETS | UPERF_OHCI0_QOS,	0x01010101,
+	UPERF_WIDGETS | UPERF_OHCI0_CACHE,	0x0107010B,
+	UPERF_WIDGETS | UPERF_OHCI1_QOS,	0x01010101,
+	UPERF_WIDGETS | UPERF_OHCI1_CACHE,	0x0107010B,
+
+	// Configure recommended bridge settings in UPERF
+	UPERF_BRIDGE | UPERF_RTLIMIT,		0x00000404,
+	UPERF_BRIDGE | UPERF_WTLIMIT,		0x00000404,
+
+	0, 0,
+	0, 0
+};
+#endif	// APPLICATION_SECUREROM || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
+
+#if WITH_DEVICETREE || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
+static const u_int32_t bridge_settings_dynamic[] = {
+	// Configure recommended transaction limits in HPerf-NRT DART
+	NRT_DART_WIDGETS | HPERF_NRT_DART_DART_RTLIMIT,		0x00003F3F,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_DART_WTLIMIT,		0x00003F3F,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER0_RTLIMIT,	0x00000707,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER0_WTLIMIT,	0x00000404,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER1_RTLIMIT,	0x00000707,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER1_WTLIMIT,	0x00000404,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_JPEG0_RTLIMIT,	0x00003F3F,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_JPEG0_WTLIMIT,	0x00003F3F,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_JPEG1_RTLIMIT,	0x00003F3F,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_JPEG1_WTLIMIT,	0x00003F3F,
+
+	// Configure recommended bridge settings in HPerf-NRT DART
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI,	0x00000000,	// JPEG0 High Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI,	0x01000001,	// JPEG1 High Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI,	0x02000002,	// Scaler0 High Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI,	0x03000003,	// Sclaer1 High Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI,	0x00000000,	// JPEG0 High Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI,	0x01000001,	// JPEG1 High Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI,	0x02000002,	// Scaler0 High Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI,	0x03000003,	// Sclaer1 High Priority
+
+	// Configure recommended bridge settings in HPerf-NRT DART
+	NRT_DART_WIDGETS | HPERF_NRT_DART_JPEG0_QOS,		0x01010101,	// JPEG0 LLT Traffic for R&W
+	NRT_DART_WIDGETS | HPERF_NRT_DART_JPEG1_QOS,		0x01010101,	// JPEG1 LLT Traffic for R&W
+	0, 0,
+
+	// Configure recommended transaction limits in HPerf-NRT Top
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_TOP_RTLIMIT,		0x00003F3F,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_TOP_WTLIMIT,		0x00000F0F,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_VENC_RTLIMIT,		0x00003F3F,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_VENC_WTLIMIT,		0x00003F3F,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_VDEC_RTLIMIT,		0x00003F3F,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_VDEC_WTLIMIT,		0x00003F3F,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_AUX_RTLIMIT,		0x00003F3F,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_AUX_WTLIMIT,		0x00003F3F,
+
+	// Configure recommended bridge settings in HPerf-NRT Top
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI,		0x00000000,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI,		0x01000001,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI,		0x02000002,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI,		0x03000003,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI,		0x00000000,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI,		0x01000001,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI,		0x02000002,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI,		0x03000003,
+
+	// Configure recommended features in HPerf-NRT Top
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_AUX_WGATHER,		0x00000100,
+	0, 0,
+
+	// Configure recommended transaction limits in HPerf-RT Top
+	RT_TOP_WIDGETS | HPERF_RT_TOP_DISP0_RTLIMIT,		0x00000909,
+	RT_TOP_WIDGETS | HPERF_RT_TOP_DISP1_RTLIMIT,		0x00001212,
+	RT_TOP_WIDGETS | HPERF_RT_TOP_ISP_RTLIMIT,		0x00003F3F,
+	RT_TOP_WIDGETS | HPERF_RT_TOP_ISP_WTLIMIT,		0x00003F3F,
+	RT_TOP_WIDGETS | HPERF_RT_TOP_TOP_RTLIMIT,		0x00003F3F,
+	RT_TOP_WIDGETS | HPERF_RT_TOP_TOP_WTLIMIT,		0x00000F0F,
+
+	// Configure recommended bridge settings in HPerf-RT Top
+	RT_TOP_BRIDGE | HPERF_RT_TOP_AR_CHAN_ARB_MI,		0x00000000,
+	RT_TOP_BRIDGE | HPERF_RT_TOP_AW_CHAN_ARB_MI,		0x00000000,
+	0, 0,
+
+	0, 0
+};
+#endif	// APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC
+
+int miu_initialize_internal_ram(void)
+{
+#if APPLICATION_SECUREROM
+	// Ensure that rPMGR_SCRATCH0-3 get cleared
+	rPMGR_SCRATCH0 = 0;
+	rPMGR_SCRATCH1 = 0;
+	rPMGR_SCRATCH2 = 0;
+	rPMGR_SCRATCH3 = 0;
+#endif /* APPLICATION_SECUREROM */
+
+	// Save the Security Epoch in the top byte of PMGR_SCRATCH0
+	rPMGR_SCRATCH0 &= ~0xFF000000;
+	rPMGR_SCRATCH0 |= (platform_get_security_epoch()) << 24;
+
+	return 0;
+}
+
+int miu_init(void)
+{
+#if APPLICATION_IBOOT && !PRODUCT_IBEC
+	// Verify that the Security Epoch in PMGR_SCRATCH0 matches
+	if ((rPMGR_SCRATCH0 >> 24) != platform_get_security_epoch()) {
+		panic("miu_init: Epoch Mismatch\n");
+	}
+#endif
+
+#if APPLICATION_SECUREROM || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
+	// Configure bridges that are statically powered
+	clock_gate(CLK_UPERF, true);
+	miu_configure_bridge(bridge_settings_static);
+	clock_gate(CLK_UPERF, false);
+#endif
+
+#if APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC
+	// Configure bridges that are dynamically powered
+	clock_gate(CLK_HPERFNRT, true);
+	clock_gate(CLK_HPERFRT, true);
+	miu_configure_bridge(bridge_settings_dynamic);
+	clock_gate(CLK_HPERFNRT, false);
+	clock_gate(CLK_HPERFRT, false);
+#endif
+
+	/* remap whatever bank of ram we're in to zero */
+	if (TEXT_BASE == SRAM_BASE)
+		miu_select_remap(REMAP_SRAM);
+	else if ((TEXT_BASE >= SDRAM_BASE) && (TEXT_BASE < SDRAM_END))
+		miu_select_remap(REMAP_SDRAM);
+
+	return 0;
+}
+
+static void miu_configure_bridge(const u_int32_t *bridge_settings)
+{
+	volatile u_int32_t *reg;
+	u_int32_t cnt = 0, bridge, offset, data;
+
+	while ((bridge_settings[cnt] != 0) || (bridge_settings[cnt + 1] != 0)) {
+		while ((bridge_settings[cnt] != 0) || (bridge_settings[cnt + 1] != 0)) {
+			bridge = bridge_settings[cnt] >> BRIDGE_SHIFT;
+			offset = bridge_settings[cnt] & BRIDGE_MASK;
+			data = bridge_settings[cnt + 1];
+			reg = (volatile u_int32_t *)(bridge_registers[bridge] + offset);
+			*reg = data;
+			cnt += 2;
+		}
+		cnt += 2;
+	}
+}
+
+void miu_suspend(void)
+{
+	/* nothing required for suspend */
+}
+
+int miu_initialize_dram(bool resume)
+{
+#if APPLICATION_IBOOT && WITH_HW_AMC
+	mcu_initialize_dram(resume);
+#endif
+
+	return 0;
+}
+
+void miu_select_remap(enum remap_select sel)
+{
+	u_int32_t tmp;
+
+	switch (sel) {
+		case REMAP_SRAM:
+			tmp = miu_read_l2cadrmap() & ~3;
+			tmp |= 1; // RemapMode = 1 (L2C RAM)
+			miu_write_l2cadrmap(tmp);
+			break;
+
+		case REMAP_SDRAM:
+			tmp = miu_read_l2cadrmap() & ~3;
+			tmp |= 2; // RemapMode = 2 (MEM)
+			miu_write_l2cadrmap(tmp);
+			break;
+	}
+}
+
+void miu_bypass_prep(int step)
+{
+#if APPLICATION_IBOOT && WITH_HW_AMC
+	extern void mcu_bypass_prep(int step);
+	mcu_bypass_prep(step);
+#endif
+}
+
+#if WITH_DEVICETREE
+
+void miu_update_device_tree(DTNode *pmgr_node)
+{
+	u_int32_t propSize;
+	char *propName;
+	void *propData;
+
+	// Fill in the bridge-settings property
+	propName = "bridge-settings";
+	if (FindProperty(pmgr_node, &propName, &propData, &propSize)) {
+		if (propSize < sizeof(bridge_settings_dynamic)) {
+			panic("miu_update_device_tree: bridge-settings property is too small (0x%x)", propSize);
+		}
+		memcpy(propData, bridge_settings_dynamic, sizeof(bridge_settings_dynamic));
+	}
+}
+
+#endif
@@ -0,0 +1,15 @@
+# Copyright (C) 2010 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_MIU=1
+
+ALL_OBJS += $(LOCAL_DIR)/miu.o
@@ -0,0 +1,17 @@
+# Copyright (C) 2010 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_CLOCKS=1 \
+	WITH_HW_PLATFORM_POWER=1 \
+	WITH_HW_POWER_GATING=0
+
+ALL_OBJS += $(LOCAL_DIR)/pmgr.o
@@ -0,0 +1,124 @@
+# Copyright (C) 2010-2013 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR	:= $(GET_LOCAL_DIR)
+
+GLOBAL_INCLUDES += $(LOCAL_DIR)/include
+
+# modules implied by this platform
+MODULES		+= \
+	platform/defaults \
+	platform/generic \
+	arch/$(ARCH)
+
+##############################################################################
+# Code running on the main CPU
+#
+ifeq ($(PLATFORM_VARIANT),)
+
+ARM_CPU		:= apple-swift
+
+# Devmap chip ID based on sub-platform identifier
+ifeq ($(SUB_PLATFORM),s5l8950x)
+DEVMAP_CHIP_ID := 8950
+endif
+
+MAX_DFU_SIZE	:= 393216
+
+ifeq ($(TEXT_BANK),srom)
+TEXT_BASE	:= 0x00000000
+endif
+ifeq ($(TEXT_BANK),sram)
+TEXT_BASE	:= 0x10000000
+endif
+ifeq ($(TEXT_BANK),sdram)
+TEXT_BASE	:= 0xBFF00000
+endif
+
+OPTIONS		+= \
+	AIC_CPU_ID=0 \
+	WITH_CLASSIC_SUSPEND_TO_RAM=1 \
+	WITH_LEGACY_PANIC_LOGS=1 \
+	WITH_NO_RANDOM_HEAP_COOKIE=1 \
+	WITH_NO_RANDOM_STACK_COOKIE=1 \
+	WITH_NON_COHERENT_DMA=1 \
+	WITH_ROM_TRAMPOLINE=1 \
+	PLATFORM_ENTROPY_RATIO=200 \
+	PLATFORM_IRQ_COUNT=192 \
+	PLATFORM_START_FUNCTION=_platform_start \
+	TEXT_BASE="$(TEXT_BASE)" \
+	TEXT_FOOTPRINT="$(TEXT_FOOTPRINT)"
+
+#	L2_CACHE_SIZE=1048576 \
+#
+
+GLOBAL_LDFLAGS	+= \
+	-seg1addr $(TEXT_BASE)
+
+ifeq ($(APPLICATION),SecureROM)
+# This selects the start of the DATA segment and the end of the INSECURE_MEMORY area
+DATA_BASE	:= 0x10060000
+
+OPTIONS		+= \
+	DATA_BASE="$(DATA_BASE)"
+
+GLOBAL_LDFLAGS	+= \
+	-segaddr __DATA $(DATA_BASE)
+endif
+
+ALL_OBJS	+= \
+	$(LOCAL_DIR)/asm.o \
+	$(LOCAL_DIR)/init.o
+
+endif
+
+##############################################################################
+# Code running on the IOP
+#
+ifeq ($(PLATFORM_VARIANT),IOP)
+
+OPTIONS		+= \
+	PLATFORM_VARIANT_IOP=1 \
+	AIC_CPU_ID=2 \
+	WITH_PLATFORM_HALT=1 \
+	SUPPORT_SLEEP=1 \
+	WITH_IOP_POWER_GATING=1 \
+	DEEP_IDLE_THRESHOLD_US=10000
+
+ARM_CPU		:=	cortex-a5
+
+TEXT_BASE	:=	0x0
+
+OPTIONS		+= \
+	TEXT_BASE="$(TEXT_BASE)"
+
+ALL_OBJS	+= $(LOCAL_DIR)/iop_init.o
+endif
+
+##############################################################################
+# Code running on the audio engine
+#
+ifeq ($(PLATFORM_VARIANT),Audio)
+
+OPTIONS		+= \
+	PLATFORM_VARIANT_AUDIO=1 \
+	WITH_PLATFORM_HALT=1 \
+	SUPPORT_SLEEP=1
+
+ARM_CPU		:=	cortex-a5
+
+TEXT_BASE	:=	0x0
+
+OPTIONS		+= \
+	TEXT_BASE="$(TEXT_BASE)" \
+	TEXT_FOOTPRINT="$(TEXT_FOOTPRINT)"
+
+ALL_OBJS	+= $(LOCAL_DIR)/iop_init.o
+
+endif