first and last commit

2023-07-08 13:03:17 -07:00
commit 1bf4efd552
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __TARGET_ADBE_SETTINGS_H
+#define __TARGET_ADBE_SETTINGS_H
+
+static struct adbe_v1_tuneable adbe_tuneables[] = {
+	{
+		.name = "default",
+		.adbe0_vblank_pos_vbi_pulse	= 0x0000,
+		.adbe0_vblank_clk_gate_wakeup 	= 0x0000,
+		.adbe0_vblank_clk_gate_idle 	= 0x0001,
+		.adbe0_vblank_blk_idle_dpb	= 0x0000,
+		.adbe0_vblank_blk_idle_aap	= 0x0000,
+		.adbe0_tunable_mode_ctrl	= (DBEMODECNTL_DYN_CLK_GATE_ENABLE | DBEMODECNTL_AFC_TEARDOWN_ENABLE | DBEMODECNTL_PMGR_CLK_GATE_ENABL| DBEMODECNTL_BLK_CLK_GATE_ENABLE),
+		.adbe0_aap_support		= 1,
+	},
+};
+
+#endif
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __TARGET_ASPNANDCONFIG_H
+#define __TARGET_ASPNANDCONFIG_H
+
+//MLC devices
+#if SUB_TARGET_J85M
+#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 4
+#else
+#define ASPNAND_MLC_WRITE_DIES_IN_PARALLEL 8
+#endif
+#define ASPNAND_SLC_WRITE_DIES_IN_PARALLEL 4
+#define ASPNAND_ERASE_DIES_IN_PARALLEL 8
+#if SUB_TARGET_J85M
+#define ASPNAND_READ_DIES_IN_PARALLEL 4
+#else
+#define ASPNAND_READ_DIES_IN_PARALLEL 8
+#endif
+#define ASPNAND_MLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
+#define ASPNAND_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
+#define ASPNAND_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
+#define ASPNAND_READ_LOW_POWER_DIES_IN_PARALLEL 2
+
+//TLC devices
+#define ASPNAND_TLC_TLC_WRITE_DIES_IN_PARALLEL 8
+#define ASPNAND_TLC_SLC_WRITE_DIES_IN_PARALLEL 8
+#define ASPNAND_TLC_ERASE_DIES_IN_PARALLEL 4
+#define ASPNAND_TLC_READ_DIES_IN_PARALLEL 4
+#define ASPNAND_TLC_TLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
+#define ASPNAND_TLC_SLC_WRITE_LOW_POWER_DIES_IN_PARALLEL 2
+#define ASPNAND_TLC_ERASE_LOW_POWER_DIES_IN_PARALLEL 2
+#define ASPNAND_TLC_READ_LOW_POWER_DIES_IN_PARALLEL 2
+
+// rdar://problem/18371949 - ASPNAND_INDIRECTION_MEMORY and ASPNAND_LEGACY_INDIRECTION_MEMORY
+// should be the same for all post-OkemoTaos targets
+#if SUB_TARGET_J85
+#define ASPNAND_INDIRECTION_MEMORY (4*1024*1024)
+#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
+#elif SUB_TARGET_J86
+#define ASPNAND_INDIRECTION_MEMORY (4*1024*1024)
+#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
+#elif SUB_TARGET_J87
+#define ASPNAND_INDIRECTION_MEMORY (4*1024*1024)
+#define ASPNAND_LEGACY_INDIRECTION_MEMORY (2*1024*1024)
+#elif SUB_TARGET_J85M
+#define ASPNAND_INDIRECTION_MEMORY (4*1024*1024)
+#define ASPNAND_LEGACY_INDIRECTION_MEMORY (4*1024*1024)
+#elif SUB_TARGET_J86M
+#define ASPNAND_INDIRECTION_MEMORY (4*1024*1024)
+#define ASPNAND_LEGACY_INDIRECTION_MEMORY (4*1024*1024)
+#elif SUB_TARGET_J87M
+#define ASPNAND_INDIRECTION_MEMORY (4*1024*1024)
+#define ASPNAND_LEGACY_INDIRECTION_MEMORY (4*1024*1024)
+#else
+#error  // need to add a value for any new subtarget
+#endif
+
+#endif
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef TARGET_BOARDID_H
+#define TARGET_BOARDID_H
+
+#define TARGET_BOARD_ID_J85MAP		(0x32)
+#define TARGET_BOARD_ID_J85MDEV		(0x33)
+#define TARGET_BOARD_ID_J86MAP		(0x34)
+#define TARGET_BOARD_ID_J86MDEV		(0x35)
+#define TARGET_BOARD_ID_J87MAP		(0x36)
+#define TARGET_BOARD_ID_J87MDEV		(0x37)
+
+#endif
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2012 - 2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __TARGET_GPIODEF_H
+#define __TARGET_GPIODEF_H
+
+/* iPad4,x specific gpio -> pin mappings */
+
+#include <platform/gpio.h>
+
+/* define target-specific gpios in a generic fashion here. */
+#define GPIO_LCD_PWR_EN		GPIO(14, 6)
+#define GPIO_RINGER_AB		GPIO(0, 6)
+
+/* Board Revision */
+#define GPIO_BOARD_REV0		GPIO(1, 2)
+#define GPIO_BOARD_REV1		GPIO(1, 3)
+#define GPIO_BOARD_REV2		GPIO(1, 4)
+
+/* which IICs to initialize */
+#if SUB_TARGET_J85M || SUB_TARGET_J86M || SUB_TARGET_J87M
+#define IICS_MASK		(0xF)
+#else
+#define IICS_MASK		(0xD)
+#endif
+
+#define TRISTAR_IIC_BUS		(0)
+
+/* D2089 watchdog tickle, 'KEEPACT' */
+#define GPIO_WDOG_TICKLE	GPIO(2, 6)
+
+#endif /* ! __TARGET_GPIODEF_H */
@@ -0,0 +1,294 @@
+/*
+ * Copyright (C) 2012 - 2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+/* Default iPad4,x SoC Pin Configuration from I/O spreadsheet rev 0.17
+   The pin configuration is tracked in the I/O spreadsheet:
+   <rdar://problem/12902078> J85: IOSpreadsheet 
+
+   The I/O spreadsheet should be updated before updating the pin configuration */
+
+/* Different drive strength for AP and DEV. */
+#if PIN_CFG_AP
+#define AP_DEV_DRIVE_STR(ap, dev) DRIVE_##ap
+#elif PIN_CFG_DEV
+#define AP_DEV_DRIVE_STR(ap, dev) DRIVE_##dev
+#endif
+
+/* Different slew rate for AP and DEV. */
+#if PIN_CFG_AP
+#define AP_DEV_SLEW(ap, dev) ap##_SLEW
+#elif PIN_CFG_DEV
+#define AP_DEV_SLEW(ap, dev) dev##_SLEW
+#endif
+
+#if TARGET_HAS_BASEBAND
+#       define IFF_BB(cfg)  cfg
+#else
+#       define IFF_BB(cfg)  CFG_DISABLED | PULL_DOWN
+#endif
+
+
+#if PIN_CFG_AP
+static const u_int32_t gpio_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
+#elif PIN_CFG_DEV
+static const u_int32_t gpio_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
+#endif
+
+/* Port  0 */
+	CFG_DISABLED,								//   0 : TST_CLKOUT		-> SOC_TST_CLKOUT
+	CFG_FUNC0 | DRIVE_X1 | FAST_SLEW,					//   1 : WDOG			-> WDOG_SOC
+	CFG_IN,									//   2 : GPIO[0]		-> GPIO_BTN_HOME_L
+	CFG_IN,									//   3 : GPIO[1]		-> GPIO_BTN_ONOFF_L
+	CFG_IN | PULL_UP,							//   4 : GPIO[2]		-> GPIO_BTN_VOL_UP_L
+	CFG_IN | PULL_UP,							//   5 : GPIO[3]		-> GPIO_BTN_VOL_DOWN_L
+	CFG_IN,									//   6 : GPIO[4]		-> GPIO_BTN_SRL_L
+	CFG_DISABLED,								//   7 : GPIO[5]		-> GPIO_SOC2BEACON_EN
+
+/* Port  1 */
+	CFG_OUT_0 | DRIVE_X1 | FAST_SLEW,					//   8 : GPIO[6]		-> GPIO_SOC2AJ_HS4_SHUNT_EN
+	CFG_OUT_0 | DRIVE_X1 | FAST_SLEW,					//   9 : GPIO[7]		-> GPIO_SOC2AJ_HS3_SHUNT_EN
+	CFG_DISABLED,								//  10 : GPIO[8]		-> GPIO_BOARD_REV0
+	CFG_DISABLED,								//  11 : GPIO[9]		-> GPIO_BOARD_REV1
+	CFG_DISABLED,								//  12 : GPIO[10]		-> GPIO_BOARD_REV2
+	CFG_IN | PULL_UP,							//  13 : GPIO[11]		-> GPIO_CODEC_IRQ_L
+	IFF_BB(CFG_OUT_0) | DRIVE_X1 | FAST_SLEW,				//  14 : GPIO[12]		-> GPIO_SOC2BB_WAKE_MODEM
+	CFG_IN | PULL_UP,							//  15 : GPIO[13]		-> GPIO_GRAPE_IRQ_L
+
+/* Port  2 */
+	CFG_DISABLED,								//  16 : GPIO[14]		-> BB_IPC_GPIO
+	CFG_IN | PULL_UP,							//  17 : GPIO[15]		-> GPIO_ALS_IRQ_L
+	CFG_DISABLED,								//  18 : GPIO[16]		-> GPIO_BOARD_ID3
+	IFF_BB(CFG_IN | PULL_DOWN),						//  19 : GPIO[17]		-> GPIO_BB2SOC_RESET_DET_L
+	CFG_DISABLED,								//  20 : GPIO[18]		-> GPIO_BOOT_CONFIG0
+	CFG_IN | PULL_UP,							//  21 : GPIO[19]		-> GPIO_PMU2SOC_IRQ_L
+	CFG_OUT_0 | DRIVE_X1 | FAST_SLEW,					//  22 : GPIO[20]		-> GPIO_SOC2PMU_KEEPACT
+	CFG_OUT_0 | DRIVE_X1 | FAST_SLEW,					//  23 : GPIO[21]		-> GPIO_GRAPE_RST_L
+
+/* Port  3 */
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+
+/* Port  4 */
+	CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X4) | AP_DEV_SLEW(SLOW, FAST),		//  32 : UART1_TXD		-> UART1_SOC2BT_TX
+	CFG_FUNC0,								//  33 : UART1_RXD		-> UART1_BT2SOC_TX
+	CFG_OUT_1 | AP_DEV_DRIVE_STR(X1, X4) | AP_DEV_SLEW(SLOW, FAST),		//  34 : UART1_RTSN		-> UART1_SOC2BT_RTS_L
+	CFG_FUNC0,								//  35 : UART1_CTSN		-> UART1_BT2SOC_RTS_L
+	CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X4) | AP_DEV_SLEW(SLOW, FAST),		//  36 : UART2_TXD		-> UART2_SOC2WLAN_TX
+	CFG_FUNC0,								//  37 : UART2_RXD		-> UART2_WLAN2SOC_TX
+	CFG_DISABLED,
+	CFG_DISABLED,
+
+/* Port  5 */
+	IFF_BB(CFG_IN) | AP_DEV_DRIVE_STR(X1, X4) | AP_DEV_SLEW(SLOW, FAST),	//  40 : UART3_TXD		-> UART3_SOC2BB_TX
+	IFF_BB(CFG_FUNC0),							//  41 : UART3_RXD		-> UART3_BB2SOC_TX
+	IFF_BB(CFG_IN) | AP_DEV_DRIVE_STR(X1, X4) | AP_DEV_SLEW(SLOW, FAST),	//  42 : UART3_RTSN		-> UART3_SOC2BB_RTS_L
+	IFF_BB(CFG_FUNC0),							//  43 : UART3_CTSN		-> UART3_BB2SOC_RTS_L
+	CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | FAST_SLEW,			//  44 : UART5_RTXD		-> UART5_BATT_RTXD
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+
+/* Port  6 */
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+
+/* Port  7 */
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+
+/* Port  8 */
+	CFG_FUNC0 | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),				//  64 : UART4_TXD		-> UART4_SOC2OSCAR_TXD
+	CFG_FUNC0,								//  65 : UART4_RXD		-> UART4_OSCAR2SOC_RXD
+	CFG_OUT_1 | DRIVE_X1 | FAST_SLEW,					//  66 : UART4_RTSN		-> GPIO_OSCAR_RESET_L
+	CFG_IN,									//  67 : UART4_CTSN		-> PMU_GPIO_OSCAR2PMU_HOST_WAKE
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					//  68 : SPI1_SCLK		-> SPI1_GRAPE_SCLK
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					//  69 : SPI1_MOSI		-> SPI1_GRAPE_MOSI
+	CFG_FUNC0,								//  70 : SPI1_MISO		-> SPI1_GRAPE_MISO
+	CFG_OUT_1 | DRIVE_X1 | FAST_SLEW,					//  71 : SPI1_SSIN		-> SPI1_GRAPE_CS_L
+
+/* Port  9 */
+	CFG_DISABLED,								//  72 : SPI0_SCLK		-> GPIO_BOARD_ID0
+	CFG_DISABLED,								//  73 : SPI0_MOSI		-> GPIO_BOARD_ID1
+	CFG_DISABLED,								//  74 : SPI0_MISO		-> GPIO_BOARD_ID2
+	CFG_DISABLED,
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					//  76 : SPI2_SCLK		-> SPI2_CODEC_SCLK
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					//  77 : SPI2_MOSI		-> SPI2_CODEC_MOSI
+	CFG_FUNC0,								//  78 : SPI2_MISO		-> SPI2_CODEC_MISO
+	CFG_OUT_1 | DRIVE_X1 | FAST_SLEW,					//  79 : SPI2_SSIN		-> SPI2_CODEC_CS_L
+
+/* Port 10 */
+	CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | AP_DEV_SLEW(SLOW, FAST),		//  80 : I2C0_SDA		-> I2C0_SDA_1V8
+	CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | AP_DEV_SLEW(SLOW, FAST),		//  81 : I2C0_SCL		-> I2C0_SCL_1V8
+	CFG_DISABLED,								//  82 : I2C1_SDA		-> I2C1_SOC2OSCAR_SWDIO_1V8
+	CFG_DISABLED,								//  83 : I2C1_SCL		-> I2C1_SOC2OSCAR_SWDCLK_1V8
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					//  84 : ISP0_SDA		-> ISP0_CAM_REAR_SDA
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					//  85 : ISP0_SCL		-> ISP0_CAM_REAR_SCL
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					//  86 : ISP1_SDA		-> ISP1_CAM_FRONT_SDA
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					//  87 : ISP1_SCL		-> ISP1_CAM_FRONT_SCL
+
+/* Port 11 */
+	CFG_OUT_0 | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),				//  88 : SENSOR0_RST		-> ISP0_CAM_REAR_SHUTDOWN_L
+	CFG_OUT_0 | DRIVE_X4 | FAST_SLEW,					//  89 : SENSOR0_CLK		-> ISP0_CAM_REAR_CLK_R
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_OUT_0 | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),				//  92 : SENSOR1_RST		-> ISP1_CAM_FRONT_SHUTDOWN_L
+	CFG_OUT_0 | DRIVE_X4 | FAST_SLEW,					//  93 : SENSOR1_CLK		-> ISP1_CAM_FRONT_CLK_R
+	CFG_DISABLED,
+	CFG_DISABLED,
+
+/* Port 12 */
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 100 : I2C2_SDA		-> I2C2_SDA_1V8
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 101 : I2C2_SCL		-> I2C2_SCL_1V8
+	CFG_DISABLED | PULL_DOWN,						// 102 : GPIO[22]		-> GPIO_BB2SOC_GPS_SYNC
+	IFF_BB(CFG_IN) | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),			// 103 : GPIO[23]		-> GPIO_SOC2BB_RADIO_ON_L
+
+/* Port 13 */
+	CFG_DISABLED,
+	CFG_DISABLED,								// 105 : GPIO[25]		-> GPIO_BOOT_CONFIG1
+	CFG_IN,									// 106 : GPIO[26]		-> GPIO_FORCE_DFU
+	CFG_DISABLED,								// 107 : GPIO[27]		-> TP_GPIO_DFU_STATUS
+	CFG_DISABLED,								// 108 : GPIO[28]		-> GPIO_BOOT_CONFIG2
+	CFG_DISABLED,								// 109 : GPIO[29]		-> GPIO_BOOT_CONFIG3
+	CFG_IN | DRIVE_X1 | FAST_SLEW,						// 110 : GPIO[30]		-> GPIO_SOC2OSCAR_DBGEN
+	IFF_BB(CFG_IN) | AP_DEV_SLEW(SLOW, FAST),				// 111 : GPIO[31]		-> GPIO_SOC2BB_RST_L
+
+
+/* Port 14 */
+	IFF_BB(CFG_IN),								// 112 : GPIO[32]		-> GPIO_PROX_IRQ_L
+	CFG_DISABLED | PULL_DOWN,						// 113 : GPIO[33]		-> GPIO_BB2SOC_GSM_TXBURST
+	CFG_OUT_0 | DRIVE_X1 | FAST_SLEW,					// 114 : GPIO[34]		-> GPIO_SPKAMP_RST_L
+	CFG_OUT_0 | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),				// 115 : GPIO[35]		-> GPIO_BT_WAKE
+	CFG_IN,									// 116 : GPIO[36]		-> GPIO_TS2SOC2PMU_INT
+	CFG_IN | PULL_UP,							// 117 : GPIO[37]		-> GPIO_SPKAMP_LEFT_IRQ_L
+	CFG_OUT_0 | DRIVE_X1 | FAST_SLEW,					// 118 : GPIO[38]		-> GPIO_SOC2LCD_PWREN
+	CFG_OUT_0 | PULL_DOWN,							// 119 : DISP_VSYNC		-> DISPLAY_SYNC
+
+/* Port 15 */
+	CFG_FUNC0 | DRIVE_X1 | FAST_SLEW,					// 120 : SOCHOT0		-> SOCHOT0_L
+	CFG_FUNC0 | DRIVE_X1 | FAST_SLEW,					// 121 : SOCHOT1		-> SOCHOT1_L
+	CFG_FUNC0 | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),				// 122 : UART0_TXD		-> UART0_SOC_TXD
+	CFG_FUNC0,								// 123 : UART0_RXD		-> UART0_SOC_RXD
+	CFG_DISABLED,
+	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,					// 125 : DWI_DO			-> DWI_AP_DO
+	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,					// 126 : DWI_CLK		-> DWI_AP_CLK
+	CFG_DISABLED,
+
+/* Port 16 */
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 128 : I2S0_LRCK		-> I2S0_CODEC_ASP_LRCK
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 129 : I2S0_BCLK		-> I2S0_CODEC_ASP_BCLK
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 130 : I2S0_DOUT		-> I2S0_CODEC_ASP_DOUT
+	CFG_FUNC0,								// 131 : I2S0_DIN		-> I2S0_CODEC_ASP_DIN
+	CFG_FUNC0 | DRIVE_X4 | FAST_SLEW,					// 132 : I2S1_MCK		-> I2S1_SPKAMP_MCK_R
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 133 : I2S1_LRCK		-> I2S1_SPKAMP_LRCK
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 134 : I2S1_BCLK		-> I2S1_SPKAMP_BCLK
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 135 : I2S1_DOUT		-> I2S1_SPKAMP_DOUT
+
+/* Port 17 */
+	CFG_FUNC0,								// 136 : I2S1_DIN		-> I2S1_SPKAMP_DIN
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 137 : I2S2_LRCK		-> I2S2_CODEC_XSP_LRCK
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 138 : I2S2_BCLK		-> I2S2_CODEC_XSP_BCLK
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 139 : I2S2_DOUT		-> I2S2_CODEC_XSP_DOUT
+	CFG_FUNC0,								// 140 : I2S2_DIN		-> I2S2_CODEC_XSP_DIN
+	CFG_IN | PULL_UP,							// 141 : I2S3_MCK		-> GPIO_SPKAMP_RIGHT_IRQ_L
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 142 : I2S3_LRCK		-> I2S3_SOC2BT_LRCK
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 143 : I2S3_BCLK		-> I2S3_SOC2BT_BCLK
+
+/* Port 18 */
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 144 : I2S3_DOUT		-> I2S3_SOC2BT_DATA
+	CFG_FUNC0,								// 145 : I2S3_DIN		-> I2S3_BT2SOC_DATA
+	IFF_BB(CFG_DISABLED),							// 146 : I2S4_MCK		-> BB_JTAG_TCK
+	IFF_BB(CFG_DISABLED),							// 147 : I2S4_LRCK		-> BB_JTAG_TDI
+	IFF_BB(CFG_DISABLED),							// 148 : I2S4_BCLK		-> BB_JTAG_TMS
+	IFF_BB(CFG_DISABLED),							// 149 : I2S4_DOUT		-> BB_JTAG_TRST_L
+	IFF_BB(CFG_DISABLED),							// 150 : I2S4_DIN		-> BB_JTAG_TDO
+	CFG_DISABLED,
+
+/* Port 19 */
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+
+/* Port 20 */
+	CFG_OUT_0 | DRIVE_X1 | FAST_SLEW,					// 160 : TMR32_PWM0		-> OSCAR_TIME_SYNC_HOST_INT
+	CFG_OUT_0 | DRIVE_X1 | FAST_SLEW,					// 161 : TMR32_PWM1		-> GPIO_SPKAMP_KEEPALIVE
+	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 162 : TMR32_PWM2		-> CLK_32K_SOC2CUMULUS
+	CFG_OUT_0 | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),				// 163 : SIO_7816UART0_SDA	-> HSIC1_SOC2WLAN_HOST_RDY
+	CFG_IN,									// 164 : SIO_7816UART0_SCL	-> HSIC1_WLAN2SOC_DEVICE_RDY
+	CFG_IN | PULL_DOWN,							// 165 : SIO_7816UART0_RST	-> HSIC1_WLAN2SOC_REMOTE_WAKE
+	IFF_BB(CFG_OUT_0) | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),			// 166 : SIO_7816UART1_SDA	-> HSIC2_SOC2BB_HOST_RDY
+	IFF_BB(CFG_IN | PULL_DOWN),						// 167 : SIO_7816UART1_SCL	-> HSIC2_BB2SOC_DEVICE_RDY
+
+/* Port 21 */
+	IFF_BB(CFG_IN | PULL_DOWN),						// 168 : SIO_7816UART1_RST	-> HSIC2_BB2SOC_REMOTE_WAKE
+	CFG_FUNC0 | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),				// 169 : UART6_TXD		-> UART6_TS_ACC_TXD
+	CFG_FUNC0,								// 170 : UART6_RXD		-> UART6_TS_ACC_RXD
+	CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | AP_DEV_SLEW(SLOW, FAST),		// 171 : I2C3_SDA		-> I2C3_SDA_1V8
+	CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | AP_DEV_SLEW(SLOW, FAST),		// 172 : I2C3_SCL		-> I2C3_SCL_1V8
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+
+/* Port 22 */
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+
+/* Port 23 */
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+	CFG_DISABLED,
+
+/* Port 24 */
+	CFG_FUNC0,								// 192 : EDP_HPD		-> EDP_HPD
+	CFG_FUNC0 | DRIVE_X4 | FAST_SLEW,					// 193 : I2S0_MCK		-> I2S0_CODEC_ASP_MCK_R
+	CFG_DISABLED,
+};
+
+#undef AP_DEV_DRIVE_STR
+#undef AP_DEV_SLEW
+#undef IFF_BB
@@ -0,0 +1,148 @@
+#ifndef __TARGET_POWERCONFIG_H
+#define __TARGET_POWERCONFIG_H
+
+#include <drivers/gasgauge.h>
+
+/* configuration per target */
+
+#define PMU_IIC_BUS		0
+
+/* this configuration is very PMU specific and must be included exactly once in power.c */
+#ifdef POWERCONFIG_PMU_SETUP
+
+static const struct pmu_setup_struct pmu_ldo_warm_setup[] =
+{
+};
+
+static const struct pmu_setup_struct pmu_ldo_cold_setup[] =
+{
+	{ PMU_IIC_BUS, kD2089_ACTIVE2,          0x03 }, // WLEDA/B BST
+#if SUB_TARGET_J85M || SUB_TARGET_J86M || SUB_TARGET_J87M
+	{ PMU_IIC_BUS, kD2089_ACTIVE3,          0xB6 }, // pp3v0_s2r_mesa (LDO5)
+	{ PMU_IIC_BUS, kD2089_HIBERNATE3,       0xA8 }, // TriStar(LDO7) Mesa(LDO5) pp3v0_s2r_sensor (LDO3) <rdar://16302495>
+	{ PMU_IIC_BUS, kD2089_LDO5_VSEL,        0x4C }, // <rdar://problem/16328834> J85M - change PMU LDO5 to 3.1V
+#else
+	{ PMU_IIC_BUS, kD2089_HIBERNATE3,       0x88 }, // pp3v0_s2r_sensor (LDO3)
+#endif
+	{ PMU_IIC_BUS, kD2089_HIBERNATE6,       0x24 }, // pp1v8_s2r_sw3 (buck3_sw3) and pp1v2_s2r_sw2 (buck4_sw2)
+};
+
+static const struct pmu_setup_struct pmu_warm_init[] =
+{
+};
+
+static const struct pmu_setup_struct pmu_cold_init[] =
+{
+	/* GPIO configuration from I/O spreadsheet.
+	   <rdar://problem/12902078> J85 IOSpreadsheet Tracker
+	   Request spreadsheet update before modifying
+
+           The following differences from OTP are intentional:
+	   	- GPIO6: Enable wake
+		- GPIO7: Enable wake
+		- GPIO8: Enable wake
+		- GPIO9: Enable wake (baseband targets)
+		- GPIO10: Enable wake
+		- GPIO11: Enable wake
+		- GPIO12: Hi level interrupt, enable wake
+		- GPIO13: Enable wake
+		- GPIO14: Disable wake
+		- GPIO16: Enable wake
+		*/
+#if SUB_TARGET_J85M || SUB_TARGET_J86M || SUB_TARGET_J87M
+	{ PMU_IIC_BUS, kD2089_GPIO1,		0x79 },	// PMU_GPIO_CLK_32K_OSCAR		in hi, disable PU, no wake, PD
+#else
+	{ PMU_IIC_BUS, kD2089_GPIO1,		0x49 },	// PMU_GPIO_CLK_32K_OSCAR		32k, Push-Pull, VBUCK3
+#endif
+	{ PMU_IIC_BUS, kD2089_GPIO2,		0x49 },	// PMU_GPIO_CLK_32K_WLAN		32k, Push-Pull, VBUCK3
+	{ PMU_IIC_BUS, kD2089_GPIO3,		0x09 },	// PMU_GPIO_BT_REG_ON			Out 0, Push-Pull, VBUCK3
+	{ PMU_IIC_BUS, kD2089_GPIO4,		0x09 },	// PMU_GPIO_WLAN_REG_ON			Out 0, Push-Pull, VBUCK3
+	{ PMU_IIC_BUS, kD2089_GPIO5,		0x09 },	// PMU_GPIO_PMU2BB_RST_L		Out 0, Push-Pull, VBUCK3
+	{ PMU_IIC_BUS, kD2089_GPIO6,		0xDA },	// UART5_BATT_TRXD			In, F Edge, Wake, PD
+	{ PMU_IIC_BUS, kD2089_GPIO7,		0xBA },	// PMU_GPIO_BT2PMU_HOST_WAKE		In, R Edge, Wake, PD
+	{ PMU_IIC_BUS, kD2089_GPIO8,		0xBA },	// PMU_GPIO_WLAN2PMU_HOST_WAKE		In, R Edge, Wake, PD
+#if TARGET_HAS_BASEBAND
+	{ PMU_IIC_BUS, kD2089_GPIO9,		0x7A },	// PMU_GPIO_BB2PMU_HOST_WAKE		In, L High, Wake, PD
+#else
+	{ PMU_IIC_BUS, kD2089_GPIO9,		0xB9 },	// PMU_GPIO_BB2PMU_HOST_WAKE		In, R Edge, PD
+#endif
+	{ PMU_IIC_BUS, kD2089_GPIO10,		0xEA },	// PMU_GPIO_CODEC_HS_INT_L		In, Any Edge, Wake, PU, VBUCK3
+	{ PMU_IIC_BUS, kD2089_GPIO11,		0xFA },	// PMU_GPIO_MB_HALL1_IRQ		In, Any Edge, Wake, No PU
+	{ PMU_IIC_BUS, kD2089_GPIO12,		0x7B },	// GPIO_TS2SOC2PMU_INT			In, Hi level, Wake, PD
+	{ PMU_IIC_BUS, kD2089_GPIO13,		0xF8 },	// PMU_GPIO_MB_HALL2_IRQ		In, Any Edge, No PU
+	{ PMU_IIC_BUS, kD2089_GPIO14,		0xF8 },	// PMU_GPIO_MB_HALL3_IRQ		In, Any Edge, No PU
+	{ PMU_IIC_BUS, kD2089_GPIO15,		0xC8 },	// PMU_GPIO_CODEC_RST_L			In, F Edge, PU, VBUCK3
+	{ PMU_IIC_BUS, kD2089_GPIO16,		0x7B },	// PMU_GPIO_OSCAR2PMU_HOST_WAKE		In, L High, Wake, PD, No PU
+	{ PMU_IIC_BUS, kD2089_GPIO17,		0x01 },	// PMU_GPIO_BB_VBUS_DET			Out 0, Push-Pull, VCC_MAIN
+
+	{ PMU_IIC_BUS, kD2089_BUCK_DWI_CTRL0, 	0x03 },		// enable DWI for BUCK0, BUCK1
+	{ PMU_IIC_BUS, kD2089_ACT_TO_HIB_DLY,	0x03 },		// set ACT_TO_HIB_DLY to 3 (6ms)
+	{ PMU_IIC_BUS, kDIALOG_SYS_CONTROL2,	0x11 },		// enable HIB_32kHz (for WIFI/BT) and DWI
+
+};
+
+static const struct pmu_setup_struct pmu_backlight_enable[] =
+{
+	{ PMU_IIC_BUS, kDIALOG_WLED_ISET,	0xD4 },	// 50% value from OS
+	{ PMU_IIC_BUS, kDIALOG_WLED_ISET2,	0x00 },
+	{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL,		// enable all LED strings
+		(kDIALOG_WLED_CONTROL_WLED_ENABLE1 |
+		 kDIALOG_WLED_CONTROL_WLED_ENABLE2 |
+		 kDIALOG_WLED_CONTROL_WLED_ENABLE3 |
+		 kDIALOG_WLED_CONTROL_WLED_ENABLE4 |
+		 kDIALOG_WLED_CONTROL_WLED_ENABLE5 |
+		 kDIALOG_WLED_CONTROL_WLED_ENABLE6) },
+	{ PMU_IIC_BUS, kDIALOG_WLED_OPTIONS,		// enable LED Power
+		(kDIALOG_WLED_CONTROL2_WLED_RAMP_EN |
+		 kDIALOG_WLED_CONTROL2_WLED_DITH_EN) }
+};
+
+static const struct pmu_setup_struct pmu_backlight_disable[] =
+{
+	{ PMU_IIC_BUS, kDIALOG_WLED_CONTROL, 0x0 }    // disable LED power
+};
+
+static const struct core_rails_struct soc_rails[] =
+{
+	{ PMU_IIC_BUS, 0, kD2089_BUCK2_VSEL }
+};
+
+static const struct core_rails_struct cpu_rails[] =
+{
+	{ PMU_IIC_BUS, 0, kD2089_BUCK0_VSEL }
+};
+
+static const struct core_rails_struct ram_rails[] =
+{
+	{ PMU_IIC_BUS, 0, kD2089_BUCK5_VSEL }
+};
+
+#endif /* POWERCONFIG_PMU_SETUP */
+
+#define TARGET_USE_CHARGE_TABLE 1
+static const struct power_charge_limits pmu_charge_table[16] = {
+	{ 4200,	        1000, 2100, 2600 },
+	{ USHRT_MAX,    1000, 2100, 1950 },
+	{ 4200,	        2000, 4500, 2600 },
+	{ USHRT_MAX,    2000, 4500, 2600 }
+};
+
+#define NO_BATTERY_VOLTAGE		2700
+#define MIN_BOOT_BATTERY_VOLTAGE	3600
+#define TARGET_BOOT_BATTERY_VOLTAGE	3700
+#define TARGET_BOOT_BATTERY_CAPACITY	50
+#define PRECHARGE_BACKLIGHT_LEVEL	1287	/* 10% brightness */
+#define ALWAYS_BOOT_BATTERY_VOLTAGE	(TARGET_BOOT_BATTERY_VOLTAGE + 100)
+#define TARGET_PRECHARGE_ALWAYS_DISPLAY_IDLE	1
+#define TARGET_MAX_USB_INPUT_CURRENT	2400
+
+#define GASGAUGE_BATTERYID_BLOCK	1
+#define GASGAUGE_CHARGETABLE_BLOCK	3
+
+// NEEDS TO BE REPLACED WITH PROPER INFO
+static const unsigned int atv_voltage_limit[16] = { 3650, 3700, 3750, 3800, 3850, 3900, 3950, 4000, 4050, 4100, 4150, 4200, 4250, 4300, 4350, 4400 };
+static const unsigned int atv_current_limit[16] = {    0,  200,  400,  650,  850, 1100, 1350, 1550, 1700, 1950, 2200, 2400, 2600, 2600, 2600, 2600 };
+
+#define ACC_PWR_LDO			(6)
+
+#endif
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2012, 2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __TARGET_UARTCONFIG_H
+#define __TARGET_UARTCONFIG_H
+
+/* define one debug serial ports */
+#define DEBUG_SERIAL_PORT		(0)
+
+#define HDQGAUGE_SERIAL_PORT		(5)
+
+#if SUPPORT_FPGA
+#define UART_OVERSAMPLE_OVERRIDE        (11)
+#endif
+
+#endif
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __TARGET_USBCONFIG_H
+#define __TARGET_USBCONFIG_H
+
+#ifdef USBPHY_OTGTUNE0
+
+#undef USBPHY_OTGTUNE0
+#define USBPHY_OTGTUNE0		(0x354493B3)
+
+#endif /* USBPHY_OTGTUNE0 */
+
+#endif /* __TARGET_USBCONFIG_H */
@@ -0,0 +1,404 @@
+/*
+ * Copyright (C) 2012 - 2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <debug.h>
+#include <drivers/display.h>
+#include <drivers/flash_nor.h>
+#include <drivers/iic.h>
+#include <drivers/power.h>
+#include <lib/devicetree.h>
+#include <lib/env.h>
+#include <lib/mib.h>
+#include <lib/paint.h>
+#include <lib/syscfg.h>
+#include <platform.h>
+#include <platform/gpio.h>
+#include <platform/gpiodef.h>
+#include <platform/memmap.h>
+#include <sys.h>
+#include <sys/boot.h>
+#include <sys/menu.h>
+#include <sys/task.h>
+#include <target.h>
+#include <platform/soc/display_color_manager_tables.h>
+
+#if SUB_TARGET_J85 || SUB_TARGET_J86 || SUB_TARGET_J87
+#define IPAD4B_DEV1_PROTO0_REV		(0x7)
+#define IPAD4B_DEV2_PROTO1_REV		(0x6)		// with Beacon backlight controller
+#define IPAD4B_EVT_REV			(0x5)		// removed Beacon
+#endif
+
+#if SUB_TARGET_J85M || SUB_TARGET_J86M || SUB_TARGET_J87M
+#define IPAD4BM_DEV1_PROTO0_REV		(0x7)
+#endif
+
+static bool		gpio_board_rev_valid;
+static u_int32_t	gpio_board_rev;
+#if (APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC))
+#include <drivers/displayport/displayport.h>
+static dp_t		dp;
+#endif
+
+MIB_CONSTANT(kMIBTargetOsPictureScale,	kOIDTypeUInt32, 2);
+MIB_CONSTANT(kMIBTargetPictureRotate,	kOIDTypeInt32,  0);
+MIB_CONSTANT(kMIBTargetDisplayCMEngammaTablePtr,	kOIDTypeStruct, (void *)linear_rgb_engamma_tables);
+MIB_CONSTANT(kMIBTargetDisplayCMEngammaTableCount,	kOIDTypeUInt32, ARRAY_SIZE(linear_rgb_engamma_tables));
+MIB_CONSTANT(kMIBTargetDisplayCMDegammaTablePtr,	kOIDTypeStruct, (void *)linear_rgb_degamma_tables);
+MIB_CONSTANT(kMIBTargetDisplayCMDegammaTableCount,	kOIDTypeUInt32, ARRAY_SIZE(linear_rgb_degamma_tables));
+MIB_CONSTANT(kMIBTargetDisplayCMMatrixTablePtr,		kOIDTypeStruct, (void *)linear_identity_matrix_tables);
+MIB_CONSTANT(kMIBTargetDisplayCMMatrixTableCount,	kOIDTypeUInt32, ARRAY_SIZE(linear_identity_matrix_tables));
+
+// Don't panic for these targets because of <rdar://problem/14236421>.
+MIB_CONSTANT(kMIBTargetPanicOnUnknownDclrVersion,	kOIDTypeBoolean, false);
+
+static u_int32_t ipad4b_get_board_rev(void)
+{
+
+	if (!gpio_board_rev_valid) {
+		gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_IN);
+		gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_IN);
+		gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_IN);
+
+		gpio_configure_pupdn(GPIO_BOARD_REV0, GPIO_PUP);
+		gpio_configure_pupdn(GPIO_BOARD_REV1, GPIO_PUP);
+		gpio_configure_pupdn(GPIO_BOARD_REV2, GPIO_PUP);
+
+		spin(100); // Wait 100us
+
+		gpio_board_rev = 
+			(gpio_read(GPIO_BOARD_REV2) << 2) |
+			(gpio_read(GPIO_BOARD_REV1) << 1) |
+			(gpio_read(GPIO_BOARD_REV0) << 0);
+
+		gpio_configure(GPIO_BOARD_REV0, GPIO_CFG_DFLT);
+		gpio_configure(GPIO_BOARD_REV1, GPIO_CFG_DFLT);
+		gpio_configure(GPIO_BOARD_REV2, GPIO_CFG_DFLT);
+
+		gpio_board_rev_valid = true;
+	}
+
+	return gpio_board_rev;
+}
+
+
+void target_early_init(void)
+{
+}
+
+void target_late_init(void)
+{
+}
+
+void target_init(void)
+{
+#if WITH_HW_FLASH_NOR
+	flash_nor_init(SPI_NOR0);
+#endif
+	// <rdar://problem/13372834> IRATE needs to be 25 mA on J85
+	//	WLED IRATE is in the low 3 bits, and 0x3 corresponds to 25mA. If OTP is
+	//	not properly programmed, use test mode to change to 25mA.
+	uint8_t value;
+	iic_read(0, 0x78, (uint8_t[]){0x06,0x07}, 2, &value, 1, IIC_NORMAL);
+	if ((value & 0x7) != 3) {
+		iic_write(0, 0x78, (uint8_t[]){0x70,0x00,0x1d},3);
+		iic_write(0, 0x78, (uint8_t[]){0x06,0x07,(value & 0xf8) | 0x3}, 3);
+		iic_write(0, 0x78, (uint8_t[]){0x70,0x00,0x00},3);
+	}
+}
+
+void target_quiesce_hardware(void)
+{
+}
+
+void target_poweroff(void)
+{
+}
+
+
+int target_bootprep(enum boot_target target)
+{
+	return 0;
+}
+
+bool target_should_recover(void)
+{
+	return platform_get_request_dfu2() && power_has_usb();
+}
+
+bool target_should_poweron(bool *cold_button_boot)
+{
+#if WITH_HW_POWER
+	if (power_get_boot_flag() == kPowerBootFlagColdButton) *cold_button_boot = true;
+#else
+	*cold_button_boot = false;
+#endif // WITH_HW_POWER
+
+	return !*cold_button_boot || platform_get_request_dfu1();
+}
+
+bool target_should_poweroff(bool at_boot)
+{
+	return platform_get_request_dfu1() && (!at_boot || !power_has_usb());
+}
+
+bool beacon_supported()
+{
+	bool supported = false;
+#if SUB_TARGET_J85 || SUB_TARGET_J86 || SUB_TARGET_J87
+	supported = (ipad4b_get_board_rev() == IPAD4B_DEV2_PROTO1_REV) ? true:false;
+#endif
+	return supported;
+}
+
+#if APPLICATION_IBOOT
+void target_watchdog_tickle(void)
+{
+	u_int32_t value = gpio_read(GPIO_WDOG_TICKLE);
+	gpio_write(GPIO_WDOG_TICKLE, value ^ 1);
+}
+#endif // APPLICATION_IBOOT
+
+void * target_get_display_configuration(void)
+{
+#if (APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC))
+	dp.mode	=		0x1;
+	dp.type	=		0x1;
+	dp.min_link_rate =	0x6;
+	dp.max_link_rate =	0x6;
+	dp.lanes =		0x4;
+	dp.ssc =		0x0;
+	dp.alpm =		0x0;
+	dp.vrr_enable =		0x0;
+	dp.vrr_on =		0x0;
+	return ((void *)(&dp));
+#else
+	return NULL;
+#endif
+}
+
+#if WITH_ENV
+
+void target_setup_default_environment(void)
+{
+	env_set("boot-device", "asp_nand", 0);
+	env_set("display-color-space","RGB888", 0);
+	env_set("display-timing", "ipad4b", 0);
+}
+
+#endif // WITH_ENV
+
+#if WITH_DEVICETREE
+
+int target_update_device_tree(void)
+{
+#if WITH_HW_DISPLAY_EDP	
+	DTNode		*clcd_node = NULL, *backlight_node = NULL, *lcd_node = NULL;
+#endif	
+	DTNode		*node;
+	uint32_t	propSize;
+	char		*propName;
+	void		*propData;
+
+	if (beacon_supported()) {
+		panic("Unsupported board revision");
+	}
+
+#if WITH_HW_DISPLAY_EDP
+        if (FindNode(0, DP_DTPATH, &node)) {
+                extern int edp_update_device_tree(DTNode *edp_node, DTNode *lcd_node, DTNode *clcd_node, DTNode *backlight_node);
+        	FindNode(0, "arm-io/disp0", &clcd_node);
+        	FindNode(0, DP_DTPATH "/lcd", &lcd_node);
+                FindNode(0, "backlight", &backlight_node);
+                edp_update_device_tree(node, lcd_node, clcd_node, backlight_node);
+        }
+#endif
+
+	// Update the codec node with acoustic transducer scale data
+	{
+		uint8_t atscData[20];
+
+		if (syscfgCopyDataForTag('ATSc', atscData, sizeof(atscData)) > 0) {
+			// Update codec
+			if (FindNode(0, "arm-io/spi2/audio-codec", &node)) {
+				propName = "at-scale-imic";
+				if (FindProperty(node, &propName, &propData, &propSize)) {
+					memcpy(propData, &atscData[0], sizeof(uint32_t));
+				}
+				propName = "at-scale-smic";
+				if (FindProperty(node, &propName, &propData, &propSize)) {
+					memcpy(propData, &atscData[4], sizeof(uint32_t));
+				}
+			}
+		}
+	}
+
+	// Update the backlight calibration data
+	if (FindNode(0, "backlight", &node)) {
+		propName = "backlight-calibration";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			syscfgCopyDataForTag('BLCl', propData, propSize);
+		}
+	}
+
+	// Update the compass calibration data
+	if (FindNode(0, "arm-io/uart4/oscar/compass", &node)) {
+		propName = "compass-calibration";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			syscfgCopyDataForTag('CPAS', propData, propSize);
+		}
+	}
+    
+	// Update the gyro calibration data
+	if (FindNode(0, "arm-io/uart4/oscar/gyro", &node)) {
+		propName = "gyro-orientation";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			syscfgCopyDataForTag('GRot', propData, propSize);
+		}
+		propName = "gyro-sensitivity-calibration";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			syscfgCopyDataForTag('GSCl', propData, propSize);
+		}
+		propName = "gyro-temp-table";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			syscfgCopyDataForTag('GYTT', propData, propSize);
+		}
+		propName = "gyro-interrupt-calibration";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			syscfgCopyDataForTag('GICl', propData, propSize);
+		}
+	}
+	
+	// Update accelerometer calibration data
+	if (FindNode(0, "arm-io/uart4/oscar/accelerometer", &node)) {
+		propName = "accel-orientation";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			syscfgCopyDataForTag('ARot', propData, propSize);
+		}
+		propName = "low-temp-accel-offset";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			syscfgCopyDataForTag('LTAO', propData, propSize);
+		}
+		propName = "accel-sensitivity-calibration";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			syscfgCopyDataForTag('ASCl', propData, propSize);
+		}
+		propName = "accel-interrupt-calibration";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			syscfgCopyDataForTag('AICl', propData, propSize);
+		}
+	}
+
+
+	// Update the bottom prox calibration data
+	if (FindNode(0, "arm-io/i2c3/prox", &node)) {
+		propName = "prox-calibration-blob";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			syscfgCopyDataForTag('CPCl', propData, propSize);
+		}
+	}
+
+	// Update the als calibration data
+	if (FindNode(0, "arm-io/i2c3/als", &node)) {
+		propName = "alsCalibration";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			syscfgCopyDataForTag('LSCI', propData, propSize);
+		}
+	}
+
+	// Update charger calibration data
+	if (FindNode(0, "charger", &node)) {
+		propName = "usb-input-limit-calibration";
+		if (FindProperty(node, &propName, &propData, &propSize)) {		
+            if ( syscfgCopyDataForTag('CBAT', propData, propSize)==20 ) {
+        		((uint32_t*)propData)[4]=0;
+			}
+		}
+	}
+
+
+	// Update the speaker calibration data
+	if (FindNode(0, "arm-io/i2c2/audio-speaker0", &node)) {
+		propName = "speaker-rdc";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			syscfgCopyDataForTag('SRdc', propData, propSize);
+		}
+				
+		propName = "speaker-config";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			uint8_t vpbr[2]; // calibrated @ 3.1V
+			if (syscfgCopyDataForTag('VPBR', vpbr, sizeof(vpbr)) == 2) {
+			    ((uint8_t *)propData)[12] = (((uint8_t *)propData)[12] & ~0x1f) | ( (vpbr[0]-1) & 0x1f);
+			    ((uint8_t *)propData)[32] = (((uint8_t *)propData)[32] & ~0x1f) | ( (vpbr[1]-1) & 0x1f);
+			}
+			uint8_t vbst[2];
+			if (syscfgCopyDataForTag('VBST', vbst, sizeof(vbst)) == 2) {
+			    ((uint8_t *)propData)[16] = vbst[0];
+			    ((uint8_t *)propData)[36] = vbst[1];
+			}
+		}
+	}
+
+#if SUB_TARGET_J85M || SUB_TARGET_J86M || SUB_TARGET_J87M
+
+	// Update the X162 calibration data
+	if (FindNode(0, "arm-io/spi3/mesa", &node)) {
+		propName = "calibration-blob";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			syscfgCopyDataForTag('FSCl', propData, propSize);
+		}
+		propName = "modulation-ratio";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			syscfgCopyDataForTag('NvMR', propData, propSize);
+		}
+	}
+#endif
+
+	return 0;
+}
+
+#endif // WITH_DEVICETREE
+
+#if WITH_PAINT
+
+// The default background is expected to to be black and the artwork is expected
+// to be white. This arrangement will be inverted depending upon the cover glass
+// color of the device.
+
+// Sample DClr_override values for testing devices without DClr syscfg entries (enclosure/cover glass):
+// gray/black:		setenv DClr_override 000200009B9899003C3B3B0000000000
+// silver/white:	setenv DClr_override 00020000D8D9D700E3E4E10000000000
+
+static color_policy_invert_t target_cover_glass_color_table[] = {
+	{ RGB( 59,  59,  60), false },	// Black - black background, white logo
+	{ RGB(225, 228, 227), true  },	// White - white background, black logo
+};
+
+color_policy_t *target_color_map_init(enum colorspace cs, color_policy_t *color_policy)
+{
+	// Must have a color policy structure passed in.
+	if (color_policy == NULL)
+		goto fail;
+
+	// We only support the RGB888 colorspace.
+	if (cs != CS_RGB888)
+		goto fail;
+
+	color_policy->policy_type  = COLOR_MAP_POLICY_INVERT;
+	color_policy->color_table  = (void *)target_cover_glass_color_table;
+	color_policy->color_count  = ARRAY_SIZE(target_cover_glass_color_table);
+	color_policy->map_color    = NULL;	// Use standard remapper
+
+	return color_policy;
+
+fail:
+	return NULL;
+}
+#endif	// WITH_PAINT
+
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2009-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <drivers/apple/gpio.h>
+#include <platform/soc/hwregbase.h>
+#include <target.h>
+
+#define PIN_CFG_AP 1
+#include <target/pinconfig-nomesa.h>
+#undef PIN_CFG_AP
+
+#define PIN_CFG_DEV 1
+#include <target/pinconfig-nomesa.h>
+#undef PIN_CFG_DEV
+
+const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
+{
+	if (target_config_ap())
+		return gpio_default_cfg_ap;
+	else
+		return gpio_default_cfg_dev;
+}
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <debug.h>
+#include <target.h>
+#include <target/powerconfig.h>
+
+#if WITH_DEVICETREE
+
+bool
+target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
+{
+	int length = 0;
+	bool result = false;
+
+	if ((result = target_get_property_base(prop, data, maxdata, retlen)) == false) {
+		switch(prop) {
+		case TARGET_PROPERTY_RESTORE_BACKLIGHT_LEVEL:
+			// fix the restore backlight level at the precharge level,
+			// to make sure the backlight does not cause the battery to
+			// drain during restore
+			if (maxdata >= (ssize_t)sizeof(uint32_t)) {
+				result = true;
+				length = sizeof(uint32_t);
+				*(uint32_t *)data = PRECHARGE_BACKLIGHT_LEVEL;
+			}
+			break;
+			
+		default:
+			break;
+		}
+	}
+
+	if (retlen != NULL) *retlen = length;
+
+	return result;
+}
+
+#endif
@@ -0,0 +1,47 @@
+# Copyright (C) 2012 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+TARGET_DIR := $(LOCAL_DIR)
+
+OPTIONS	+= \
+	DIALOG_D2089=1 \
+	TARGET_BOOT_CPU_VOLTAGE=CHIPID_CPU_VOLTAGE_MED \
+	TARGET_BOOT_RAM_VOLTAGE=0 \
+	TARGET_BOOT_SOC_VOLTAGE=0 \
+	TARGET_HAS_BASEBAND=$(TARGET_HAS_BASEBAND) \
+	TARGET_SPARE0_CLK_CFG=0x83000006 \
+	TARGET_VID0_CLK_CFG=0x81000000 \
+	DISPLAY_LANDSCAPE_IPAD_TUNABLES=1 \
+	TARGET_ENABLE_CM=1 \
+	TARGET_HPD_TO_BL_TIMEOUT=92000 \
+	TARGET_DDR_798M=1 \
+	AMC_NUM_CHANNELS=2 \
+	AMC_NUM_RANKS=1 \
+	TARGET_DWI_FREQUENCY=24000000 \
+	TARGET_DWI_TRANSFER_GAP_US=2.5 \
+	TARGET_ADBE0_VBLANK_POSITION=0xF0000 \
+	BUCK_CPU=0  \
+	BUCK_GPU=1 \
+	WITH_CPU_APSC=1 \
+	BT_DTPATH=\"arm-io/uart1/bluetooth\" \
+	DP_DTPATH=\"arm-io/displayport\" \
+	MULTITOUCH_DTPATH=\"arm-io/spi1/multi-touch\" \
+	WIFI_DTPATH=\"arm-io/usb-complex/usb-ehci1/wlan\" \
+	WITH_TARGET_USB_CONFIG=1
+
+GLOBAL_INCLUDES += $(LOCAL_DIR)/include
+
+ALL_OBJS += $(LOCAL_DIR)/init.o \
+	    $(LOCAL_DIR)/$(PINCONFIG_OBJ)
+
+ifneq ($(PRODUCT),LLB)
+ALL_OBJS += \
+	$(LOCAL_DIR)/properties.o
+endif