first and last commit

platform/defaults/chipid_get_raw_production_mode.c

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+/*
+ * Copyright (C) 2007-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <platform.h>
+#include <platform/chipid.h>
+
+bool chipid_get_raw_production_mode(void)
+{
+	bool current_production_mode = chipid_get_current_production_mode();
+	u_int32_t minimum_epoch = chipid_get_minimum_epoch();
+
+	// Pre-H6 platforms only support a "current" view of fuses.
+	// However, pre-H6 platforms only used epoch greater than 0 for
+	// production fused chips, so we can infer demotion.
+	return current_production_mode || (minimum_epoch > 0);
+}

platform/defaults/formatter.awk

@@ -0,0 +1,37 @@
+# Copyright (C) 2007 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+
+# Format a trivial function
+#
+# Input records are formatted as:
+#
+# $2 : return type
+# $3 : function name
+# $4 : argument list
+# $5 : return value
+#
+# Caller is expected to set FUNCTION and TEMPLATE
+#
+
+BEGIN {
+	FS = "[ \t]*:[ \t]*"
+}
+
+$1=="#" {
+	next
+}
+
+$3==FUNCTION {
+    if ($2 == "void") {
+	cmd = sprintf("sed -e \'s/TYPE/%s/g\' -e \'s/FUNCTION/%s/g\' -e \'s/ARGLIST/%s/g\' -e \'s/RETVAL/%s/g\' -e \'s/RET//g\'  %s", $2, $3, $4, $5, TEMPLATE)
+    } else {
+	cmd = sprintf("sed -e \'s/TYPE/%s/g\' -e \'s/FUNCTION/%s/g\' -e \'s/ARGLIST/%s/g\' -e \'s/RETVAL/%s/g\' -e \'s/RET/return/g\' %s", $2, $3, $4, $5, TEMPLATE)
+    }
+    system(cmd)
+}

platform/defaults/library.mk

@@ -0,0 +1,49 @@
+# Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+#
+# This document is the property of Apple Computer, Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Computer, Inc.
+#
+
+LIBPD_DIR 		:= 	$(GET_LOCAL_DIR)
+LIBPD_BUILD		:=	$(call TOLIBDIR,$(LIBPD_DIR)/LIBPD.a)
+COMMONLIBS		+=	LIBPD
+
+# Only process the remainder of the makefile if we are building libraries
+#
+ifeq ($(MAKEPHASE),libraries)
+
+# Build definitions for the target/platform independent parts of the platform defaults code
+
+SPECIFICATION		:=	$(LIBPD_DIR)/platform.defaults
+TEMPLATE		:=	$(LIBPD_DIR)/template.c
+LISTER			:=	$(LIBPD_DIR)/lister.awk
+FORMATTER		:=	$(LIBPD_DIR)/formatter.awk
+
+PLATFORM_DEFAULTS	:=	$(shell awk -v TAG=INDEP -f $(LISTER) $(SPECIFICATION))
+
+ifneq ($(PLATFORM_DEFAULTS),)
+
+GENERATED_SRC_DIR 	:=	$(call TOLIBOBJDIR,$(LIBPD_DIR))
+GENERATED_NAMES		:=	$(foreach tf,$(PLATFORM_DEFAULTS),$(word 1,$(subst :, ,$(tf))))
+GENERATED_SRCS		:=	$(addprefix $(GENERATED_SRC_DIR)/,$(addsuffix .c,$(GENERATED_NAMES)))
+GENERATED_OBJS		:=	$(addprefix $(GENERATED_SRC_DIR)/,$(addsuffix .o,$(GENERATED_NAMES)))
+
+$(GENERATED_SRCS):	$(SPECIFICATION) $(TEMPLATE) $(LISTER) $(FORMATTER)
+$(GENERATED_SRCS):	func = $(notdir $(@:.c=))
+$(GENERATED_SRCS):
+	@echo GEN  $@
+	@mkdir -p $(dir $@)
+	@awk -v TEMPLATE=$(TEMPLATE) -v FUNCTION=$(func) -f $(FORMATTER) < $(SPECIFICATION) > $@
+
+LIBPD_OBJS		:=	$(GENERATED_OBJS)
+
+$(LIBPD_BUILD):		$(LIBPD_OBJS)
+
+ALL_DEPS		+=	$(LIBPD_OBJS:%o=%d)
+
+endif
+endif

platform/defaults/lister.awk

@@ -0,0 +1,18 @@
+# Copyright (C) 2007 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+
+# Print the function field from lines with tags matching TAG
+
+BEGIN {
+	FS = "[ \t]*:[ \t]*"
+}
+
+$1==TAG {
+	printf("%s ", $3)
+}

platform/defaults/platform.defaults

@@ -0,0 +1,135 @@
+#
+# Copyright (C) 2007-2015 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+#
+# This file describes default implementations of platform functions.
+#
+# Each line comprises five fields, separated by "<whitespace>:<whitespace>"
+#
+# The fields are:
+#
+# <tag> : <return type> : <function name> : <argument list> : <return expression>
+#
+# The tag field indicates whether the function is independent (INDEP) of or dependent (DEP) on the
+# build configuration.  Functions marked INDEP are built into a static library keyed off
+# LIBRARY_TAG; functions marked DEP are built into a static library for every build pass.
+
+# chipid
+INDEP	: bool		: chipid_get_production_mode		: void : false
+INDEP	: bool		: chipid_get_current_production_mode	: void : chipid_get_production_mode()
+INDEP	: void		: chipid_clear_production_mode		: void :
+INDEP	: bool		: chipid_get_secure_mode		: void : false
+INDEP	: u_int32_t	: chipid_get_security_domain		: void : kPlatformSecurityDomainDarwin
+INDEP	: u_int32_t	: chipid_get_minimum_epoch		: void : 0
+INDEP	: u_int32_t	: chipid_get_chip_id			: void : 0
+INDEP	: u_int32_t	: chipid_get_chip_revision 		: void : 0
+INDEP	: u_int64_t	: chipid_get_ecid_id			: void : 0
+INDEP	: u_int64_t	: chipid_get_die_id			: void : 0
+INDEP	: uint32_t	: chipid_get_fuse_revision		: void : 0
+INDEP	: void		: chipid_set_fuse_lock			: bool locked :
+INDEP	: bool		: chipid_get_memory_dqcal		: u_int32_t *cal_data : false
+INDEP	: u_int32_t	: chipid_get_memory_manufacturer	: void : 0
+
+# platform
+INDEP	: bool		: platform_get_current_production_mode	: void : chipid_get_current_production_mode()
+INDEP	: bool		: platform_get_raw_production_mode	: void : chipid_get_raw_production_mode()
+INDEP	: void		: platform_clear_production_mode	: void : chipid_clear_production_mode()
+INDEP	: int		: platform_early_init			: void : 0
+INDEP	: int		: platform_init				: void : 0
+INDEP	: int		: platform_late_init			: void : 0
+INDEP	: int		: platform_debug_init			: void : 0
+INDEP	: int		: platform_init_hwpins			: void : 0
+INDEP	: int		: platform_init_internal_mem		: void : 0
+INDEP	: int		: platform_init_display			: void : 0
+INDEP	: int		: platform_init_display_mem		: addr_t *base, size_t *size : 0
+INDEP	: int		: platform_init_setup_clocks		: void : 0
+INDEP	: int		: platform_init_power			: void : 0
+INDEP	: int		: platform_init_mass_storage		: void : 0
+INDEP	: int		: platform_init_mass_storage_panic	: void : 0
+INDEP	: void		: platform_mmu_setup			: bool resume :
+INDEP	: u_int32_t	: platform_get_boot_config		: void : 0
+INDEP	: u_int32_t	: platform_get_board_id			: void : 0
+INDEP	: u_int32_t	: platform_get_security_domain		: void : chipid_get_security_domain()
+INDEP	: bool		: platform_get_secure_mode		: void : chipid_get_secure_mode()||chipid_get_raw_production_mode()
+INDEP	: bool		: platform_get_core_idle_enable		: void : true
+INDEP	: bool		: platform_get_ecid_image_personalization_required	: void : false
+INDEP	: u_int32_t	: platform_get_hardware_epoch		: void : chipid_get_minimum_epoch()
+INDEP	: u_int64_t	: platform_get_nonce			: void : 0
+INDEP	: u_int32_t	: platform_get_chip_id			: void : chipid_get_chip_id()
+INDEP	: u_int32_t	: platform_get_chip_revision		: void : chipid_get_chip_revision()
+INDEP	: u_int64_t	: platform_get_ecid_id			: void : chipid_get_ecid_id()
+INDEP	: u_int64_t	: platform_get_die_id			: void : chipid_get_die_id()
+INDEP	: u_int32_t	: platform_get_fuse_revision		: void : chipid_get_fuse_revision()
+INDEP	: u_int32_t	: platform_get_entropy			: void : timer_get_entropy()
+INDEP	: u_int16_t	: platform_get_usb_vendor_id		: void : 0x05ac
+INDEP	: void		: platform_set_dfu_status		: bool dfu : 
+INDEP	: bool		: platform_get_force_dfu		: void : false
+INDEP	: bool		: platform_get_request_dfu1		: void : false
+INDEP	: bool		: platform_get_request_dfu2		: void : false
+INDEP	: bool		: platform_get_lock_fuses_required	: void : true
+INDEP	: uint32_t	: platform_get_pcie_link_width		: uint32_t link : 0
+INDEP	: bool		: platform_set_usb_brick_detect		: int select : false
+INDEP	: void		: platform_halt				: void : arch_halt()
+INDEP	: void		: platform_deep_idle			: void : platform_halt()
+INDEP	: int		: platform_quiesce_display		: void : 0
+INDEP	: int		: platform_update_device_tree		: void : 0
+INDEP	: void		: platform_sleep			: void : 
+INDEP	: const char *	: platform_get_usb_manufacturer_string	: void : "Apple Inc."
+INDEP	: u_int16_t	: platform_get_usb_device_version	: void : 0
+INDEP	: int		: platform_init_mainmem			: bool resume : 0
+INDEP	: void		: platform_init_mainmem_map		: void :
+INDEP	: int		: platform_bootprep			: enum boot_target target : 0
+INDEP	: int		: platform_quiesce_hardware		: enum boot_target target : 0
+INDEP	: u_int32_t	: platform_set_performance		: u_int32_t level : kPerformanceHigh
+INDEP	: bool		: platform_provide_spec_blob		: const void *common_name, const size_t common_name_length, const void *serial_number, const size_t serial_number_length, void **spec_blob, size_t *spec_blob_length : false
+INDEP	: void		: platform_watchdog_tickle		: void :
+INDEP	: u_int32_t	: platform_get_base_cpu_voltage		: void : 0
+INDEP	: u_int32_t	: platform_get_base_ram_voltage		: void : 0
+INDEP	: int		: platform_get_cpu_voltages		: u_int32_t count, u_int32_t *voltages : -1
+INDEP	: int		: platform_get_cpu_min_voltages		: u_int32_t count, u_int32_t *voltages : -1
+INDEP	: int		: platform_get_ram_voltages		: u_int32_t count, u_int32_t *voltages : -1
+INDEP	: int		: platform_get_gpu_ram_voltages		: u_int32_t count, u_int32_t *voltages : -1
+INDEP	: int		: platform_convert_voltages		: int buck, u_int32_t count, u_int32_t *voltages : -1
+INDEP	: bool		: platform_is_pre_lpddr4		: void : true
+INDEP	: u_int64_t	: platform_get_memory_size		: void : 0
+INDEP	: void		: platform_set_memory_info		: u_int8_t manuf_id, u_int64_t memory_size :
+INDEP	: u_int8_t	: platform_get_memory_manufacturer_id	: void : 0
+INDEP	: void		: platform_asynchronous_exception	: void :
+INDEP	: void		: platform_adjust_memory_layout		: void : 
+INDEP	: uint64_t	: platform_map_host_to_pci_bus_addr	: uintptr_t addr : addr
+INDEP	: void		: platform_setup_default_environment	: void : target_setup_default_environment()
+INDEP	: void *	: platform_get_boot_trampoline		: void : 0
+INDEP	: size_t 	: platform_get_display_memory_size	: void : 0
+
+# target
+INDEP	: color_policy_t *	: target_color_map_init		: enum colorspace cs, color_policy_t *color_policy : NULL
+INDEP	: void		: target_early_init			: void :
+INDEP	: void		: target_init				: void :
+INDEP	: void		: target_late_init			: void :
+INDEP	: int		: target_debug_init			: void : 0
+INDEP	: void		: target_quiesce_hardware		: void :
+INDEP	: bool		: target_should_poweroff		: bool at_boot : false
+INDEP	: bool		: target_should_recover			: void : false
+INDEP	: void		: target_setup_default_environment	: void :
+INDEP	: int		: target_bootprep			: enum boot_target target : 0
+INDEP	: int		: target_update_device_tree		: void : 0
+INDEP	: void		: target_set_led			: int color : 
+INDEP	: void		: target_watchdog_tickle		: void :
+INDEP	: void		: target_debug				: int code : 
+INDEP	: u_int32_t	: target_lookup_backlight_cal		: int index : 0
+INDEP	: int		: target_dclr_from_clrc			: uint8_t *buffer, size_t size : -1
+INDEP	: u_int8_t	: target_lm3534_gpr			: u_int32_t ctlr : 3
+INDEP	: void * 	: target_get_display_configuration	: void : 0
+
+# application (these really belong somewhere else)
+INDEP	: bool		: env_blacklist				: const char *var, bool write : false
+INDEP	: bool		: env_blacklist_nvram			: const char *var : false
+INDEP	: bool		: security_allow_memory			: const void *address, size_t length : false
+INDEP	: bool		: syscfg_find_tag			: uint32_t tag, void **data, uint32_t *size : false

platform/defaults/platform_get_default_gpio_cfg.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2014-2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <debug.h>
+#include <platform.h>
+#include <target.h>
+#if !WITH_TARGET_CONFIG && WITH_HW_GPIO
+#include <drivers/apple/gpio.h>
+#include <platform/pinconfig.h>
+#endif
+
+const uint32_t* platform_get_default_gpio_cfg(uint32_t gpioc)
+{
+#if WITH_TARGET_CONFIG
+	return target_get_default_gpio_cfg(gpioc);
+#elif WITH_HW_GPIO
+	if (gpioc == 0)
+		return gpio_default_cfg_0;
+#ifdef GPIO_1_GROUP_COUNT
+	if (gpioc == 1)
+		return gpio_default_cfg_0;
+#endif
+	panic("unknown gpio controller %u", gpioc);
+#else
+	panic("no default pinconfig source");
+#endif
+}

platform/defaults/platform_get_memory_region.c

@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2007-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <debug.h>
+#include <platform.h>
+#include <platform/memmap.h>
+
+uintptr_t platform_get_memory_region_base_optional(memory_region_type_t region)
+{
+	uintptr_t base;
+
+	switch (region) {
+		case kMemoryRegion_Panic:
+			base = SDRAM_BASE + platform_get_memory_size() - PANIC_SIZE;
+			break;
+
+#if defined(DISPLAY_BASE)
+		case kMemoryRegion_Display:
+			base = SDRAM_BASE + platform_get_memory_size() - platform_get_memory_region_size(kMemoryRegion_Display) - PANIC_SIZE;
+			break;
+#endif
+
+#if defined(SLEEP_TOKEN_BUFFER_BASE)
+		case kMemoryRegion_SleepToken:
+			base = SLEEP_TOKEN_BUFFER_BASE;
+			break;
+#endif
+
+		case kMemoryRegion_Kernel:
+			base = SDRAM_BASE;
+			break;
+
+		default:
+			base = (uintptr_t)-1;
+	}
+
+	return base;
+}
+
+size_t platform_get_memory_region_size_optional(memory_region_type_t region)
+{
+	size_t size;
+
+	switch (region) {
+		case kMemoryRegion_Panic:
+			size = PANIC_SIZE;
+			break;
+
+#if defined(DISPLAY_SIZE)
+		case kMemoryRegion_Display:
+			size = platform_get_display_memory_size();
+			ASSERT(size != 0);
+			break;
+#endif
+
+#if defined(SLEEP_TOKEN_BUFFER_SIZE)
+		case kMemoryRegion_SleepToken:
+			size = SLEEP_TOKEN_BUFFER_SIZE;
+			break;
+#endif
+
+		case kMemoryRegion_Kernel:
+#if defined(DISPLAY_BASE)
+			size = platform_get_memory_region_base(kMemoryRegion_Display)- platform_get_memory_region_base(kMemoryRegion_Kernel);
+#else
+			size = platform_get_memory_region_base(kMemoryRegion_Panic) - platform_get_memory_region_base(kMemoryRegion_Kernel);
+#endif
+			break;
+
+		default:
+			size = (size_t)-1;
+	}
+
+	return size;
+}

platform/defaults/platform_get_spi_frequency.c

@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#include <debug.h>
+#include <platform.h>
+
+u_int32_t platform_get_spi_frequency(void)
+{
+#if SUPPORT_FPGA
+	return 2500000;
+#else
+	return 12000000;
+#endif
+}
+

platform/defaults/platform_memory_map.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2009-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#include <sys.h>
+#include <platform/memmap.h>
+
+/*
+ * Default platform memory map; takes advantage of common platform
+ * defintions about memory sizes and locations.
+ *
+ * Note that this definition should only be used for simple applications
+ * where memory is all cached and identity-mapped.  More complicated
+ * memory arrangements should be described in platform-specific code,
+ * rather than complicating this table.
+ *
+ * For some platforms/targets, SDRAM_LEN is not constant and so we 
+ * have to compute a maximum via other means.
+ * 
+ */
+#ifndef SDRAM_MAX_LEN
+# ifndef SDRAM_BANK_COUNT
+#  define SDRAM_BANK_COUNT	1
+# endif
+# define SDRAM_MAX_LEN		(SDRAM_BANK_LEN * SDRAM_BANK_COUNT)
+#endif
+
+#ifndef SRAM_MAX_LEN
+# ifndef SRAM_BANK_COUNT
+#  define SRAM_BANK_COUNT	1
+# endif
+# define SRAM_MAX_LEN		(SRAM_BANK_LEN * SRAM_BANK_COUNT)
+#endif
+
+struct mem_static_map_entry mem_static_map_entries[] = {
+        /* cached         uncached        physical        size */
+#ifdef SDRAM_BASE
+        { SDRAM_BASE,     MAP_NO_ENTRY,     SDRAM_BASE,     SDRAM_MAX_LEN },
+#endif
+#ifdef SRAM_BASE
+        { SRAM_BASE,      MAP_NO_ENTRY,     SRAM_BASE,      SRAM_MAX_LEN },
+#endif
+        {MAP_NO_ENTRY, MAP_NO_ENTRY, MAP_NO_ENTRY, 0}
+};

platform/defaults/platform_restore_system.c

@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#include <debug.h>
+#include <drivers/power.h>
+#include <platform/memmap.h>
+#include <sys/boot.h>
+#include <sys/security.h>
+
+int32_t platform_restore_system(void)
+{
+	uint32_t *signature = (uint32_t *)(SLEEP_TOKEN_BUFFER_BASE + kSleepTokenKernelOffset);
+
+	power_will_resume();
+
+	dprintf(DEBUG_INFO, "restore_system: signature[0]: 0x%08x, signature[1]: 0x%08x\n",
+		signature[0], signature[1]);
+
+	if ((signature[0] != 'MOSX') || (signature[1] != 'SUSP')) return -1;
+
+	signature[0] = 0;
+	signature[1] = 0;
+
+	if (!security_validate_sleep_token(SLEEP_TOKEN_BUFFER_BASE + kSleepTokeniBootOffset)) return -1;
+
+	/* Jump to reset vector */
+	dprintf(DEBUG_INFO, "restoring kernel\n");
+	prepare_and_jump(BOOT_DARWIN_RESTORE, NULL, NULL);
+
+	/* shouldn't get here */
+	panic("returned from restore_system\n");
+}

platform/defaults/rules.mk

@@ -0,0 +1,52 @@
+# Copyright (C) 2007-2013 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ifeq ($(IMAGE_FORMAT),img3)
+ALL_OBJS	+= \
+	$(LOCAL_DIR)/chipid_get_raw_production_mode.o
+endif
+
+
+# To avoid having a bunch of little tiny files containing default
+# functions, we auto-generate the trivial ones from a specification.
+#
+# XXX The techniques used here could be generalised to provide
+# default implementations for other subsystems.
+
+# Default functions that are independent of the build configuration
+# are built into a static library shared across builds.
+LIBRARY_MODULES		+=	$(LOCAL_DIR)
+
+#
+# Library sources
+# 
+# Adding files here is very expensive, as each file
+# gets compiled for every target/product/build permutation.
+#
+PLATFORM_DEFAULT_SRCS	:= \
+	$(LOCAL_DIR)/platform_get_default_gpio_cfg.c \
+	$(LOCAL_DIR)/platform_get_memory_region.c \
+	$(LOCAL_DIR)/platform_get_spi_frequency.c \
+	$(LOCAL_DIR)/platform_memory_map.c \
+	$(LOCAL_DIR)/platform_restore_system.c \
+	$(LOCAL_DIR)/target_get_boot_battery_capacity.c \
+	$(LOCAL_DIR)/target_get_precharge_gg_flag_mask.c \
+	$(LOCAL_DIR)/target_get_property.c \
+	$(LOCAL_DIR)/target_get_property_base.c
+
+ALL_DEPS		+=	$(PLATFORM_DEFAULT_SRCS:%c=%d)
+PLATFORM_DEFAULT_OBJS	:=	$(call TOBUILDDIR,$(PLATFORM_DEFAULT_SRCS:%c=%o))
+
+LOCALLIBS		+=	PLATFORM_DEFAULT
+
+PLATFORM_DEFAULT_BUILD	:=	$(call TOBUILDDIR,$(LOCAL_DIR)/PLATFORM_DEFAULT.a)
+
+$(PLATFORM_DEFAULT_BUILD): $(PLATFORM_DEFAULT_OBJS)

platform/defaults/target_get_boot_battery_capacity.c

@@ -0,0 +1,12 @@
+#if WITH_HW_POWER && WITH_TARGET_CONFIG
+#include <limits.h>
+#include <target/powerconfig.h>
+#include <target.h>
+
+#ifdef TARGET_BOOT_BATTERY_CAPACITY
+int target_get_boot_battery_capacity(void)
+{
+	return TARGET_BOOT_BATTERY_CAPACITY;
+}
+#endif
+#endif // WITH_TARGET_CONFIG

platform/defaults/target_get_precharge_gg_flag_mask.c

@@ -0,0 +1,17 @@
+#if WITH_HW_POWER && WITH_TARGET_CONFIG
+#include <limits.h>
+#include <debug.h>
+#include <drivers/gasgauge.h>
+#include <target/powerconfig.h>
+#include <target.h>
+
+int target_get_precharge_gg_flag_mask(void)
+{
+#ifdef TARGET_PRECHARGE_GG_FLAG_MASK
+	return TARGET_PRECHARGE_GG_FLAG_MASK;
+#else
+	return kHDQRegFlagsMaskSOC1;
+#endif
+}
+
+#endif // WITH_TARGET_CONFIG

platform/defaults/target_get_property.c

@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2012-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <target.h>
+
+bool
+target_get_property(enum target_property prop, void *data, int maxdata, int *retlen)
+{
+	return target_get_property_base(prop, data, maxdata, retlen);
+}

platform/defaults/target_get_property_base.c

@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2012-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <debug.h>
+#include <lib/syscfg.h>
+#include <target.h>
+
+static const uint32_t prop_map[TARGET_PROPERTY_MAX] = {
+	[TARGET_PROPERTY_WIFI_MACADDR]                  = 'WMac',
+	[TARGET_PROPERTY_WIFI_CALIBRATION_TX_24]        = 'W24G',
+	[TARGET_PROPERTY_WIFI_CALIBRATION_TX_50]        = 'W50G',
+	[TARGET_PROPERTY_WIFI_CALIBRATION_RX_24]        = 'W24R',
+	[TARGET_PROPERTY_WIFI_CALIBRATION_RX_50]        = 'W50R',
+	[TARGET_PROPERTY_WIFI_CALIBRATION_RX_TEMP]      = 'WRxT',
+	[TARGET_PROPERTY_WIFI_CALIBRATION_FREQ_GROUP_2G]= 'FG2G',
+	[TARGET_PROPERTY_WIFI_WCAL]			= 'WCAL',
+	[TARGET_PROPERTY_WIFI_BOARD_SNUM]               = 'WBSn',
+	[TARGET_PROPERTY_BT_MACADDR]                    = 'BMac',
+	[TARGET_PROPERTY_ETH_MACADDR]                   = 'EMac',
+	[TARGET_PROPERTY_BB_REGION_SKU]                 = 'RSKU',
+	[TARGET_PROPERTY_PINTO_MACADDR]                 = 'MMac',
+	[TARGET_PROPERTY_WIFI1_MACADDR]                 = 'WMc2',
+	[TARGET_PROPERTY_BT1_MACADDR]                   = 'BMc2',
+	[TARGET_PROPERTY_ETH1_MACADDR]                  = 'EMc2',
+	[TARGET_PROPERTY_BLUETOOTH_DEV_MACADDR0]        = 'RMac',
+};
+
+bool
+target_get_property_base(enum target_property prop, void *data, int maxdata, int *retlen)
+{
+	int length = 0; 
+	bool result = false;
+
+	if ((prop < TARGET_PROPERTY_MAX) && (prop_map[prop] != 0)) {
+		length = syscfgCopyDataForTag(prop_map[prop], data, maxdata);
+		result = (length == maxdata);
+	}
+
+	if (retlen != NULL) *retlen = length;
+
+	return result;
+}

platform/defaults/template.c

@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2007-2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+/*
+ * Template for trivial default functions.
+ *
+ * Add header includes here as required; it's not super-efficient but it works.
+ */
+#include <arch.h>
+#include <lib/paint.h>
+#include <platform.h>
+#include <platform/chipid.h>
+#include <platform/timer.h>
+#include <sys/types.h>
+#include <target.h>
+
+TYPE FUNCTION ( ARGLIST )
+{
+	RET RETVAL ;
+}

platform/generic/breadcrumbs.c

@@ -0,0 +1,114 @@
+#include <lib/env.h>
+#include <stdlib.h>
+#include <lib/nvram.h>
+#include <debug.h>
+#include <platform.h>
+#include <arch.h>
+
+
+#define BREADCRUMB_BUFFER_SIZE 256	// This is arbitrarily sized, should be large enough for 
+					// sensible options of key/value
+#define BREADCRUMB_MIN_SIZE    3	// Smallest size of a breadcrumb
+
+typedef struct {
+	char* 		buffer;		// Storage for the breadcrumbs
+	int		buffer_len; 	// Length of breadcrumb buffer
+	int 		wrpos;		// Current write position
+} breadcrumb_store_t;
+
+static bool initialized = false;
+
+breadcrumb_store_t breadcrumb_store;
+
+
+static char* bc_cur_pos (void)
+{
+	ASSERT(breadcrumb_store.wrpos <= breadcrumb_store.buffer_len);
+	return &breadcrumb_store.buffer[breadcrumb_store.wrpos];
+}
+
+static int bc_remaining (void)
+{
+	ASSERT(breadcrumb_store.wrpos <= breadcrumb_store.buffer_len);
+	return breadcrumb_store.buffer_len - breadcrumb_store.wrpos;
+}
+
+void _platform_init_breadcrumbs_internal(void)
+{
+	if (!initialized) {
+		breadcrumb_store.buffer = malloc(BREADCRUMB_BUFFER_SIZE);
+		breadcrumb_store.wrpos = 0;
+		breadcrumb_store.buffer_len = BREADCRUMB_BUFFER_SIZE;
+
+		initialized = (breadcrumb_store.buffer != NULL);
+		dprintf(DEBUG_INFO, "breadcrumb store initialized at %p\n", breadcrumb_store.buffer);
+		platform_record_breadcrumb_marker("BOOT");
+	}
+}
+
+void _platform_record_breadcrumb_internal(const char* key, const char* val)
+{
+	if (initialized && bc_remaining() > BREADCRUMB_MIN_SIZE) {
+		int count = (int)snprintf(bc_cur_pos(), bc_remaining(), "%s=%s, ", key, val);
+
+		if (count > 0)
+			breadcrumb_store.wrpos += strlen(bc_cur_pos());
+	}
+}
+
+void _platform_record_breadcrumb_marker_internal(const char* val)
+{
+	if (initialized && bc_remaining() > BREADCRUMB_MIN_SIZE) {
+		int count = (int)snprintf(bc_cur_pos(), bc_remaining(), "<%s> ", val);
+
+		if (count > 0)
+			breadcrumb_store.wrpos += strlen(bc_cur_pos());
+	}
+}
+
+void _platform_record_breadcrumb_int_internal(const char* key, int val)
+{
+	if (initialized && bc_remaining() > BREADCRUMB_MIN_SIZE) {
+		int count = (int)snprintf(bc_cur_pos(), bc_remaining(), "%s=%d, ", key, val);
+
+		if (count > 0)
+			breadcrumb_store.wrpos += strlen(bc_cur_pos());
+	}
+}
+
+void _platform_commit_breadcrumbs_internal(const char* envvar)
+{
+	if (initialized) {
+		platform_record_breadcrumb_marker("DONE");
+		// We expect this buffer to always be NULL terminated since it was built using
+		// snprintf(), but just to be sure, make sure the end of the buffer is terminated.
+		breadcrumb_store.buffer[breadcrumb_store.buffer_len - 1] = '\0';
+
+		const char* existing_breadcrumbs = env_get(envvar);
+		if (existing_breadcrumbs) {
+			dprintf(DEBUG_INFO, "Existing breadcrumbs found: '%s'\n", existing_breadcrumbs);
+			// If there's already iBoot breadcrumbs, we should preserve them chronologically
+			// (earliest first). Since we need to prepend, we might as well swap it with
+			// a new buffer.
+			if (bc_remaining() < (int)strlen(existing_breadcrumbs)) {
+				// Existing breadcrumbs would not fit. Drop the oldest breadcrumbs first
+				existing_breadcrumbs += ((int)strlen(existing_breadcrumbs) - bc_remaining());
+			}
+			char* tmp_buf = malloc(BREADCRUMB_BUFFER_SIZE);
+			if (tmp_buf) {
+				int count = snprintf(tmp_buf, BREADCRUMB_BUFFER_SIZE, "%s%s", existing_breadcrumbs, breadcrumb_store.buffer);
+				if (count >= 0 && count < BREADCRUMB_BUFFER_SIZE)
+					breadcrumb_store.wrpos = count;
+				else
+					breadcrumb_store.wrpos = 0;
+
+				free(breadcrumb_store.buffer);
+				breadcrumb_store.buffer = tmp_buf;
+			}
+		}
+		dprintf(DEBUG_INFO, "Committing breadcrumbs [used %d of %d bytes]: Setting '%s'='%s'\n", breadcrumb_store.wrpos, breadcrumb_store.buffer_len, envvar, breadcrumb_store.buffer);
+		env_set(envvar, breadcrumb_store.buffer, ENV_PERSISTENT);
+		nvram_save();
+		initialized=false; // Stop recording breadcrumbs and make redundant commits a no-op.
+	}
+}

platform/generic/default_mib.c

@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2008,2014-2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#if !APPLICATION_SECUREROM
+
+#include <lib/mib.h>
+#include <platform.h>
+
+// Default MIB Application/Product
+MIB_CONSTANT_WEAK(kMIBTargetApplicationProduct,		kOIDTypeUInt32,  0);
+
+// Default MIB build configuration constants
+MIB_CONSTANT_WEAK(kMIBTargetWithHwAsp,			kOIDTypeBoolean, false);
+MIB_CONSTANT_WEAK(kMIBTargetWithEffaceable,		kOIDTypeBoolean, false);
+MIB_CONSTANT_WEAK(kMIBTargetWithFileSystem,		kOIDTypeBoolean, false);
+MIB_CONSTANT_WEAK(kMIBTargetWithHwFlashNand,		kOIDTypeBoolean, false);
+MIB_CONSTANT_WEAK(kMIBTargetWithHwFlashNor,		kOIDTypeBoolean, false);
+MIB_CONSTANT_WEAK(kMIBTargetWithHwNvme,			kOIDTypeBoolean, false);
+MIB_CONSTANT_WEAK(kMIBTargetWithLegacyPanicLogs,	kOIDTypeBoolean, false);
+
+// Default MIB target paint constants
+MIB_CONSTANT_WEAK(kMIBTargetDisplayGammaTableCount,	kOIDTypeUInt32, 0);
+MIB_CONSTANT_PTR_WEAK(kMIBTargetDisplayGammaTablePtr,	kOIDTypeStruct, NULL);
+MIB_CONSTANT_WEAK(kMIBTargetPanicOnUnknownDclrVersion,	kOIDTypeBoolean, true);
+MIB_CONSTANT_WEAK(kMIBTargetPictureScale,		kOIDTypeUInt32, 1);
+
+// Default MIB NOR configuration
+MIB_CONSTANT_WEAK(kMIBTargetNvramNorBankCount,		kOIDTypeUInt32,	2);
+MIB_CONSTANT_WEAK(kMIBTargetNvramNorBankSize,		kOIDTypeSize,	0x2000);
+MIB_CONSTANT_WEAK(kMIBTargetNvramNorOffset,		kOIDTypeInt32, -(2 * 0x2000));
+
+// Default MIB Image3 constants
+// Delete this and it's definition in mib.base when all Image3 targets are deprecated.
+MIB_CONSTANT_WEAK(kMIBTargetAcceptGlobalTicket,		kOIDTypeBoolean, false);
+
+//Default Color Manager Data
+MIB_CONSTANT_WEAK(kMIBTargetDisplayCMEngammaTablePtr,	kOIDTypeStruct, NULL);
+MIB_CONSTANT_WEAK(kMIBTargetDisplayCMEngammaTableCount,	kOIDTypeUInt32, 0);
+MIB_CONSTANT_WEAK(kMIBTargetDisplayCMDegammaTablePtr,	kOIDTypeStruct, NULL);
+MIB_CONSTANT_WEAK(kMIBTargetDisplayCMDegammaTableCount,	kOIDTypeUInt32, 0);
+MIB_CONSTANT_WEAK(kMIBTargetDisplayCMMatrixTablePtr,	kOIDTypeStruct, NULL);
+MIB_CONSTANT_WEAK(kMIBTargetDisplayCMMatrixTableCount,	kOIDTypeUInt32, 0);
+
+#endif	// !APPLICATION_SECUREROM
+

platform/generic/defaults.c

@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2007-2008 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+/* XXX keep this here but blank for now */

platform/generic/library.mk

@@ -0,0 +1,36 @@
+# Copyright (C) 2007 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+
+LIBPGINDEP_DIR	:=	$(GET_LOCAL_DIR)
+LIBPGINDEP_BUILD:=	$(call TOLIBDIR,$(LIBPGINDEP_DIR)/LIBPGINDEP.a)
+COMMONLIBS	+=	LIBPGINDEP
+
+# Force this library's symbols to be imported so that they can't be
+# overridden. This library isn't designed with one function per object file
+# to allow selective overriding
+GLOBAL_LDFORCELIBS	+=	$(LIBPGINDEP_BUILD)
+
+# Only process the remainder of the makefile if we are building libraries
+#
+ifeq ($(MAKEPHASE),libraries)
+
+LIBPGINDEP_OBJS	:= \
+	$(LIBPGINDEP_DIR)/platform_indep.o \
+	$(LIBPGINDEP_DIR)/target_indep.o \
+	$(LIBPGINDEP_DIR)/target_pass_boot_manifest.o \
+	$(LIBPGINDEP_DIR)/breadcrumbs.o
+
+LIBPGINDEP_OBJS	:=	$(call TOLIBOBJDIR,$(LIBPGINDEP_OBJS))
+
+$(LIBPGINDEP_BUILD):	$(LIBPGINDEP_OBJS)
+
+ALL_DEPS	+=	$(LIBPGINDEP_OBJS:%o=%d)
+
+endif

platform/generic/platform_dep.c

@@ -0,0 +1,402 @@
+/*
+ * Copyright (C) 2007-2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <arch.h>
+#include <debug.h>
+#include <drivers/aes.h>
+#include <drivers/power.h>
+#if WITH_HW_SEP
+#include <drivers/sep/sep_client.h>
+#endif
+#if WITH_EFFACEABLE
+#include <lib/effaceable.h>
+#endif
+#include <lib/image.h>
+#include <lib/libc.h>
+#include <lib/nonce.h>
+#include <lib/random.h>
+#include <lib/syscfg.h>
+#include <platform.h>
+#include <platform/chipid.h>
+#include <platform/memmap.h>
+#include <target.h>
+#include <sys.h>
+#include <sys/boot.h>
+#include <sys/hash.h>
+#include <sys/security.h>
+#include <drivers/display.h>
+
+// platfom_dep holds generic functions that are just defined once for all
+// platforms, and are expected to be rebuilt for every target/product
+
+
+#if !PLATFORM_VARIANT_IOP && !PLATFORM_VARIANT_AUDIO
+#if (defined(__arm__) || defined(__arm64__))
+# include <arch/arm/arm.h>
+
+/*
+ * Default implementation of platform_cache_operation(), assumes the ARM architecture
+ * supplied functions are available and appropriate.
+ */
+void platform_cache_operation(int operation, void *address, u_int32_t length)
+{
+	uintptr_t	start, end;
+	void		(*func)(addr_t addr);
+
+	/* all we are willing to do in the panic case is clean the entire cache */
+	if (unlikely(operation & CACHE_PANIC)) {
+		if ((operation & CACHE_CLEAN) && (NULL == address) && (0 == length))
+			arm_clean_dcache();
+		return;
+	}
+	
+	/* disable interrupts as we don't want to be re-entered */
+	enter_critical_section();
+
+	if ((0 == address) && (0 == length)) {
+		
+		/* invalidating the entire cache guarantees a crash */
+		ASSERT((operation & (CACHE_CLEAN | CACHE_INVALIDATE)) != CACHE_INVALIDATE);
+		
+		/* whole-cache operations */
+		switch(operation & (CACHE_CLEAN | CACHE_INVALIDATE)) {
+		case CACHE_CLEAN:
+			arm_clean_dcache();
+			break;
+
+		case CACHE_CLEAN | CACHE_INVALIDATE:
+			arm_clean_invalidate_dcache();
+			break;
+		}
+	} else {
+
+		/* ranged operations by line */
+		start = (uintptr_t)address;
+		end = start + length;
+		switch (operation & (CACHE_CLEAN | CACHE_INVALIDATE)) {
+		case CACHE_INVALIDATE:
+			/*
+			 * Non-aligned range invalidate operations are illegal
+			 * as we may shoot something else sharing the line.
+			 */
+			ASSERT(0 == (start % CPU_CACHELINE_SIZE));
+			ASSERT(0 == (length % CPU_CACHELINE_SIZE));
+
+			/* invalidate */
+			func = arm_invalidate_dcache_line;
+			break;
+
+		case CACHE_CLEAN:
+			/* adjust start to the base of the cacheline */
+			start &= ~(CPU_CACHELINE_SIZE - 1);
+			func = arm_clean_dcache_line;
+			break;
+
+		case CACHE_CLEAN | CACHE_INVALIDATE:
+			/* adjust start to the base of the cacheline */
+			start &= ~(CPU_CACHELINE_SIZE - 1);
+			func = arm_clean_invalidate_dcache_line;
+			break;
+		default:
+			func = NULL;
+		}
+		/* do it */
+		if (likely(NULL != func))
+			for (; start < end; start += CPU_CACHELINE_SIZE) 
+				func(start);
+	}
+
+	/* write buffer is address-agnostic */
+	if (operation & CACHE_DRAIN_WRITE_BUFFER)
+		arm_drain_write_buffer();
+
+#if defined(__arm64__)
+	arm_memory_barrier();
+#endif
+
+	exit_critical_section();
+}
+
+void platform_memory_barrier(void)
+{
+	arm_memory_barrier();
+}
+
+#else
+# error no architecture support for platform_cache_operation
+#endif /* ARCH_ARM */
+#endif // PLATFORM_VARIANT_IOP
+
+
+//	iBoot Flags
+//		Bit 0 - Restore host should send image capable of restore boot (a.k.a. iBEC).
+//		Bit 1 - Restore host should send ticket to validate images
+//		Bit 2 - Restore host should send Image4 images.
+//		Bit 3 - Current status of Secure fuse bit
+//		Bit 4 - Current status of Production fuse bit
+//		Bit 5 - Restore host should send images with SHA2-384 hash
+
+uint32_t platform_get_iboot_flags(void)
+{
+	u_int32_t flag_summary = 0;
+
+#if WITH_RESTORE_STRAP
+	flag_summary |= (1 << 0);
+#endif
+
+#if WITH_TICKET
+	flag_summary |= (1 << 1);
+#endif
+
+#if WITH_IMAGE4
+	flag_summary |= (1 << 2);
+#endif
+
+	if (platform_get_secure_mode()) flag_summary |= (1 << 3);
+
+	if (platform_get_current_production_mode()) flag_summary |= (1 << 4);
+
+#if WITH_SHA2_384
+	flag_summary |= (1 << 5);
+#endif
+
+	return flag_summary;
+}
+
+#ifndef PLATFORM_PRODUCT_ID
+#define PLATFORM_PRODUCT_ID {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}
+#endif
+
+const char* platform_get_product_id(void)
+{
+	static const char product_id[] = PLATFORM_PRODUCT_ID;
+	return product_id;
+}
+
+u_int32_t platform_get_security_epoch(void)
+{
+#if WITH_IMAGE4
+	return chipid_get_minimum_epoch();
+#else
+	u_int32_t build_epoch = PLATFORM_SECURITY_EPOCH;
+	u_int32_t minimum_epoch = chipid_get_minimum_epoch();
+
+	if (minimum_epoch < build_epoch) minimum_epoch = build_epoch;
+
+	return minimum_epoch;
+#endif	
+}
+
+#ifndef DEFAULT_RECOVERY_MODE_PRODUCT_ID
+#define DEFAULT_RECOVERY_MODE_PRODUCT_ID 0x1281
+#endif
+
+/*
+ *  platform_get_usb_product_id() - returns the usb product
+ *
+ *
+ */
+uint16_t platform_get_usb_product_id(void)
+{
+#if WITH_RECOVERY_MODE
+	return DEFAULT_RECOVERY_MODE_PRODUCT_ID;
+#else
+	return 0x1226 + (platform_get_security_domain() & 3);
+#endif
+}
+
+const char *platform_get_usb_product_string(void)
+{
+#if WITH_RECOVERY_MODE
+	return "Apple Mobile Device (Recovery Mode)";
+#else
+	return "Apple Mobile Device (DFU Mode)";
+#endif
+}
+
+// gUSBSerialNumber Format: "CPID:xxxx CPRV:xx CPFM:xx SCEP:xx BDID:xx ECID:xxxxxxxxxxxxxxxx IBFL:xx"
+// optionally includes " SRTG:[<str24>]"
+// optionally includes " SRNM:[xxxxxxxxxxxxxxxx]"
+static char gUSBSerialNumber[127];
+//					Size		iBoot		SecureROM
+//	CPID	      (5 + 4)		9		9		9
+//	CPRV	+ 1 + (5 + 2)		8		17		17
+//	CPFM	+ 1 + (5 + 2)		8		25		25
+//	SCEP	+ 1 + (5 + 2)		8		33		33
+//	BDID	+ 1 + (5 + 2)		8		41		41
+//	ECID	+ 1 + (5 + 16)		22		63		63
+//	IBFL	+ 1 + (5 + 2)		8		71		71
+//	SRTG	+ 1 + (5 + 2 + 24)	32				103
+//	SRNM	+ 1 + (5 + 2 + 16)	24		95
+//	nul	+ 1     		1 		96		104
+
+static u_int32_t gUSBSerialNumberStatus;
+
+const char *platform_get_usb_serial_number_string(bool full)
+{
+	char		srnm_buf[1 + (5 + 2 + 16) + 1];
+	char		imei_buf[1 + (5 + 2 + 16) + 1];
+	char		srtg_buf[1 + (5 + 2 + 24) + 1];
+	int		srnm_size = 0, imei_size = 0;
+
+	// Return if the request string has already been generated
+	if (gUSBSerialNumberStatus > 1) return gUSBSerialNumber;
+	if (!full && (gUSBSerialNumberStatus > 0)) return gUSBSerialNumber;
+
+	// Set the status based on the requested string
+	gUSBSerialNumberStatus = full ? 2 : 1;
+
+	srtg_buf[0] = '\0';
+	srnm_buf[srnm_size] = '\0';
+	imei_buf[imei_size] = '\0';
+
+	snprintf(gUSBSerialNumber, sizeof(gUSBSerialNumber),
+		 "CPID:%04X CPRV:%02X CPFM:%02X SCEP:%02X BDID:%02X ECID:%016llX IBFL:%02X",
+		 platform_get_chip_id(), platform_get_chip_revision(), platform_get_fuse_modes(),
+		 platform_get_security_epoch(), platform_get_board_id(), platform_get_ecid_id(),
+		 platform_get_iboot_flags());
+
+#if APPLICATION_SECUREROM
+	snprintf(srtg_buf, sizeof(srtg_buf), " SRTG:[%s]", build_tag_string);
+	strlcat(gUSBSerialNumber, srtg_buf, sizeof(gUSBSerialNumber));
+#endif
+
+#if WITH_SYSCFG
+	strlcpy(srnm_buf, " SRNM:[", sizeof(srnm_buf));
+	srnm_size = syscfgCopyDataForTag('SrNm', (u_int8_t *)(srnm_buf + 7), 16);
+	if (srnm_size > 0) {
+		srnm_buf[7 + srnm_size] = '\0';
+		strlcat(srnm_buf, "]", sizeof(srnm_buf));
+		strlcat(gUSBSerialNumber, srnm_buf, sizeof(gUSBSerialNumber));
+	}
+#endif
+
+	return gUSBSerialNumber;
+}
+
+// gUSBMoreOther Format: ""
+// optionally includes " NONC:xxxxxxxxxxxxxxxx"
+// optionally includes " SNON:xxxxxxxxxxxxxxxx"
+static char gUSBMoreOther[127];
+// SHA1:
+//					Size
+//	NONC	+ 1 + (5 + (2*20))	 46
+//	SNON	+ 1 + (5 + (2*20))	 46
+//	Total				 92
+//
+// SHA2-384:
+//					Size
+//	NONC	+ 1 + (5 + (2*32))	 70
+//	SNON	+ 1 + (5 + (2*20))	 46
+//	Total				116
+
+static u_int32_t gUSBMoreOtherStatus;
+
+const char *platform_get_usb_more_other_string(bool full)
+{
+	u_int64_t	nonc;
+	u_int8_t	nonc_hash[HASH_OUTPUT_SIZE];
+	char		nonc_buf[1 + (5 + (2 * NONCE_HASH_OUTPUT_SIZE)) + 1];
+	u_int8_t	i;
+
+	// Return if the request string has already been generated
+	if (gUSBMoreOtherStatus > 1) return gUSBMoreOther;
+	if (!full && (gUSBMoreOtherStatus > 0)) return gUSBMoreOther;
+
+	// Set the status based on the requested string
+	gUSBMoreOtherStatus = full ? 2 : 1;
+
+	nonc_buf[0] = '\0';
+
+	gUSBMoreOther[0] = '\0';
+
+	if (full) {
+		nonc = platform_get_nonce();
+		hash_calculate((const void *)&nonc, sizeof(nonc), (void *)nonc_hash, sizeof(nonc_hash));
+
+		strlcpy(nonc_buf, " NONC:", sizeof(nonc_buf));
+		for(i = 0; (i < NONCE_HASH_OUTPUT_SIZE) && (i < HASH_OUTPUT_SIZE); i++)
+			snprintf((nonc_buf + 1 + 5 + (i * 2)), (sizeof(nonc_buf) - 1 - 5 - (i * 2)), "%02X", nonc_hash[i]);
+		strlcat(gUSBMoreOther, nonc_buf, sizeof(gUSBMoreOther));
+
+#if WITH_HW_SEP
+		u_int8_t snon[SEP_NONCE_SIZE];
+		if (platform_get_sep_nonce(snon) == 0) {
+
+			bzero(nonc_buf, sizeof(nonc_buf));
+			strlcpy(nonc_buf, " SNON:", sizeof(nonc_buf));
+			for(i = 0; (i < SEP_NONCE_SIZE); i++)
+				snprintf((nonc_buf + 1 + 5 + (i * 2)), (sizeof(nonc_buf) - 1 - 5 - (i * 2)), "%02X", snon[i]);
+			strlcat(gUSBMoreOther, nonc_buf, sizeof(gUSBMoreOther));
+		}
+#endif
+	}
+
+	// dprintf(DEBUG_INFO, "%s, len=%ld\n", gUSBMoreOther, strlen(gUSBMoreOther));
+
+	return gUSBMoreOther;
+}
+
+u_int64_t platform_consume_nonce(void)
+{
+	uint64_t	nonce = 0;
+	const char*	how = NULL;
+
+#if WITH_EFFACEABLE
+	if (effaceable_consume_nonce(&nonce)) {
+		how = "effaced";
+	}
+#elif WITH_NVRAM && WITH_ENV
+	if (mobile_ap_nonce_consume_nonce(&nonce)) {
+		how = "consumed";
+	}
+#endif
+
+#if WITH_RANDOM
+	if (!how) {
+		uint8_t	*nonce_bytes = (uint8_t *)&nonce;
+		int result = random_get_bytes(nonce_bytes, sizeof(nonce));
+		RELEASE_ASSERT(result == 0);
+		if (result == 0) {
+			how = "generated";
+		}
+	}
+#endif
+
+	if (!how) {
+		nonce = 0;
+		how = "zeroed";
+	}
+
+#if DEBUG_BUILD
+	dprintf(DEBUG_INFO, "boot-nonce (%s): 0x%016llX\n", how, nonce);
+#endif
+
+	return nonce;
+}
+
+size_t platform_get_display_memory_size(void)
+{
+	size_t size = 0;
+
+	struct display_info info;
+
+	memset(&info, 0, sizeof(info));
+	display_get_info(&info);
+
+	if ((addr_t)info.framebuffer != 0)
+		size = (uintptr_t)PANIC_BASE - (uintptr_t)info.framebuffer;
+#ifdef PURPLE_GFX_MEMORY_LEN
+	if (size < PURPLE_GFX_MEMORY_LEN)
+		size = PURPLE_GFX_MEMORY_LEN;
+#endif
+	
+	return (size);
+}

platform/generic/platform_indep.c

@@ -0,0 +1,347 @@
+/*
+ * Copyright (C) 2014-2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#include <arch.h>
+#include <debug.h>
+#include <drivers/dram.h>
+#include <lib/libc.h>
+#include <platform.h>
+#include <platform/tunables.h>
+#include <stdint.h>
+
+// platfom_indep holds generic functions that are just defined once for all
+// platforms, and are not expected to be rebuilt for every target/product.
+//
+// These functions can vary per BUILD, and per architecture, but not per
+// PLATFORM, TARGET, PRODUCT, or CONFIG
+
+void platform_not_supported(void)
+{
+	dprintf(DEBUG_CRITICAL, "\n");
+	dprintf(DEBUG_CRITICAL, "\n");
+	dprintf(DEBUG_CRITICAL, "\n");
+	dprintf(DEBUG_CRITICAL, "**************************************\n");
+	dprintf(DEBUG_CRITICAL, "*                                    *\n");
+	dprintf(DEBUG_CRITICAL, "*     This unit is not supported     *\n");
+	dprintf(DEBUG_CRITICAL, "*                                    *\n");
+	dprintf(DEBUG_CRITICAL, "**************************************\n");
+	while (1);
+}
+
+//	Fuse Modes
+//		Bit 0 - Chip is Secure
+//		Bit 1 - Chip is Production
+
+uint32_t platform_get_fuse_modes(void)
+{
+	u_int32_t fuse_summary = 0;
+
+	if (platform_get_secure_mode()) fuse_summary |= (1 << 0);
+
+	if (platform_get_raw_production_mode()) fuse_summary |= (1 << 1);
+
+	return fuse_summary;
+}
+
+const char *platform_get_memory_manufacturer_string(void)
+{
+	uint8_t index;
+
+	// This list is based of JEDEC Vendor list in dram.h 
+	// index 0 and 15 are reserverd, we are using them to provide additional information related to the system.
+	static const char *memory_manufacturer_strings[JEDEC_NUM_MANUF_IDS] = {
+		"Unknown",
+		"Samsung",
+		"Qimonda",
+		"Elpida",
+		"Etron",
+		"Nanya",
+		"Hynix",
+		"Mosel",
+		"Winbond",
+		"ESMT",
+		"Reserved",
+		"Spansion",
+		"SST",
+		"ZMOS",
+		"Intel",
+		"Numonyx",
+		"Micron",
+		"FPGA",
+	};
+	
+	index = platform_get_memory_manufacturer_id();
+	
+	if(platform_is_pre_lpddr4()) {
+	
+		if (index >= JEDEC_NUM_MANUF_IDS)
+			return NULL;
+
+		return memory_manufacturer_strings[index];
+	} else {
+		switch(index) {
+			case JEDEC_LPDDR4_MANUF_ID_SAMSUNG:
+				return "Samsung";
+				break;
+		
+			case JEDEC_LPDDR4_MANUF_ID_HYNIX:
+				return "Hynix";
+				break;
+				
+			case JEDEC_LPDDR4_MANUF_ID_MICRON:
+				return "Micron";
+				break;
+			
+			default:
+				return NULL;
+				break;
+		}
+	}
+}
+
+
+uintptr_t platform_get_memory_region_base(memory_region_type_t region)
+{
+	uintptr_t base = platform_get_memory_region_base_optional(region);
+	if (base == (uintptr_t)-1)
+		panic("unsupported region %d base requested\n", (int)region);
+
+	return base;
+}
+
+size_t platform_get_memory_region_size(memory_region_type_t region)
+{
+	size_t size = platform_get_memory_region_size_optional(region);
+
+	if (size == (size_t)-1)
+		panic("unsupported region %d size requested\n", region);
+
+	return size;
+}
+
+void platform_apply_tunables(const struct tunable_chip_struct *tunable_chips, uint32_t num_tunable_chips, const char* type)
+{
+	const struct tunable_struct *tunable;
+	uintptr_t base_address;
+	uint32_t chip_rev = platform_get_chip_revision();
+	uint32_t i;
+	uint32_t t;
+	bool match = false;
+
+	if (num_tunable_chips == 0)
+		return;
+
+	ASSERT(tunable_chips != NULL);
+
+	// For each bucket of tunable values...
+	for (i = 0; i < num_tunable_chips; i++) {
+
+		// Tunable for a newer chip revision?
+		if (tunable_chips[i].chip_rev > chip_rev) {
+			continue;
+		}
+
+		// Tunable for an older chip revision?
+		if (tunable_chips[i].chip_rev < chip_rev) {
+
+			if (match) {
+				// We've already found all the tunables matching
+				// this chip revision -- we're done.
+				break;
+			} else {
+				// We haven't found a match yet. Because the tunable
+				// chip table is supposed to be sorted from highest
+				// to lowest, finding an older chip revision means
+				// that there is no entry in the table for this
+				// chip revision and we'll use the first older one
+				// we find.
+				dprintf(DEBUG_SPEW, "%s tunables for chip rev %d not found -- using tunables for chip rev %d\n",
+					type, chip_rev, tunable_chips[i].chip_rev);
+				chip_rev = tunable_chips[i].chip_rev;
+			}
+		}
+
+		// We've found a matching tunable chip revision (either an exact
+		// match or the next older chip revision).
+		match = true;
+
+		// Get the base address and pointer to the tunables data.
+		tunable = tunable_chips[i].tunable;
+		ASSERT(tunable != NULL);
+		base_address = tunable_chips[i].base_address;
+
+		// For each tunable in registers at this base address...
+		for (t = 0; tunable[t].offset != -1; t++) {
+
+			// Elided tunables have a size of zero, just skip them.
+			if (tunable[t].size == 0) {
+				continue;
+			}
+
+			switch (tunable[t].size) {
+				case sizeof(uint32_t):
+				{
+					volatile uint32_t *addr;
+					uint32_t new_reg, old_reg, mask, value;
+
+					// Get the address of the register.
+					addr = (volatile uint32_t *)(base_address + tunable[t].offset);
+
+					// Get the current value of the register.
+					old_reg = *addr;
+					mask  = (uint32_t)tunable[t].mask;
+					value = (uint32_t)tunable[t].value;
+
+					// If the tunable needs to be applied, do it.
+					if ((old_reg & mask) != (value & mask)) {
+						new_reg = old_reg;
+						new_reg &= ~mask;
+						new_reg |= value & mask;
+						*addr = new_reg;
+						dprintf(DEBUG_SPEW, "%s tunable addr/mask/value=%p/0x%08x/0x%08x: 0x%08x -> 0x%08x\n",
+							type, addr, mask, value, old_reg, new_reg);
+					} else {
+						dprintf(DEBUG_SPEW, "%s tunable addr/mask/value=%p/0x%08x/0x%08x: already correct 0x%08x\n",
+							type, addr, mask, value, old_reg);
+					}
+					break;
+				}
+
+				case sizeof(uint64_t):
+				{
+					volatile uint64_t *addr;
+					uint64_t new_reg, old_reg, mask, value;
+
+					// Get the address of the register.
+					addr = (volatile uint64_t *)(base_address + tunable[t].offset);
+
+					// Get the current value of the register.
+					old_reg = *addr;
+					mask  = tunable[t].mask;
+					value = tunable[t].value;
+
+					// If the tunable needs to be applied, do it.
+					if ((old_reg & mask) != (value & mask)) {
+						new_reg = old_reg;
+						new_reg &= ~mask;
+						new_reg |= value & mask;
+						*addr = new_reg;
+						dprintf(DEBUG_SPEW, "%s tunable addr/mask/value=%p/0x%016llx/0x%016llx: 0x%016llx -> 0x%016llx\n",
+							type, addr, mask, value, old_reg, new_reg);
+					} else {
+						dprintf(DEBUG_SPEW, "%s tunable addr/mask/value=%p/0x%016llx/0x%016llx: already correct 0x%016llx\n",
+							type, addr, mask, value, old_reg);
+					}
+					break;
+				}
+
+				default:
+					panic("Unsupported tunable register size");
+			}
+		}
+	}
+}
+
+uint8_t *platform_apply_dt_tunables(const struct tunable_chip_struct *tunable_chips,
+					uint32_t num_tunable_chips, uint8_t *buffer,
+					uintptr_t dt_base, const char *type)
+{
+	const struct tunable_struct *tunable;
+	struct tunable_struct_unpacked tunable_data;
+	uintptr_t addr;
+	uintptr_t base_address;
+	uint32_t chip_rev = platform_get_chip_revision();
+	uint32_t i;
+	uint32_t t;
+	bool match = false;
+
+	if (num_tunable_chips == 0)
+		return buffer;
+
+	ASSERT((tunable_chips != NULL) && (buffer != NULL));
+
+	// For each bucket of tunable values...
+	for (i = 0; i < num_tunable_chips; i++) {
+
+		// Tunable for a newer chip revision?
+		if (tunable_chips[i].chip_rev > chip_rev) {
+			continue;
+		}
+
+		// Tunable for an older chip revision?
+		if (tunable_chips[i].chip_rev < chip_rev) {
+
+			if (match) {
+				// We've already found all the tunables matching
+				// this chip revision -- we're done.
+				break;
+			} else {
+				// We haven't found a match yet. Because the tunable
+				// chip table is supposed to be sorted from highest
+				// to lowest, finding an older chip revision means
+				// that there is no entry in the table for this
+				// chip revision and we'll use the first older one
+				// we find.
+				dprintf(DEBUG_SPEW, "%s tunables for chip rev %d not found -- using tunables for chip rev %d\n",
+					type, chip_rev, tunable_chips[i].chip_rev);
+				chip_rev = tunable_chips[i].chip_rev;
+			}
+		}
+
+		// We've found a matching tunable chip revision (either an exact
+		// match or the next older chip revision).
+		match = true;
+
+		// Copy the tunable value and get the base address of the block it pertains to.
+		tunable = tunable_chips[i].tunable;
+		ASSERT(tunable != NULL);
+		base_address = tunable_chips[i].base_address;
+
+		// For each tunable register at this base address...
+		for (t = 0; tunable[t].offset != -1; t++) {
+
+			// Elided tunables have a size of zero, but pass them
+			// through in case the driver wants to un-elide them.
+
+			// Copy the tunable data so we can update it.
+			tunable_data.offset = tunable[t].offset;
+			tunable_data.size = tunable[t].size;
+			tunable_data.mask = tunable[t].mask;
+			tunable_data.value = tunable[t].value;
+
+			addr = base_address + tunable_data.offset;
+
+			// Get the address of the register.
+			if (dt_base != 0) {
+				// Adjust the offset to match the reg property in the
+				// device tree.
+				tunable_data.offset = (uint32_t)addr - dt_base;
+				ASSERT(tunable_data.offset != -1);
+			}
+
+			if (tunable_data.size == -1) {
+				dprintf(DEBUG_SPEW, "%s DT tunable @ 0x%lx: offset=0x%08x, size=%d, mask=0x%16llx, value=0x%16llx\n",
+					type, addr,
+					tunable_data.offset, tunable_data.size,
+					tunable_data.mask, tunable_data.value);
+			} else {
+				dprintf(DEBUG_SPEW, "%s DT tunable @ 0x%lx: offset=0x%08x, size=%d, mask=0x%08llx, value=0x%08llx\n",
+					type, addr,
+					tunable_data.offset, tunable_data.size,
+					tunable_data.mask, tunable_data.value);
+			}
+			memcpy(buffer, &tunable_data, sizeof(tunable_data));
+			buffer += sizeof(tunable_data);
+		}
+	}
+	return buffer;
+}
+

platform/generic/platform_info.S

@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#include <platform/memmap.h>
+
+/*
+ * Utility file exporting symbols at absolute locations.  These
+ * values are largely useful to the build system before the final
+ * object is linked, or for diagnosis purposes later.
+ */
+
+	/*
+	 * symbol <name> <value>
+	 */
+	.macro	symbol
+	.global $0
+	.set $0 , $1
+	.endmacro
+
+	/* This is used at link time */
+	symbol	_TEXT_BASE,			TEXT_BASE
+
+#if 0
+	/* debug/sanity checks */
+	symbol	_INSECURE_MEMORY_BASE,		INSECURE_MEMORY_BASE
+	symbol	_INSECURE_MEMORY_SIZE,		INSECURE_MEMORY_SIZE
+	symbol	_DEFAULT_KERNEL_ADDRESS,	DEFAULT_KERNEL_ADDRESS
+	symbol	_DEFAULT_KERNEL_SIZE,		DEFAULT_KERNEL_SIZE
+	symbol	_DEFAULT_RAMDISK_ADDRESS,	DEFAULT_RAMDISK_ADDRESS
+	symbol	_DEFAULT_RAMDISK_SIZE,		DEFAULT_RAMDISK_SIZE
+	symbol	_DEFAULT_DEVICETREE_ADDRESS,	DEFAULT_DEVICETREE_ADDRESS
+	symbol	_DEFAULT_DEVICETREE_SIZE,	DEFAULT_DEVICETREE_SIZE
+	
+	symbol	_IBOOT_SIZE,			IBOOT_SIZE
+	symbol	_MMU_TT_BASE,			MMU_TT_BASE
+	symbol	_MMU_TT_SIZE,			MMU_TT_SIZE
+	symbol	_STACK_BASE,			STACK_BASE
+	symbol	_STACK_SIZE,			STACK_SIZE
+#endif

platform/generic/pmgr/pmgr_binning.c

@@ -0,0 +1,294 @@
+/*
+ * Copyright (C) 2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#include <platform.h>
+#include <platform/pmgr.h>
+#include <debug.h>
+
+static uint64_t pmgr_binning_read_register(uint64_t address, uint32_t low, uint32_t high, bool reg64)
+{
+	uint64_t result = 0;
+	do {
+		uint64_t current_low;
+		uint64_t offset;
+		uint64_t register_value;
+
+		if (reg64) {
+			offset = high/64;
+			current_low = offset * 64;
+			register_value = ((uint64_t *)(address))[offset];
+		} else {
+			offset = high/32;
+			current_low = offset * 32;
+			register_value = ((uint32_t *)(address))[offset];
+		}
+
+		// Mask useful bit : [current_low:high]
+		register_value &= (1ULL << (high - current_low + 1)) - 1;
+
+		if (current_low <= low) {
+			result |= register_value >> (low - current_low);
+			break;
+		}
+
+		result |= register_value << (current_low - low);
+		high = current_low - 1;
+	} while (1);
+
+	return result;
+}
+
+static uint64_t pmgr_binning_read(const struct pmgr_binning_fuse_to_register *fuse_to_register, uint32_t binning_low, uint32_t binning_high)
+{
+	uint32_t result = 0;
+	while (1) {
+		uint32_t i = 0;
+		while (fuse_to_register[i].register_address != 0) {
+			if ((fuse_to_register[i].binning_high >= binning_high) && (fuse_to_register[i].binning_low <= binning_high)) {
+				break;
+			}
+			i++;
+		}
+		if (fuse_to_register[i].register_address == 0) {
+			return PMGR_BINNING_NOTFOUND;
+		}
+
+		if ((fuse_to_register[i].binning_high >= binning_high) && (fuse_to_register[i].binning_low <= binning_low)) {
+			result |= pmgr_binning_read_register(fuse_to_register[i].register_address,
+													binning_low - fuse_to_register[i].binning_low + fuse_to_register[i].register_low,
+													binning_high - fuse_to_register[i].binning_low + fuse_to_register[i].register_low,
+													fuse_to_register[i].register_64bit);
+			break;
+		}
+		result |= pmgr_binning_read_register(fuse_to_register[i].register_address,
+											 fuse_to_register[i].register_low,
+											 binning_high - fuse_to_register[i].binning_low + fuse_to_register[i].register_low,
+											 fuse_to_register[i].register_64bit) << (fuse_to_register[i].binning_low - binning_low);
+		binning_high = fuse_to_register[i].binning_low - 1;
+	}
+	return result;
+}
+
+static uint32_t pmgr_binning_from_const_data(enum pmgr_binning_type_t type, uint32_t mode, bool use_binning)
+{
+	uint32_t i;
+	for (i = 0; i < pmgr_binning_mode_to_const_data_size; i++) {
+		if (pmgr_binning_mode_to_const_data[i].type != type) {
+			continue;
+		}
+		if (pmgr_binning_mode_to_const_data[i].mode != mode) {
+			continue;
+		}
+		if ((use_binning) && pmgr_binning_mode_to_const_data[i].bingroup != pmgr_binning_get_group() && pmgr_binning_mode_to_const_data[i].bingroup != PMGR_BINNING_GROUP_ALL) {
+			continue;
+		}
+		if ((use_binning) && (pmgr_binning_get_revision() < pmgr_binning_mode_to_const_data[i].fuse_revision_minimum)) {
+			continue;
+		}
+		if ((!use_binning) && (pmgr_binning_mode_to_const_data[i].fuse_revision_minimum != 0)) {
+			continue;
+		}
+		return pmgr_binning_mode_to_const_data[i].mv;
+	}
+	return PMGR_BINNING_NOTFOUND;
+}
+
+uint32_t pmgr_binning_from_config_data(uint32_t voltage_index, const struct pmgr_binning_voltage_index_to_config **config_data)
+{
+	uint32_t i;
+	for (i = 0; i < pmgr_binning_voltage_index_to_config_data_size; i++) {
+		if (pmgr_binning_voltage_index_to_config_data[i].voltage_index != voltage_index) {
+			continue;
+		}
+		if (pmgr_binning_voltage_index_to_config_data[i].bingroup != pmgr_binning_get_group() && pmgr_binning_voltage_index_to_config_data[i].bingroup != PMGR_BINNING_GROUP_ALL) {
+			continue;
+		}
+		if (pmgr_binning_get_revision() < pmgr_binning_voltage_index_to_config_data[i].fuse_revision_minimum) {
+			continue;
+		}
+		*config_data = &pmgr_binning_voltage_index_to_config_data[i];
+
+		return pmgr_binning_voltage_index_to_config_data[i].safe_voltage;
+	}
+	return PMGR_BINNING_NOTFOUND;
+}
+
+int32_t pmgr_binning_get_voltage_offset(uint32_t voltage_index, enum pmgr_binning_type_t type)
+{
+	uint32_t i;
+	uint32_t size = 0;
+	const struct pmgr_binning_voltage_index_to_offset *voltage_index_to_offset;
+	uint32_t board_id = platform_get_board_id();
+
+	for (i = 0; i < pmgr_binning_board_id_to_offsets_data_size; i++) {
+		if (pmgr_binning_board_id_to_offsets_data[i].board_id != board_id) {
+			continue;
+		}
+		if (pmgr_binning_board_id_to_offsets_data[i].type != type) {
+			continue;
+		}
+		if (platform_get_chip_revision() < pmgr_binning_board_id_to_offsets_data[i].chip_rev_min) {
+			continue;
+		}
+		if (pmgr_binning_board_id_to_offsets_data[i].bingroup != pmgr_binning_get_group() && pmgr_binning_board_id_to_offsets_data[i].bingroup != PMGR_BINNING_GROUP_ALL) {
+			continue;
+		}
+
+		voltage_index_to_offset = pmgr_binning_board_id_to_offsets_data[i].voltage_offsets;
+		size = pmgr_binning_board_id_to_offsets_data[i].size;
+		break;
+	}
+
+	for (i = 0; i < size; i++) {
+		if (voltage_index_to_offset[i].voltage_index != voltage_index) {
+			continue;
+		}
+		if (pmgr_binning_get_revision() < voltage_index_to_offset[i].fuse_revision_minimum) {
+			continue;
+		}
+
+		return voltage_index_to_offset[i].offset;
+	}
+
+	return 0;
+}
+
+uint32_t pmgr_binning_mode_get_value(enum pmgr_binning_type_t type, uint32_t mode)
+{
+	uint32_t i = 0;
+	do {
+		if (pmgr_binning_mode_to_fuse_data[i].type == PMGR_BINNING_END_OF_LIST) {
+			return PMGR_BINNING_NOTFOUND;
+		}
+		if (pmgr_binning_mode_to_fuse_data[i].type != type) {
+			i++;
+			continue;
+		}
+		if (pmgr_binning_mode_to_fuse_data[i].mode != mode) {
+			i++;
+			continue;
+		}
+		if (type != PMGR_BINNING_GROUP && pmgr_binning_mode_to_fuse_data[i].bingroup != pmgr_binning_get_group() && pmgr_binning_mode_to_fuse_data[i].bingroup != PMGR_BINNING_GROUP_ALL) {
+			i++;
+			continue;
+		}
+		break;
+	} while (1);
+
+	if (pmgr_binning_mode_to_fuse_data[i].low > pmgr_binning_mode_to_fuse_data[i].high) {
+		panic("Invalid low (%u) and high (%u) mode_to_fuse_data for type %u mode %u\n", pmgr_binning_mode_to_fuse_data[i].low, pmgr_binning_mode_to_fuse_data[i].high, type, mode);
+	}
+
+	uint32_t result = pmgr_binning_read(pmgr_binning_mode_to_fuse_data[i].fuse_to_register, pmgr_binning_mode_to_fuse_data[i].low, pmgr_binning_mode_to_fuse_data[i].high);
+	return result;
+}
+
+uint32_t pmgr_binning_get_base(void)
+{
+	static uint32_t base = 0;
+	if (base == 0) {
+		base = pmgr_binning_mode_get_value(PMGR_BINNING_BASE, 0);
+	}
+	return base;
+}
+
+uint32_t pmgr_binning_get_group(void)
+{
+	static uint32_t group = 0;
+	if (group == 0) {
+		group =pmgr_binning_mode_get_value(PMGR_BINNING_GROUP, 0);
+	}
+	return group;
+}
+
+uint32_t pmgr_binning_get_revision(void)
+{
+	static uint32_t revision = 0;
+	if (revision == 0) {
+		revision = pmgr_binning_mode_get_value(PMGR_BINNING_REV, 0);
+	}
+	return revision;
+}
+
+uint32_t pmgr_binning_mode_get_mv(enum pmgr_binning_type_t type, uint32_t mode)
+{
+	uint32_t value = pmgr_binning_mode_get_value(type, mode);
+	if ((value == PMGR_BINNING_NOTFOUND) || (value == 0)) {
+		return PMGR_BINNING_NOTFOUND;
+	}
+	return 25 * (pmgr_binning_get_base() + 1) + value * 5;
+}
+
+uint32_t pmgr_binning_get_mv(uint32_t voltage_index, bool sram, bool use_binning)
+{
+	uint32_t voltage;
+	int32_t voltage_offset;
+	uint32_t mode;
+	enum pmgr_binning_type_t type;
+
+	if (sram) {
+		if (voltage_index >= pmgr_binning_voltage_config_sram_data_size) {
+			return PMGR_BINNING_NOTFOUND;
+		}
+		const struct pmgr_binning_voltage_config *binning_voltage_config;
+		binning_voltage_config = &pmgr_binning_voltage_config_sram_data[voltage_index];
+
+		voltage = binning_voltage_config->safe_voltage;
+		type = binning_voltage_config->type;
+		mode = binning_voltage_config->mode;
+
+		if ((voltage == 0) && (type != PMGR_BINNING_NONE)){
+			return pmgr_binning_from_const_data(type, mode, use_binning);
+		}
+	} else {
+		const struct pmgr_binning_voltage_index_to_config *config_data;
+		if (pmgr_binning_from_config_data(voltage_index, &config_data) == PMGR_BINNING_NOTFOUND) {
+			return PMGR_BINNING_NOTFOUND;
+		}
+
+		voltage = config_data->safe_voltage;
+		type = config_data->type;
+		mode = config_data->mode;
+
+		if (use_binning) {
+			uint32_t voltage_binning = pmgr_binning_mode_get_mv(type, mode);
+			if (voltage_binning != PMGR_BINNING_NOTFOUND) {
+				voltage = voltage_binning;
+			}
+		}
+	}
+
+	voltage_offset = pmgr_binning_get_voltage_offset(voltage_index, type);
+	if ((int32_t)voltage + voltage_offset < 0) {
+		panic("Invalid voltage offset");
+	}
+
+	return voltage + voltage_offset;
+}
+
+const struct pmgr_binning_vol_adj *pmgr_binning_get_vol_adj(uint32_t chipdid, uint32_t chip_rev, uint32_t voltage_index)
+{
+	uint32_t fuse_rev = pmgr_binning_get_revision();
+
+	for (size_t i = 0; i < pmgr_binning_voltadj_entry_data_size; i++) {
+		if (voltage_index != pmgr_binning_voltadj_entry_data[i].voltage_index) {
+			continue;
+		}
+		if ((chip_rev < pmgr_binning_voltadj_entry_data[i].chip_rev_min)) {
+			continue;
+		}
+		if ((fuse_rev < pmgr_binning_voltadj_entry_data[i].fuse_rev_min)) {
+			continue;
+		}
+		return &pmgr_binning_voltadj_entry_data[i].voltages;
+	}
+	return NULL;
+}

platform/generic/pmgr/pmgr_binning_menu.c

@@ -0,0 +1,344 @@
+/*
+
+ * Copyright (c) 2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#if !RELEASE_BUILD && WITH_MENU
+
+#include <sys/menu.h>
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+#include <platform.h>
+#include <stdio.h>
+#include <sys.h>
+#include <lib/env.h>
+#include <platform/pmgr.h>
+
+static bool pmgr_binning_menu_override_get_voltage_indexes(bool gpu, uint32_t *voltage_indexes, uint32_t voltage_index_size, uint32_t *voltage_index_found)
+{
+	uint32_t freq = 0;
+	uint32_t i = 0;
+	const char *name = env_get(gpu?"pmgr_gpu_override":"pmgr_cpu_override");
+	const struct pmgr_binning_voltage_index_to_config *config_data;
+	*voltage_index_found = 0;
+	if (name == NULL) {
+		return false;
+	}
+
+	while (i < voltage_index_size) {
+		if (i > 0) {
+			name = strchr(name, ',');
+			if (name == NULL) {
+				break;
+			}
+			name++;
+		}
+		
+		voltage_indexes[i] = atoi(name);
+		if (pmgr_binning_from_config_data(voltage_indexes[i], &config_data) == PMGR_BINNING_NOTFOUND) {
+			return false;
+		}
+		if ((gpu) && (config_data->type != PMGR_BINNING_GPU)) {
+			return false;
+		}
+		if ((!gpu) && (config_data->type != PMGR_BINNING_CPU)) {
+			return false;
+		}
+		freq = pmgr_platform_get_freq(gpu, voltage_indexes[i]);
+		if (freq == 0) {
+			return false;
+		}
+		i++;
+	}
+	*voltage_index_found = i;
+	return true;
+}
+
+static bool pmgr_binning_menu_find_safe_voltage(enum pmgr_binning_type_t type, uint32_t mode,
+				uint32_t *safe_voltage, uint32_t *freq)
+{
+	uint32_t i;
+	*freq = 0;
+	for (i = 0; i < pmgr_binning_voltage_config_sram_data_size; i++) {
+		if (pmgr_binning_voltage_config_sram_data[i].mode != mode) {
+			continue;
+		}
+		if (pmgr_binning_voltage_config_sram_data[i].type != type) {
+			continue;
+		}
+		*safe_voltage = pmgr_binning_voltage_config_sram_data[i].safe_voltage;
+		return true;
+	}
+	for (i = 0; i < pmgr_binning_voltage_index_to_config_data_size; i++) {
+		if (pmgr_binning_voltage_index_to_config_data[i].mode != mode) {
+			continue;
+		}
+		if (pmgr_binning_voltage_index_to_config_data[i].type != type) {
+			continue;
+		}
+		if (type == PMGR_BINNING_CPU) {
+			*freq = pmgr_platform_get_freq(false, pmgr_binning_voltage_index_to_config_data[i].voltage_index);
+		} else if (type == PMGR_BINNING_GPU) {
+			*freq = pmgr_platform_get_freq(true, pmgr_binning_voltage_index_to_config_data[i].voltage_index);
+		}
+		*safe_voltage = pmgr_binning_voltage_index_to_config_data[i].safe_voltage;
+		return true;
+	}
+	return false;
+}
+
+static void pmgr_binning_menu_print_type(enum pmgr_binning_type_t type)
+{
+	uint32_t mode;
+	for (mode = 1; mode < 63; mode++) {
+		uint32_t result = pmgr_binning_mode_get_value(type, mode);
+		uint32_t safe_voltage;
+		uint32_t freq;
+		if ((result == PMGR_BINNING_NOTFOUND) || (result == 0)) {
+			continue;
+		}
+		printf("    mode %u %u mV (0x%x)", mode, pmgr_binning_mode_get_mv(type, mode), pmgr_binning_mode_get_value(type, mode));
+
+		if (!pmgr_binning_menu_find_safe_voltage(type, mode, &safe_voltage, &freq)) {
+			printf(" no safe voltage");
+		} else {
+			printf(" safe voltage %u mV", safe_voltage);
+		}
+
+		if (freq > 0) {
+			printf(" %u MHz", freq);
+		}
+		printf("\n");
+	}
+}
+
+static void pmgr_binning_menu_voltage_config_print(const struct pmgr_binning_voltage_config *voltage_config, uint32_t voltage_index)
+{
+	const char *name = "";
+	uint32_t freq = 0, safe_voltage = 0, mode = 0, type = 0;
+	bool sram = false;
+
+	if (voltage_config != NULL) {
+		safe_voltage = voltage_config->safe_voltage;
+		mode = voltage_config->mode;
+		type = voltage_config->type;
+	}
+	else {
+		const struct pmgr_binning_voltage_index_to_config *config_data;
+		if (pmgr_binning_from_config_data(voltage_index, &config_data) == PMGR_BINNING_NOTFOUND) {
+			return;
+		}
+		safe_voltage = config_data->safe_voltage;
+		mode = config_data->mode;
+		type = config_data->type;
+	}
+	if (type == PMGR_BINNING_NONE) {
+		return;
+	}
+	switch (type) {
+		case PMGR_BINNING_CPU:
+			name = "CPU";
+			freq = pmgr_platform_get_freq(false, voltage_index);
+			break;
+		case PMGR_BINNING_GPU:
+			name = "GPU";
+			freq = pmgr_platform_get_freq(true, voltage_index);
+			break;
+		case PMGR_BINNING_SOC:
+			name = "SOC";
+			break;
+		case PMGR_BINNING_CPU_SRAM:
+			name = "CPU SRAM";
+			sram = true;
+			break;
+		case PMGR_BINNING_GPU_SRAM:
+			name = "GPU SRAM";
+			sram = true;
+			break;
+		case PMGR_BINNING_SRAM:
+			name = "SRAM";
+			sram = true;
+			break;
+		default:
+			name = "Unknown";
+			break;
+	}
+
+	printf("    %s index %u safe voltage %u mV",
+			name,
+			voltage_index,
+			pmgr_binning_get_mv(voltage_index, sram, false));
+
+	if (pmgr_binning_mode_get_mv(type,  mode) != PMGR_BINNING_NOTFOUND) {
+		printf(" binning %u mV", pmgr_binning_get_mv(voltage_index, sram, true));
+	} else {
+		printf(" no binning %u mV", pmgr_binning_get_mv(voltage_index, sram, true));
+	}
+
+	printf(" offset %d mV", pmgr_binning_get_voltage_offset(voltage_index, type));
+
+	if (mode != PMGR_BINNING_MODE_NONE && mode > 0) {
+		printf(" mode %u", mode);
+	}
+
+	if (freq > 0) {
+		printf(" %u MHz", freq);
+	}
+
+	if (sram && safe_voltage == 0) {
+		uint32_t i;
+		for (i = 0; i < pmgr_binning_mode_to_const_data_size; i++) {
+			if (pmgr_binning_mode_to_const_data[i].type != type) {
+				continue;
+			}
+			if (pmgr_binning_mode_to_const_data[i].mode != mode) {
+				continue;
+			}
+			if (pmgr_binning_mode_to_const_data[i].bingroup != pmgr_binning_get_group() && pmgr_binning_mode_to_const_data[i].bingroup != PMGR_BINNING_GROUP_ALL) {
+				continue;
+			}
+			printf(" fuse >= %d %d mV", pmgr_binning_mode_to_const_data[i].fuse_revision_minimum,  pmgr_binning_mode_to_const_data[i].mv + pmgr_binning_get_voltage_offset(voltage_index, type));
+		}
+	}
+	else if (!sram && mode != PMGR_BINNING_MODE_NONE) {
+		uint32_t i;
+		for (i = 0; i < pmgr_binning_voltage_index_to_config_data_size; i++) {
+			if (pmgr_binning_voltage_index_to_config_data[i].voltage_index != voltage_index) {
+				continue;
+			}
+			if (pmgr_binning_voltage_index_to_config_data[i].type != type) {
+				continue;
+			}
+			if (pmgr_binning_voltage_index_to_config_data[i].bingroup != pmgr_binning_get_group() && pmgr_binning_voltage_index_to_config_data[i].bingroup != PMGR_BINNING_GROUP_ALL) {
+				continue;
+			}
+			printf(" fuse >= %d %d mV", pmgr_binning_voltage_index_to_config_data[i].fuse_revision_minimum,  pmgr_binning_voltage_index_to_config_data[i].safe_voltage + pmgr_binning_get_voltage_offset(voltage_index, type));
+		}
+	}
+	printf("\n");
+}
+
+static void pmgr_binning_menu_current_values_type(enum pmgr_binning_type_t type)
+{
+	uint32_t i = 0;
+	uint32_t freq;
+	uint32_t voltage;
+	while (pmgr_platform_get_perf_state(type, i, &voltage, &freq)) {
+		if (freq == 0) {
+			printf("    state %u: %u mV", i, voltage);
+		} else {
+			printf("    state %u: %u Mhz %u mV", i, freq / 1000000, voltage);
+		}
+		if ((type == PMGR_BINNING_CPU) && (pmgr_platform_get_perf_state(PMGR_BINNING_CPU_SRAM, i, &voltage, &freq))) {
+			printf(" SRAM %u mV", voltage);
+		}
+		if ((type == PMGR_BINNING_GPU) && (pmgr_platform_get_perf_state(PMGR_BINNING_GPU_SRAM, i, &voltage, &freq))) {
+			printf(" SRAM %u mV", voltage);
+		}
+		printf("\n");
+		i++;
+	}
+}
+
+static int do_pmgr(int argc, struct cmd_arg *args)
+{
+	uint32_t voltage_indexes[32];
+	uint32_t max_voltage_index = 0;
+	uint32_t voltage_index_found;
+	if ((argc < 2) || ((strcmp(args[1].str, "binning") != 0) && (strcmp(args[1].str, "values") != 0))) {
+		printf("Usage\n");
+		printf("    pmgr [values | [binning [internal|values]]]\n");
+		printf("         pmgr binning: fused value\n");
+		printf("         pmgr binning internal: fused value and all known operating points\n");
+		printf("         pmgr values: values currently set in PMGR/ACC registers\n");
+		return 0;
+	}
+
+	if ((argc > 1) && (strcmp(args[1].str, "values") == 0)) {
+                printf("CPU:\n");
+                pmgr_binning_menu_current_values_type(PMGR_BINNING_CPU);
+                printf("GPU:\n");
+                pmgr_binning_menu_current_values_type(PMGR_BINNING_GPU);
+                printf("SOC:\n");
+                pmgr_binning_menu_current_values_type(PMGR_BINNING_SOC);
+		return 0;
+        }
+
+	printf("Fuse revision %u base %u bin group %u\n", pmgr_binning_get_revision(), pmgr_binning_get_base(), pmgr_binning_get_group());
+	printf("  CPU\n");
+	pmgr_binning_menu_print_type(PMGR_BINNING_CPU);
+	printf("  CPU SRAM\n");
+	pmgr_binning_menu_print_type(PMGR_BINNING_CPU_SRAM);
+	printf("  GPU\n");
+	pmgr_binning_menu_print_type(PMGR_BINNING_GPU);
+	printf("  GPU SRAM\n");
+	pmgr_binning_menu_print_type(PMGR_BINNING_GPU_SRAM);
+	printf("  SRAM\n");
+	pmgr_binning_menu_print_type(PMGR_BINNING_SRAM);
+	printf("  SOC\n");
+	pmgr_binning_menu_print_type(PMGR_BINNING_SOC);
+
+	if ((argc > 2) && (strcmp(args[2].str, "internal") == 0)) {
+		uint32_t i;
+		printf("\n");
+		for (i = 0; i < pmgr_binning_voltage_index_to_config_data_size; i++) {
+			if (pmgr_binning_voltage_index_to_config_data[i].voltage_index > max_voltage_index) {
+				max_voltage_index = pmgr_binning_voltage_index_to_config_data[i].voltage_index;
+			}
+		}
+		for (i = 0; i <= max_voltage_index; i++) {
+			pmgr_binning_menu_voltage_config_print(NULL, i);
+		}
+		for (i = 0; i < pmgr_binning_voltage_config_sram_data_size; i++) {
+			pmgr_binning_menu_voltage_config_print(&pmgr_binning_voltage_config_sram_data[i], i);
+		}
+	}
+
+	if (pmgr_binning_menu_override_get_voltage_indexes(false, voltage_indexes, sizeof(voltage_indexes)/sizeof(voltage_indexes[0]), &voltage_index_found)) {
+		uint32_t i;
+		for (i = 0; i < voltage_index_found; i++) {
+			if (i == 0) {
+				printf("\n\nOverridden CPU states:\n");
+			}
+			printf("    state %u ", i + 3); // state 0 (bypass), 1 (securerom) and 2 (current state) are not overridden
+			pmgr_binning_menu_voltage_config_print(NULL, voltage_indexes[i]);
+		}
+	}
+	if (pmgr_binning_menu_override_get_voltage_indexes(true, voltage_indexes, sizeof(voltage_indexes)/sizeof(voltage_indexes[0]), &voltage_index_found)) {
+		uint32_t i;
+		for (i = 0; i < voltage_index_found; i++) {
+			if (i == 0) {
+				printf("\n\nOverridden GPU states:\n");
+			}
+			printf("    state %u ", i + 1); // state 0 (off) are not overridden
+			pmgr_binning_menu_voltage_config_print(NULL, voltage_indexes[i]);
+		}
+	}
+	return 0;
+}
+
+void pmgr_binning_menu_update_states(void)
+{
+	uint32_t voltage_indexes[32];
+	uint32_t voltage_index_found;
+
+	if (pmgr_binning_menu_override_get_voltage_indexes(false, voltage_indexes, sizeof(voltage_indexes)/sizeof(voltage_indexes[0]), &voltage_index_found)) {
+		pmgr_platform_set_perf_state(false, 3, voltage_indexes, voltage_index_found);
+	}
+	if (pmgr_binning_menu_override_get_voltage_indexes(true, voltage_indexes, sizeof(voltage_indexes)/sizeof(voltage_indexes[0]), &voltage_index_found)) {
+		pmgr_platform_set_perf_state(true, 1, voltage_indexes, voltage_index_found);
+	}
+}
+
+// _command, _function, _help, _meta
+MENU_COMMAND_DEVELOPMENT(pmgr, do_pmgr, "Print pmgr data", NULL);
+
+#endif // !RELEASE_BUILD && WITH_MENU

platform/generic/pmgr/rules.mk

@@ -0,0 +1,42 @@
+# Copyright (C) 2015 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+# All H8+ chip must use pmgr_binning
+PMGR_BINNING=0
+
+ifeq ($(SUB_PLATFORM),s8000)
+PMGR_BINNING=1
+endif
+
+ifeq ($(SUB_PLATFORM),s8001)
+PMGR_BINNING=1
+endif
+
+ifeq ($(SUB_PLATFORM),s8003)
+PMGR_BINNING=1
+endif
+
+ifeq ($(PMGR_BINNING),1)
+ALL_OBJS += \
+	$(LOCAL_DIR)/pmgr_binning.o
+
+ifneq ($(BUILD),RELEASE)
+ifeq ($(PRODUCT),iBoot)
+ALL_OBJS +=                     \
+    $(LOCAL_DIR)/pmgr_binning_menu.o
+endif
+ifeq ($(PRODUCT),iBEC)
+ALL_OBJS +=                     \
+    $(LOCAL_DIR)/pmgr_binning_menu.o
+endif
+endif
+endif
+

platform/generic/rules.mk

@@ -0,0 +1,48 @@
+# Copyright (C) 2007-2013 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+#
+# Objects that must be built for every target.
+# 
+# Adding files here is very expensive, as each file
+# gets compiled for every target/product/build permutation.
+#
+#
+
+ifneq ($(APPLICATION),SecureROM)
+MODULES += \
+	$(LOCAL_DIR)/pmgr
+endif
+
+ALL_OBJS += \
+	$(LOCAL_DIR)/default_mib.o \
+	$(LOCAL_DIR)/platform_info.o \
+	$(LOCAL_DIR)/platform_dep.o \
+	$(LOCAL_DIR)/target_dep.o
+
+# Include library with platform/target/product-independent functions
+LIBRARY_MODULES += $(LOCAL_DIR)
+
+#
+# The platform_info file contains symbols with useful information
+#
+INFO_SYMBOL_FILE	:=	$(call TOBUILDDIR,$(LOCAL_DIR)/platform_info.o)
+
+# for platform_get_security_epoch()
+ifeq ($(DEVMAP_EPOCH),)
+OPTIONS			+=	PLATFORM_SECURITY_EPOCH=00
+else
+OPTIONS			+=	PLATFORM_SECURITY_EPOCH=$(DEVMAP_EPOCH)
+endif
+
+ifneq ($(DEVMAP_PRODUCT_ID),)
+OPTIONS			+=	PLATFORM_PRODUCT_ID=`echo $(DEVMAP_PRODUCT_ID) | sed 's/../0x&,/g' | sed 's/.*/{&}/g'`
+endif

platform/generic/target_dep.c

@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#include <lib/syscfg.h>
+#include <lib/env.h>
+#include <stdint.h>
+
+// Target/product dependent functions that aren't expected to be overridden by targets
+
+bool target_is_tethered(void)
+{
+#if WITH_SYSCFG
+	uint8_t tethcfg[16];
+
+	if ((syscfgCopyDataForTag('Teth', tethcfg, 16) != -1) && (tethcfg[0] != 0x0)) {
+		return true;
+	}
+#endif
+
+	return 0 != env_get_uint("is-tethered", 0);
+}

platform/generic/target_indep.c

@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2012-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#include <platform.h>
+#include <stdbool.h>
+#include <target.h>
+
+bool target_config_ap(void)
+{
+	static bool valid = false;
+	static bool result;
+
+	if (!valid) {
+		result = (platform_get_board_id() & 1) == 0;
+		valid = true;
+	}
+
+	return result;
+}
+
+bool target_config_dev(void)
+{
+	static bool valid = false;
+	static bool result;
+
+	if (!valid) {
+		result = (platform_get_board_id() & 1) != 0;
+		valid = true;
+	}
+
+	return result;
+}

platform/generic/target_pass_boot_manifest.c

@@ -0,0 +1,247 @@
+/*
+ * Copyright (C) 2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <target.h>
+#include <stdlib.h>
+#include <lib/devicetree.h>
+#include <lib/image4_spi.h>
+#include <debug.h>
+
+/**
+ * Stash away properties in a simple data structure while the image is being validated.
+ *
+ * The image4 wrapper extracts out properties before declaring an overall image valid/invalid,
+ * and we also can load the kernelcache before the device tree.
+ */
+#define N_BOOL_PROPS 20
+#define N_INT_PROPS  20
+#define N_STRING_PROPS 10
+#define MAX_IMG4_STRING_LEN 64
+typedef struct {
+	uint32_t tag;
+	bool val;
+} bool_prop_t;
+typedef struct {
+	uint32_t tag;
+	uint64_t val;
+} int_prop_t;
+typedef struct {
+	uint32_t tag;
+	size_t length;
+	uint8_t data[MAX_IMG4_STRING_LEN];
+} string_prop_t;
+
+typedef struct {
+	bool_prop_t	bool_props[N_BOOL_PROPS];
+	int_prop_t	int_props[N_INT_PROPS];
+	string_prop_t	string_props[N_STRING_PROPS];
+
+} image4_property_collection_t;
+
+struct {
+	bool is_valid;
+	bool cb_encountered_error;
+	image4_property_collection_t manifest_properties;
+	image4_property_collection_t manifest_object_properties;
+} image4_properties;
+
+static bool image4_start_cb(uint32_t type)
+{
+	return (type == IMAGE_TYPE_KERNELCACHE || type == IMAGE_TYPE_KERNELCACHE_RESTORE);
+}
+static void image4_update_validity(bool is_valid)
+{
+	if (!is_valid) {
+		bzero(&image4_properties, sizeof(image4_properties));
+	}
+	image4_properties.is_valid = is_valid;
+}
+static void image4_bool_cb(uint32_t tag, bool is_object_property, bool val)
+{
+	bool_prop_t* properties = NULL;
+	if (is_object_property) {
+		properties = image4_properties.manifest_object_properties.bool_props;
+	} else {
+		properties = image4_properties.manifest_properties.bool_props;
+	}
+
+	for(int i = 0; i < N_BOOL_PROPS; i++)
+	{
+		if(properties[i].tag == 0)
+		{
+			properties[i].tag = tag;
+			properties[i].val = val;
+			return;
+		}
+	}
+	dprintf(DEBUG_CRITICAL, "Ran out of space storing boolean properties -- please tune N_BOOL_PROPS");
+	image4_properties.cb_encountered_error = true;
+}
+static void image4_int_cb(uint32_t tag, bool is_object_property, uint64_t val)
+{
+	int_prop_t* properties = NULL;
+	if (is_object_property) {
+		properties = image4_properties.manifest_object_properties.int_props;
+	} else {
+		properties = image4_properties.manifest_properties.int_props;
+	}
+
+	for(int i = 0; i < N_INT_PROPS; i++)
+	{
+		if(properties[i].tag == 0)
+		{
+			properties[i].tag = tag;
+			properties[i].val = val;
+			return;
+		}
+	}
+	dprintf(DEBUG_CRITICAL, "Ran out of space storing integer properties -- please tune N_INT_PROPS");
+	image4_properties.cb_encountered_error = true;
+}
+static void image4_string_cb(uint32_t tag, bool is_object_property, uint8_t* data, size_t length)
+{
+	string_prop_t* properties = NULL;
+	if (is_object_property) {
+		properties = image4_properties.manifest_object_properties.string_props;
+	} else {
+		properties = image4_properties.manifest_properties.string_props;
+	}
+
+	for(int i = 0; i < N_STRING_PROPS; i++)
+	{
+		if(properties[i].tag == 0)
+		{
+			if (length > MAX_IMG4_STRING_LEN) {
+				dprintf(DEBUG_CRITICAL, "image4_string_cb: Property length %lu exceeds max supported length, %u", length, MAX_IMG4_STRING_LEN);
+				image4_properties.cb_encountered_error = true;
+				return;
+			}
+			properties[i].tag = tag;
+			memcpy(properties[i].data, data, length);
+			properties[i].length = length;
+			return;
+		}
+	}
+	dprintf(DEBUG_CRITICAL, "Ran out of space storing string properties -- please tune N_STRING_PROPS");
+	image4_properties.cb_encountered_error = true;
+}
+#define IMG4UNTAG(x)		(((x) >> 24) & 0xff),(((x) >> 16) & 0xff),(((x) >> 8) & 0xff),((x) & 0xff)
+
+static int image4_copy_boolean_properties(DTNode* node, bool_prop_t* props)
+{
+	char entryName[50];
+	char* propName;
+	void* propData;
+	uint32_t propSize;
+	for(int i = 0; (i < N_BOOL_PROPS) && (props[i].tag != 0); i++) {
+		snprintf(entryName, sizeof(entryName), "UnusedBooleanProperty%d", i);
+		propName = entryName;
+		if (!FindProperty(node, &propName, &propData, &propSize)) {
+			dprintf(DEBUG_CRITICAL, "Ran out of boolean entries %s", propName);
+			return -1;
+		}
+		snprintf(entryName, sizeof(entryName), "%c%c%c%c", IMG4UNTAG(props[i].tag));		
+		strlcpy(propName, entryName, kPropNameLength);
+		memcpy(propData, &props[i].val, sizeof(bool));
+	}
+	return 0;
+}
+static int image4_copy_integer_properties(DTNode* node, int_prop_t* props)
+{
+	char entryName[50];
+	char* propName;
+	void* propData;
+	uint32_t propSize;
+	for(int i = 0; (i < N_INT_PROPS) && (props[i].tag != 0); i++) {
+		snprintf(entryName, sizeof(entryName), "UnusedIntegerProperty%d", i);
+		propName = entryName;
+		if (!FindProperty(node, &propName, &propData, &propSize)) {
+			dprintf(DEBUG_CRITICAL, "Ran out of integer entries %s", propName);
+			return -1;
+		}
+		snprintf(entryName, sizeof(entryName), "%c%c%c%c", IMG4UNTAG(props[i].tag));		
+		strlcpy(propName, entryName, kPropNameLength);
+		memcpy(propData, &props[i].val, sizeof(uint64_t));
+	}
+	return 0;
+}
+static int image4_copy_string_properties(DTNode* node, string_prop_t* props)
+{
+	char entryName[50];
+	char* propName;
+	void* propData;
+	uint32_t propSize;
+	for(int i = 0; (i < N_STRING_PROPS) && (props[i].tag != 0); i++) {
+		snprintf(entryName, sizeof(entryName), "UnusedStringProperty%d", i);
+		propName = entryName;
+		if (!FindProperty(node, &propName, &propData, &propSize)) {
+			dprintf(DEBUG_CRITICAL, "Ran out of string entries %s", propName);
+			return -1;
+		}
+		if (propSize < props[i].length) {
+			dprintf(DEBUG_CRITICAL, "DT property size too small to fit string property");
+			return -2;
+		}
+
+		snprintf(entryName, sizeof(entryName), "%c%c%c%c", IMG4UNTAG(props[i].tag));		
+		strlcpy(propName, entryName, kPropNameLength);
+		memcpy(propData, &props[i].data, props[i].length);
+	}
+	return 0;
+}
+
+static bool initialized;
+
+int target_init_boot_manifest(void)
+{
+	image4_register_property_capture_callbacks(image4_start_cb, 
+  		image4_bool_cb, image4_int_cb, image4_string_cb, image4_update_validity);
+	initialized=true;
+	return 0;
+}
+int target_pass_boot_manifest(void)
+{
+	// You must call init before loading the image4 of interest.
+	if (!initialized)
+		panic("target_pass_boot_manifest() used without target_init_boot_manifest()");
+
+	if (!image4_properties.is_valid || image4_properties.cb_encountered_error) {
+		// Don't touch the DT unless the image is validated.
+		return -1;
+	}
+	const char* ManifestPropertiesPath = "chosen/manifest-properties";
+	const char* ManifestObjectPropertiesPath = "chosen/manifest-object-properties";
+	DTNode* dtnode;
+	if (FindNode(0, ManifestPropertiesPath, &dtnode)) {
+		if (image4_copy_boolean_properties(dtnode, image4_properties.manifest_properties.bool_props))
+			return -2;
+
+		if (image4_copy_integer_properties(dtnode, image4_properties.manifest_properties.int_props))
+			return -3;
+
+		if (image4_copy_string_properties(dtnode, image4_properties.manifest_properties.string_props))
+			return -4;
+	} else {
+		dprintf(DEBUG_CRITICAL, "Can't find manifest properties path %s -- Skipping DT patching\n", ManifestPropertiesPath);
+		return -5;
+	}
+	if (FindNode(0, ManifestObjectPropertiesPath, &dtnode)) {
+		if (image4_copy_boolean_properties(dtnode, image4_properties.manifest_object_properties.bool_props))
+			return -6;
+		if (image4_copy_integer_properties(dtnode, image4_properties.manifest_object_properties.int_props))
+			return -7;
+		if (image4_copy_string_properties(dtnode, image4_properties.manifest_object_properties.string_props))
+			return -8;
+	} else {
+		dprintf(DEBUG_CRITICAL, "Can't find manifest object properties path %s -- Skipping DT patching\n", ManifestObjectPropertiesPath);
+		return -9;
+	}
+	return 0;
+}

platform/s5l8747x/asm.S

@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <arch/arm/assembler.h>
+#include <platform/memmap.h>
+
+	.text
+
+ARM_FUNCTION _platform_start
+	
+#if WITH_PROFILE && PROFILE_BUF_SIZE > 0
+	// Turn on PCLK to TIM64
+	mov		r2, #0x0200
+	movt		r2, #0x3c50
+	ldr		r3, [r2, #4]
+	bic		r3, #(1 << 30)
+	str		r3, [r2, #4]
+	
+	// Turn on NCLK to TIM64
+	ldr		r3, [r2, #0x10]
+	bic		r3, #(1 << 8)
+	str		r3, [r2, #0x10]
+
+	// Enable TIM64
+	mov		r2, #0x0088
+	movt		r2, #0x3c70
+	// r3 = (r<<15)|(1<<4)
+	mov		r3, #((1 << 15) | (1 << 4))
+	movt		r3, #1
+	str		r3, [r2]
+#endif
+
+	bx		lr
+
+	

platform/s5l8747x/chipid/chipid.c

@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <platform.h>
+#include <platform/soc/chipid.h>
+#include <platform/soc/hwclocks.h>
+
+bool chipid_get_production_mode(void)
+{
+	while (!chipid_get_read_done());
+
+	return ((rCHIPIDL >> 0) & 1) != 0;
+}
+
+bool chipid_get_secure_mode(void)
+{
+	while (!chipid_get_read_done());
+
+	return ((rCHIPIDH >> 1) & 1) != 0;
+}
+
+u_int32_t chipid_get_security_domain(void)
+{
+	while (!chipid_get_read_done());
+
+#if SUPPORT_FPGA
+	return kPlatformSecurityDomainDarwin;
+#else
+	return (rCHIPIDH >> 1) & 3;
+#endif
+}
+
+u_int32_t chipid_get_minimum_epoch(void)
+{
+	while (!chipid_get_read_done());
+
+	return (rCHIPIDH >> 3) & 0x7F;
+}
+
+bool chipid_get_ecid_image_personalization_required(void)
+{
+	return ((rCHIPIDH >> 14) & 1) != 0;
+}
+
+u_int32_t chipid_get_board_id(void)
+{
+	while (!chipid_get_read_done());
+
+	return (rCHIPIDH >> 10) & 3;
+}
+
+u_int32_t chipid_get_chip_id(void)
+{
+	while (!chipid_get_read_done());
+
+	return (rCHIPIDH >> 16) & 0xFFFF;
+}
+
+u_int32_t chipid_get_chip_revision(void)
+{
+	while (!chipid_get_read_done());
+
+	return (((rCHIPIDL >> 24) & 0xF) << 4) | (((rCHIPIDL >> 28) & 0xF) << 0);
+}
+
+u_int32_t chipid_get_osc_frequency(void)
+{
+	return OSC_FREQ;
+}
+
+u_int64_t chipid_get_ecid_id(void)
+{
+	u_int64_t ecid = 0;
+
+	while (!chipid_get_read_done());
+
+#if SUPPORT_FPGA
+	ecid = 0x000012345678ABCDULL;
+#else
+	/*
+	 * For the sake of the next poor bastard that comes along and has
+	 * to decode the ECID produced by this silliness, the code here
+	 * produces output formatted thus:
+	 *
+	 * 6              4               3               1
+	 * 3              8               2               6               0
+	 * ......................lllllllllllllllllllllwwwwwyyyyyyyyxxxxxxxx
+	 *
+	 * l - lot number
+	 * w - wafer number
+	 * y - wafer y position
+	 * x - wafer x position
+	 */
+	ecid |= ((rDIEIDL >>  0)) & ((1ULL << (21 -  0)) - 1);	// LOT_ID
+
+	ecid <<= (26 - 21);
+	ecid |= ((rDIEIDL >> 21)) & ((1ULL << (26 - 21)) - 1);	// WAFER_NUM
+
+	ecid <<= (10 -  2);
+	ecid |= ((rDIEIDH >>  2)) & ((1ULL << (10 -  2)) - 1);	// Y_POS
+
+	ecid <<= (32 - 26);
+	ecid |= ((rDIEIDL >> 26)) & ((1ULL << (32 - 26)) - 1);	// X_POS_H
+
+	ecid <<= ( 2 -  0);
+	ecid |= ((rDIEIDH >>  0)) & ((1ULL << ( 2 -  0)) - 1);	// X_POS_L
+#endif
+
+	return ecid;
+}
+
+u_int64_t chipid_get_die_id(void)
+{
+	while (!chipid_get_read_done());
+
+	return ((u_int64_t)rDIEIDH << 32) | rDIEIDL;
+}
+
+//  chipid_get_tv_dac_cals
+//    Saves the three tv dac calibration values in the given array.
+//
+void chipid_get_tv_dac_cals(u_int32_t *dac_cals)
+{
+	while (!chipid_get_read_done());
+
+	dac_cals[0] = (rCHIPIDL >>  9) & 0x1F;
+	dac_cals[1] = (rCHIPIDL >> 14) & 0x1F;
+	dac_cals[2] = (rCHIPIDL >> 19) & 0x1F;
+}
+
+bool chipid_get_read_done(void)
+{
+#if !SUPPORT_FPGA
+	return ((rEFUSE_READ_DONE >> 0) & 1) != 0;
+#else
+	return true;
+#endif
+}
+

platform/s5l8747x/chipid/rules.mk

@@ -0,0 +1,15 @@
+# Copyright (C) 2011 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_PLATFORM_CHIPID=1
+
+ALL_OBJS += $(LOCAL_DIR)/chipid.o

platform/s5l8747x/clocks/clocks.c

@@ -0,0 +1,504 @@
+/*
+ * Copyright (C) 2011-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <debug.h>
+#include <platform.h>
+#include <lib/libc.h>
+#include <platform/clocks.h>
+#include <platform/timer.h>
+#include <platform/soc/clocks.h>
+#include <platform/soc/hwclocks.h>
+#include <platform/soc/chipid.h>
+#include <sys.h>
+#include <sys/boot.h>
+#include <sys/menu.h>
+
+#include <drivers/power.h>
+
+
+#define PLL_FREQ_TARGET(pllx) (1ULL * pllx##_O * pllx##_M / pllx##_P / (1 << pllx##_S))
+
+#define PRESCALE_EN(x)	((x) == 1 ? 0 : 1)
+#define CLK_DIV_N(x)	((x) == 1 ? 0 : ((x)/2)-1)
+
+#if APPLICATION_IBOOT
+
+//PLL0 @ 800MHz
+#define PLL0		0
+#define PLL0_O		OSC_FREQ
+#define PLL0_P		12
+#define PLL0_M		400
+#define PLL0_S		0
+#define PLL0_VSEL	1 // High if 600MHz < Fvco < 864MHz (Fvco = Fin * M / P)
+#define PLL0_T		PLL_FREQ_TARGET(PLL0)
+
+// PLL1 @ 330MHz
+#define PLL1		1
+#define PLL1_O		OSC_FREQ
+#define PLL1_P		4
+#define PLL1_M		110
+#define PLL1_S		1
+#define PLL1_VSEL	1 // High if 600MHz < Fvco < 864MHz (Fvco = Fin * M / P)
+#define PLL1_T		PLL_FREQ_TARGET(PLL1)
+
+// PLL2 @ 432MHz
+#define PLL2		2
+#define PLL2_O		OSC_FREQ
+#define PLL2_P		5
+#define PLL2_M		180
+#define PLL2_S		1
+#define PLL2_VSEL	1 // High if 600MHz < Fvco < 864MHz (Fvco = Fin * M / P)
+#define PLL2_T		PLL_FREQ_TARGET(PLL2432/)
+
+#define LOW_PERF_DIV_N		(11)
+#define MEDIUM_PERF_DIV_N	(5)
+#define MEMORY_PERF_DIV_N	(2)
+// With PLL0 @ 800MHz for B0, SCLK_DIV_VAL needs to be at least 2!
+#define HIGH_PERF_DIV_N		(2)
+
+#endif /* APPLICATION_IBOOT */
+
+#if APPLICATION_SECUREROM
+
+#define PLL0		0
+#define PLL0_O		OSC_FREQ
+#define PLL0_P		6
+#define PLL0_M		133
+#define PLL0_S		2
+#define PLL0_VSEL	0
+#define PLL0_T		PLL_FREQ_TARGET(PLL0)
+
+#define LOW_PERF_DIV_N		(1)
+#define MEDIUM_PERF_DIV_N	(1)
+#define MEMORY_PERF_DIV_N	(2)
+#define HIGH_PERF_DIV_N		(1)
+
+#endif /* APPLICATION_SECUREROM */
+
+#define SCLK_PLL	0
+#define FCLK_DIV_N	(1)
+#define DCLK_DIV_N	(1)
+#define ACLK_DIV_N	(MEMORY_PERF_DIV_N)
+#define HCLK_DIV_N	(MEMORY_PERF_DIV_N)
+#define PCLK_DIV_N	(MEMORY_PERF_DIV_N)
+
+#define NCLK_DIV_N	(1)
+
+/* current clock speeds */
+static u_int32_t clks[CLKGEN_CLK_COUNT];
+static u_int32_t *plls = &clks[CLKGEN_CLK_PLL0];
+
+static u_int32_t perf_level;
+static u_int32_t perf_div;
+
+static u_int32_t get_pll(int pll);
+
+int clocks_init(void)
+{
+#if APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC)
+	
+#if SUPPORT_FPGA
+	clks[CLKGEN_CLK_SCLK] = 10000000;
+	clks[CLKGEN_CLK_FCLK] = 10000000;
+	clks[CLKGEN_CLK_DCLK] = 10000000;
+	clks[CLKGEN_CLK_ACLK] = 10000000;
+	clks[CLKGEN_CLK_HCLK] = 10000000;
+	clks[CLKGEN_CLK_PCLK] = 10000000;
+	clks[CLKGEN_CLK_NCLK] = 10000000;
+	clks[CLKGEN_CLK_USBPHY] = 12000000;
+
+	perf_div = 1;
+	perf_level = kPerformanceHigh;
+
+#else
+#error "The calculations of vclk0 and vclk1 need to be scrubbed"
+	int cnt;
+	int sclk_pll	= ((rCLKCON0 >> 12) & 3) - 1;
+	int sclk_div_n	= ((rCLKCON0 >>  0) & 0xF) + 1;
+	int fclk_div_n	= ((rCLKCON1 >> 29) & 1) ? ((((rCLKCON1 >> 24) & 0x1F) + 1) * 2) : 1;
+	int dclk_div_n	= ((rCLKCON1 >> 23) & 1) ? ((((rCLKCON1 >> 18) & 0x1F) + 1) * 2) : 1;
+	int hclk_div_n	= ((rCLKCON1 >> 17) & 1) ? ((((rCLKCON1 >> 12) & 0x1F) + 1) * 2) : 1;
+	int pclk_div_n	= ((rCLKCON1 >> 11) & 1) ? ((((rCLKCON1 >>  6) & 0x1F) + 1) * 2) : 1;
+	int aclk_div_n	= ((rCLKCON1 >>  5) & 1) ? ((((rCLKCON1 >>  0) & 0x1F) + 1) * 2) : 1;
+	int vclk0_pll	= ((rCLKCON2 >> 28) & 3) - 1;
+	int vclk0_div_n	= ((rCLKCON2 >> 16) & 0xF) + 1;
+	int vclk1_pll	= ((rCLKCON2 >> 12) & 3) - 1;
+	int vclk1_div_n	= (((rCLKCON2 >> 0) & 0xF) + 1) * (((rCLKCON2 >> 4) & 0xF) + 1);
+	
+	plls[-1] = OSC_FREQ;
+	for (cnt = 0; cnt < 3; cnt++) plls[cnt] = get_pll(cnt);
+	
+	perf_div = sclk_div_n;
+
+	switch (perf_div) {
+		default :
+		case HIGH_PERF_DIV_N : perf_level = kPerformanceHigh; break;
+		case MEDIUM_PERF_DIV_N : perf_level = kPerformanceMedium; break;
+		case LOW_PERF_DIV_N : perf_level = kPerformanceLow; break;
+	}
+
+	clks[CLKGEN_CLK_SCLK] = plls[sclk_pll] / HIGH_PERF_DIV_N;
+	clks[CLKGEN_CLK_FCLK] = clks[CLKGEN_CLK_SCLK] / fclk_div_n;
+	clks[CLKGEN_CLK_DCLK] = clks[CLKGEN_CLK_SCLK] / dclk_div_n;
+	clks[CLKGEN_CLK_ACLK] = clks[CLKGEN_CLK_SCLK] / aclk_div_n;
+	clks[CLKGEN_CLK_HCLK] = clks[CLKGEN_CLK_SCLK] / hclk_div_n;
+	clks[CLKGEN_CLK_PCLK] = clks[CLKGEN_CLK_SCLK] / pclk_div_n;
+	clks[CLKGEN_CLK_VCLK0] = plls[vclk0_pll] / vclk0_div_n;
+	clks[CLKGEN_CLK_VCLK1] = plls[vclk1_pll] / vclk1_div_n;
+	
+	clks[CLKGEN_CLK_NCLK] = OSC_FREQ;
+	
+	clks[CLKGEN_CLK_USBPHY] = OSC_FREQ;
+#endif
+	
+#endif /* APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC) */
+
+	return 0;
+}
+
+static u_int32_t get_pll(int pll)
+{
+	volatile u_int32_t *pllpms;
+	u_int32_t pllcon, pms;
+	u_int64_t freq;
+	
+	pllcon = rPLLCON;
+	
+	if (((pllcon >> pll) & 1) == 0) return OSC_FREQ;
+	
+	switch (pll) {
+		case 0:
+			pllpms = &rPLL0PMS;
+			break;
+		case 1:
+			pllpms = &rPLL1PMS;
+			break;
+		case 2:
+			pllpms = &rPLL2PMS;
+			break;
+		case 3:
+			pllpms = &rPLL3PMS;
+			break;
+		default:
+			return 0;
+			break;
+	}
+	
+	freq = OSC_FREQ;
+	pms = *pllpms;
+	
+	freq *= (pms >> 8) & 0x3FF;  // *M
+	
+	freq /= (pms >> 24) & 0x3F;  // /P
+	
+	freq /= 1 << (pms & 0x07);   // /2^S
+	
+	return freq;
+}
+
+static void set_pll(int pll, u_int32_t p, u_int32_t m, u_int32_t s, u_int32_t vsel)
+{
+	volatile u_int32_t *pllpms;
+	volatile u_int32_t *plllcnt;
+
+	switch (pll) {
+		case 0:
+			pllpms = &rPLL0PMS;
+			plllcnt = &rPLL0LCNT;
+			break;
+		case 1:
+			pllpms = &rPLL1PMS;
+			plllcnt = &rPLL1LCNT;
+			break;
+		case 2:
+			pllpms = &rPLL2PMS;
+			plllcnt = &rPLL2LCNT;
+			break;
+		case 3:
+			pllpms = &rPLL3PMS;
+			plllcnt = &rPLL3LCNT;
+			break;
+		default:
+			return;
+	}
+
+	*pllpms = (vsel << 30) | (p << 24) | (m << 8) | (s << 0);	// set p/m/s values
+	*plllcnt = 300 * 24;						// set lock counter for 300us
+	rPLLCON |= (1<<(0+pll));					// pll power up
+#if !SUPPORT_FPGA
+	while ((rPLLLOCK & (1 << pll)) == 0);				// wait for pll to lock
+#endif /* ! SUPPORT_FPGA */
+	*pllpms = (vsel << 30) | (p << 24) | (m << 8) | (s << 0);	// set p/m/s values again
+	rPLLCON |= (1<<(16+pll));					// pll select output
+}
+
+int clocks_set_default(void)
+{
+	uint32_t cnt;
+
+	/* Change all the clocks to something safe */
+	clocks_quiesce();
+	
+	/* set up the clock tree to our default setting */
+	clks[CLKGEN_CLK_OSC] = OSC_FREQ;
+	
+#ifdef PLL0_T
+	set_pll(0, PLL0_P, PLL0_M, PLL0_S, PLL0_VSEL);
+#endif
+	
+#ifdef PLL1_T
+	set_pll(1, PLL1_P, PLL1_M, PLL1_S, PLL2_VSEL);
+#endif
+	
+#ifdef PLL2_T
+	set_pll(2, PLL2_P, PLL2_M, PLL2_S, PLL2_VSEL);
+#endif
+
+#ifdef PLL3_T
+	set_pll(3, PLL3_P, PLL3_M, PLL3_S, PLL3_VSEL);
+#endif
+
+	// Use get_pll() to establish the frequencies (unconfigured PLLs will bypass OSC)
+	for (cnt = 0; cnt < 4; cnt++) plls[cnt] = get_pll(cnt);
+	
+	perf_level = kPerformanceHigh;
+	perf_div = HIGH_PERF_DIV_N;
+	
+	clks[CLKGEN_CLK_SCLK] = plls[SCLK_PLL] / perf_div;
+	clks[CLKGEN_CLK_FCLK] = clks[CLKGEN_CLK_SCLK] / FCLK_DIV_N;
+	clks[CLKGEN_CLK_DCLK] = clks[CLKGEN_CLK_SCLK] / DCLK_DIV_N;
+	clks[CLKGEN_CLK_ACLK] = clks[CLKGEN_CLK_SCLK] / ACLK_DIV_N;
+	clks[CLKGEN_CLK_HCLK] = clks[CLKGEN_CLK_SCLK] / HCLK_DIV_N;
+	clks[CLKGEN_CLK_PCLK] = clks[CLKGEN_CLK_SCLK] / PCLK_DIV_N;
+	clks[CLKGEN_CLK_NCLK] = clks[CLKGEN_CLK_OSC] / NCLK_DIV_N;
+	clks[CLKGEN_CLK_USBPHY] = clks[CLKGEN_CLK_OSC];
+	
+	// switch the useful clocks back to their plls
+	rCLKCON1 = 
+		   (PRESCALE_EN(FCLK_DIV_N)<<29)|(CLK_DIV_N(FCLK_DIV_N)<<24) |		// FCLK
+		   (PRESCALE_EN(DCLK_DIV_N)<<23)|(CLK_DIV_N(DCLK_DIV_N)<<18) |		// DCLK
+		   (PRESCALE_EN(HCLK_DIV_N)<<17)|(CLK_DIV_N(HCLK_DIV_N)<<12) |		// HCLK
+		   (PRESCALE_EN(PCLK_DIV_N)<<11)|(CLK_DIV_N(PCLK_DIV_N)<< 6) |		// PCLK
+		   (PRESCALE_EN(ACLK_DIV_N)<< 5)|(CLK_DIV_N(ACLK_DIV_N)<< 0);		// ACLK
+	// must set divider before switching to PLL because of delay in divider taking effect
+	// <rdar://problem/11951206> Race condition in CLKCON register setting causes unpredictable behavior
+	rCLKCON0 = ((perf_div-1)<<0);
+	rCLKCON0 |= ((SCLK_PLL+1)<<12);
+	rCLKCON2 = (0<<15)|(1<<31);				// CLK_OUT0 enable, CLK_OUT1 disable
+	rCLKCON3 = (1<<31)|(2<<28)|(7<<16)			// VCLK_DAC source PLL2, div 7+1, disable
+		 | (1<<15)|(3<<12)|(0<<4)|(0<<0);		// RGBOUT_CLK source PLL3, div 1, disable
+	rCLKCON4 = (1<<31)|(0<<28)|(0<<16)			// MCLK1 source OSC,  div 1, disable
+		|(1<<15)|(3<<12)|(0<<4)|(0<<0);			// MCLK0 source PLL3, div 1, disable
+	rCLKCON5 = (1<<31)|(0<<28)|(0<<16)			// MCLK3 source OSC, div 1, disable
+		|(1<<15)|(0<<12)|(0<<0); 				// MCLK2 source OSC, div 1, disable
+		
+	rCLKCON6 = (0<<28)|((NCLK_DIV_N-1)<<16)		// NCLK source OSC, enable
+		|(1<<15)|(2<<12);						// MFC_CLK source PLL1, div 0+1, disable
+	
+	rCLKCON7 = (0x1F<<27)|(1<<24)|(3<<16)		// VMHCLKx source PLL0, div 3+1, disable
+		|(1<<15)|(1<<12)|(2<<0);		// SCALER source PLL0, div 2+1, disable
+	
+#if SUPPORT_FPGA
+	clks[CLKGEN_CLK_SCLK] = 10000000;
+	clks[CLKGEN_CLK_FCLK] = 10000000;
+	clks[CLKGEN_CLK_DCLK] = 10000000;
+	clks[CLKGEN_CLK_ACLK] = 10000000;
+	clks[CLKGEN_CLK_HCLK] = 10000000;
+	clks[CLKGEN_CLK_PCLK] = 10000000;
+	clks[CLKGEN_CLK_NCLK] = 10000000;
+	clks[CLKGEN_CLK_USBPHY] = 12000000;
+#endif
+	
+	return 0;
+}
+
+void clocks_quiesce(void)
+{
+	// Turn off non-critical device clocks
+	rCGCON0 = 0x00001CBF;	// HCLK to VROM
+	rCGCON1 = 0x3FC5EFFF;	// PCLKs to DREX, Timer64, Cortex-A5 Debug and Sys, AXI, and GPIO
+	rCGCON2 = 0x0000001F;
+	rCGCON3 = 0x00000000;	// ACLKs to AXI, XMC, and SRAM
+	rCGCON4 = 0x003DFEFF;	// NCLK to DREX and Timer64 on
+
+	// Set OSC to select the 12/24MHz clock
+	//rPLLCON &= ~(1 << 8); // FIXME
+
+	// Set all of the clocks to use OSC bypass.
+	// Disable the clocks that will not be used.
+	rCLKCON0 &= ~(0x3<<12);		// Use OSC bypass for SCLK ahead of turning off divider
+	rCLKCON0 = (1<<30);		// MCLK disable, SCLK enable, use OSC bypass, disable prescalar
+	rCLKCON1 = 0;			// FCLK/HCLK/PCLK/ACLK enable, use OSC bypass, disable prescalar
+	rCLKCON2 = (1<<31)|(1<<15);	// CLK_OUT1/CLK_OUT0 disable
+	rCLKCON3 = (1<<31)|(1<<15);	// VCLK_DAC/RGBOUT_VCLK disable
+	rCLKCON4 = (1<<31)|(1<<15);	// MCLK1/MCLK0 disable
+	rCLKCON5 = (1<<31)|(1<<15);	// MCLK3/MCLK2 disable
+	rCLKCON6 = (1<<15);		// NCLK enable, MFC_CLK disable
+	rCLKCON7 = (0x1F<<27)|(1<<15);	// VMHCLKx/SCALER disable
+
+	// Bypass and shut down all PLLs
+	rPLLCON &= ~0xF0000;
+	rPLLCON &= ~0x0000F;
+}
+
+u_int32_t clocks_get_performance_divider(void)
+{
+	return perf_div;
+}
+
+u_int32_t clocks_set_performance(u_int32_t performance_level)
+{
+	u_int32_t old_perf_level = perf_level;
+
+	switch (performance_level) {
+		default : performance_level = kPerformanceHigh;
+		case kPerformanceHigh: perf_div = HIGH_PERF_DIV_N; break;
+		case kPerformanceMedium: perf_div = MEDIUM_PERF_DIV_N; break;
+		case kPerformanceLow: perf_div = LOW_PERF_DIV_N; break;
+
+		case kPerformanceMemory :
+			if (old_perf_level == kPerformanceHigh) goto done;
+
+			perf_div = MEMORY_PERF_DIV_N;
+			break;
+	}
+
+	perf_level = performance_level;
+
+	if (old_perf_level == kPerformanceMemory) {
+		rCLKCON1 =
+			   (PRESCALE_EN(HCLK_DIV_N)<<22)|(CLK_DIV_N(HCLK_DIV_N)<<17) |			// HCLK
+			   (PRESCALE_EN(PCLK_DIV_N)<<14)|(CLK_DIV_N(PCLK_DIV_N)<< 9) |			// PCLK
+			   (PRESCALE_EN(ACLK_DIV_N)<< 6)|(CLK_DIV_N(ACLK_DIV_N)<< 1);			// ACLK
+	}
+
+	rCLKCON0 = (rCLKCON0 & ~0xF) | ((perf_div - 1) & 0xF);
+
+	if (perf_level == kPerformanceMemory) {
+		rCLKCON1 =
+			   (PRESCALE_EN(1)<<22)|(CLK_DIV_N(1)<<17) |					// HCLK
+			   (PRESCALE_EN(1)<<14)|(CLK_DIV_N(1)<< 9) |					// PCLK
+			   (PRESCALE_EN(1)<< 6)|(CLK_DIV_N(1)<< 1);					// ACLK
+	}
+done:
+	return old_perf_level;
+}
+
+u_int32_t clock_get_frequency(int clock)
+{
+	switch (clock) {
+		case CLK_CPU:
+		case CLK_FCLK:
+			return clks[CLKGEN_CLK_FCLK];
+		case CLK_DCLK:
+		case CLK_MEM:
+			return clks[CLKGEN_CLK_DCLK];
+		case CLK_ACLK:
+			return clks[CLKGEN_CLK_ACLK];
+		case CLK_HCLK:
+		case CLK_BUS:
+			return clks[CLKGEN_CLK_HCLK];
+		case CLK_PERIPH:
+		case CLK_PCLK:
+			return clks[CLKGEN_CLK_PCLK];
+		case CLK_NCLK:
+		case CLK_FIXED:
+			return clks[CLKGEN_CLK_NCLK];
+		case CLK_TIMEBASE:
+#if SUPPORT_FPGA
+			// <rdar://problem/10442644> Rig clock frequency data for G1 FPGA
+			return clks[CLKGEN_CLK_NCLK] / 2;
+#else
+			return clks[CLKGEN_CLK_NCLK];
+#endif
+		case CLK_USBPHYCLK:
+			return clks[CLKGEN_CLK_USBPHY];
+		case CLK_MCLK:
+		default:
+			return 0;
+	}
+}
+
+void platform_reset(bool panic)
+{
+#if WITH_BOOT_STAGE
+	if (!panic) boot_set_stage(kPowerNVRAMiBootStageOff);
+#endif
+
+	/* reset ourselves */
+	wdt_chip_reset();
+
+	while (1);
+}
+
+
+void platform_system_reset(bool panic)
+{
+	dprintf(DEBUG_INFO, "no platform system reset, using normal reset\n");
+	platform_reset(panic);
+}
+
+struct clock_gate_entry {
+	u_int32_t	gccon0_mask;
+	u_int32_t	gccon1_mask;
+	u_int32_t	gccon2_mask;
+	u_int32_t	gccon3_mask;
+	u_int32_t	gccon4_mask;
+};
+
+static const struct clock_gate_entry clock_gate_map[] =
+{
+	[CLK_AES] =	{ 0x00000080, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_CHIPID] =	{ 0x00000000, 0x00020000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_DMAC0] =	{ 0x00000800, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_DMAC1] =	{ 0x00001000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_GPIO] =	{ 0x00000000, 0x00001000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_IIC0] =	{ 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x00001000 },
+	[CLK_IIC1] =	{ 0x00000000, 0x00000020, 0x00000000, 0x00000000, 0x00002000 },
+	[CLK_IIC2] =	{ 0x00000000, 0x00000040, 0x00000000, 0x00000000, 0x00004000 },
+	[CLK_PKE] =	{ 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_SHA1] =	{ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_SPI0] =	{ 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00008000 },
+	[CLK_SPI1] =	{ 0x00000000, 0x00000008, 0x00000000, 0x00000000, 0x00010000 },
+	[CLK_TIMER] =	{ 0x00000000, 0x7FC00000, 0x00000000, 0x00000000, 0x000001FF },
+	[CLK_UART0] =	{ 0x00000000, 0x00002000, 0x00000000, 0x00000000, 0x00000200 },
+	[CLK_UART1] =	{ 0x00000000, 0x00004000, 0x00000000, 0x00000000, 0x00000400 },
+	[CLK_UART2] =	{ 0x00000000, 0x00008000, 0x00000000, 0x00000000, 0x00000800 },
+	[CLK_USBOTG0] =	{ 0x00000004, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_USBOTG1] =	{ 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_USBPHY] =	{ 0x00000020, 0x00000800, 0x00000000, 0x00000000, 0x00000000 },
+	[CLK_ROSC] = 	{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 },
+};
+#define CLOCK_GATE_MAP_COUNT (sizeof(clock_gate_map) / sizeof(struct clock_gate_entry))
+
+void clock_gate(int device, bool enable)
+{
+	const struct clock_gate_entry	*entry = 0;
+
+	if (device > (int)CLOCK_GATE_MAP_COUNT)
+		panic("Invalid clock gate");
+
+	entry = &clock_gate_map[device];
+
+	if (enable) {
+		rCGCON0 &= ~entry->gccon0_mask;
+		rCGCON1 &= ~entry->gccon1_mask;
+		rCGCON2 &= ~entry->gccon2_mask;
+		rCGCON3 &= ~entry->gccon3_mask;
+		rCGCON4 &= ~entry->gccon4_mask;
+	} else {
+		rCGCON0 |= entry->gccon0_mask;
+		rCGCON1 |= entry->gccon1_mask;
+		rCGCON2 |= entry->gccon2_mask;
+		rCGCON3 |= entry->gccon3_mask;
+		rCGCON4 |= entry->gccon4_mask;
+	}
+}
+

platform/s5l8747x/clocks/rules.mk

@@ -0,0 +1,15 @@
+# Copyright (C) 2007 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_CLOCKS=1
+
+ALL_OBJS += $(LOCAL_DIR)/clocks.o

platform/s5l8747x/include/platform/gpiodef.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2011-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_GPIODEF_H
+#define __PLATFORM_GPIODEF_H
+
+/* S5L8747X specific gpio -> pin mappings */
+
+#include <platform/gpio.h>
+#include <platform/soc/hwregbase.h>
+
+#if WITH_TARGET_CONFIG
+# include <target/gpiodef.h>
+#endif
+
+/* define platform-specific gpios in a generic fashion here. */
+#define GPIO_IIC0_SCL		GPIO( 1, 1)
+#define GPIO_IIC0_SDA		GPIO( 1, 2)
+#define GPIO_IIC1_SCL		GPIO( 3, 6)
+#define GPIO_IIC1_SDA		GPIO( 3, 7)
+
+#define GPIO_BOARD_ID0		GPIO( 2, 3)
+#define GPIO_BOARD_ID1		GPIO( 2, 4)
+#define GPIO_BOARD_ID2		GPIO( 2, 5)
+#define GPIO_BOARD_ID3		GPIO( 2, 6)
+
+#define GPIO_BOOT_CONFIG0	GPIO( 2, 1)
+#define GPIO_BOOT_CONFIG1	GPIO( 2, 2)
+
+#define GPIO_FORCE_DFU		GPIO(3, 4)
+#define GPIO_DFU_STATUS		GPIO(3, 5)
+
+#define GPIO_CLK0_OUT		GPIO( 3, 0)
+
+#define SPI_NOR0		(0)
+#define SPI_NOR1		(1)
+
+#if SUPPORT_FPGA
+#define GPIO_SPI0_CS		GPIO(GPIO_PAD_SPI, 0)
+#define GPIO_SPI1_CS		GPIO(GPIO_PAD_SPI, 1)
+#else
+#define GPIO_SPI0_CS		GPIO( 1, 3)
+#define GPIO_SPI3_CS		GPIO( 4, 4)
+#endif
+
+#endif /* ! __PLATFORM_GPIODEF_H */

platform/s5l8747x/include/platform/image_devices.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_IMAGE_DEVICES_H
+#define __PLATFORM_IMAGE_DEVICES_H
+
+static const struct image_device platform_image_devices[] = {
+       { "nor0", 0x00000 }
+};
+
+#if WITH_SYSCFG
+static const struct image_device platform_syscfg_devices[] = {
+       { "nor0", 0x00000 }
+};
+#endif /* WITH_SYSCFG */
+
+#endif /* ! __PLATFORM_IMAGE_DEVICES_H */

platform/s5l8747x/include/platform/memmap.h

@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2011-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_MEMMAP_H
+#define __PLATFORM_MEMMAP_H
+
+/* S5L8747X hardware memory map */
+#define SDRAM_BASE			(0x08000000ULL)
+#define SDRAM_BANK_LEN			(0x10000000ULL)
+#define SDRAM_BANK_COUNT		1
+#define SDRAM_END			(SDRAM_BASE + (SDRAM_BANK_LEN * SDRAM_BANK_COUNT))
+#define VROM_BASE			(0x20000000ULL)
+#define VROM_BANK_LEN			(0x00100000ULL)
+#define VROM_LEN			(0x00020000ULL)
+#define SRAM_BASE			(0x22000000ULL)
+#define SRAM_BANK_LEN			(0x00400000ULL)
+#define SRAM_LEN			(0x00020000ULL)
+
+/* Sleep token is stored at first physical page in kernel memory */
+#define SLEEP_TOKEN_BUFFER_BASE		(SDRAM_BASE)
+
+/* reserved area for panic info */
+#define PANIC_SIZE		(0x00004000ULL)
+#define PANIC_BASE		(SDRAM_END - PANIC_SIZE)
+
+/* Purple graphics memory, must be 1 MB aligned */
+#define PURPLE_GFX_MEMORY_LEN	(0x09600000 - PANIC_SIZE)
+
+/* reserved area for iBoot */
+#define IBOOT_SIZE		(0x00100000 - PANIC_SIZE)
+#define IBOOT_BASE		(PANIC_BASE - IBOOT_SIZE)
+#define PROTECTED_REGION_SIZE	IBOOT_SIZE
+
+/* where to stick the mmu tt, default heap and insecure memory*/
+#if APPLICATION_SECUREROM
+#define MMU_TT_SIZE		(0x1000ULL)
+#define MMU_TT_BASE		(SRAM_BASE + SRAM_LEN - MMU_TT_SIZE)
+#define MMU_NONCACHE0_SIZE	(SRAM_BANK_LEN)
+#define MMU_NONCACHE0_PBASE	(SRAM_BASE)
+#define MMU_NONCACHE0_VBASE	(SRAM_BASE + SRAM_BANK_LEN)
+
+#define STACK_SIZE		(0x3000ULL)
+#define STACK_BASE		(MMU_TT_BASE - STACK_SIZE)
+
+#define HEAP_END		(STACK_BASE)
+
+#ifndef __ASSEMBLY__
+
+#define INSECURE_MEMORY_BASE	(SRAM_BASE)
+#define INSECURE_MEMORY_SIZE	((uintptr_t)__segment_start(__DATA) - INSECURE_MEMORY_BASE)
+
+#endif /* ! __ASSEMBLY__ */
+
+#endif /* APPLICATION_SECUREROM */
+
+/* iBoot SDRAM map
+0x08000000-0x0B000000 - Load area (48 MB)
+0x0B000000-0x0DF00000 - Kernel (47 MB)
+0x0DF00000-0x0E000000 - Device tree (1 MB)
+0x0E000000-0x11000000 - Ramdisk (48 MB)
+0x11000000-0x17F00000 - Heap (111 MB)
+0x17F00000-0x17FFC000 - iBoot (unused) (1008 kB)
+0x17FFC000-0x18000000 - Panic (16kB)
+*/
+
+#if APPLICATION_IBOOT
+#define MMU_TT_SIZE		(0x1000ULL)
+#define MMU_TT_BASE		(TEXT_BASE + TEXT_FOOTPRINT - MMU_TT_SIZE)
+#define MMU_NONCACHE0_SIZE	(SRAM_BANK_LEN)
+#define MMU_NONCACHE0_PBASE	(SRAM_BASE)
+#define MMU_NONCACHE0_VBASE	(SRAM_BASE + SRAM_BANK_LEN)
+#define MMU_NONCACHE1_SIZE	(0x10000000ULL)
+#define MMU_NONCACHE1_PBASE	(0x08000000ULL)
+#define MMU_NONCACHE1_VBASE	(0x28000000ULL)
+
+#if WITH_DFU_MODE
+#define STACK_SIZE		(0x3000ULL)
+
+#define INSECURE_MEMORY_SIZE	(0x00800000ULL)
+#define INSECURE_MEMORY_BASE	(SDRAM_BASE + ((u_int32_t)platform_get_memory_size()) - INSECURE_MEMORY_SIZE)
+
+#else /* !WITH_DFU_MODE */
+#define STACK_SIZE		(0x0800ULL)
+
+#define INSECURE_MEMORY_BASE		(SDRAM_BASE)
+#define INSECURE_MEMORY_SIZE		(DEFAULT_KERNEL_ADDRESS - SDRAM_BASE)
+#define DEFAULT_LOAD_ADDRESS		(INSECURE_MEMORY_BASE)
+#define DEFAULT_LOAD_SIZE		(0x03000000ULL)
+#define DEFAULT_KERNEL_ADDRESS		(DEFAULT_LOAD_ADDRESS + DEFAULT_LOAD_SIZE)
+#define DEFAULT_KERNEL_SIZE		(0x02F00000ULL)
+#define DEFAULT_DEVICETREE_ADDRESS	(DEFAULT_KERNEL_ADDRESS + DEFAULT_KERNEL_SIZE)
+#define DEFAULT_DEVICETREE_SIZE		(0x00100000ULL)
+#define DEFAULT_RAMDISK_ADDRESS		(DEFAULT_DEVICETREE_ADDRESS + DEFAULT_DEVICETREE_SIZE)
+#define DEFAULT_RAMDISK_SIZE		(0x03000000ULL)
+#define DEFAULT_FREE_ADDRESS		(DEFAULT_RAMDISK_ADDRESS + DEFAULT_RAMDISK_SIZE)
+
+#define SECURE_MEMORY_BASE	(INSECURE_MEMORY_BASE + INSECURE_MEMORY_SIZE)
+#define SECURE_MEMORY_SIZE	(IBOOT_BASE - SECURE_MEMORY_BASE)
+
+#define HEAP_EXT_BASE		(DEFAULT_FREE_ADDRESS)
+#define HEAP_EXT_SIZE		(IBOOT_BASE - HEAP_EXT_BASE)
+#endif /* !WITH_DFU_MODE */
+
+#define STACK_BASE		(MMU_TT_BASE - STACK_SIZE)
+
+/* Reserved area for boot trace */
+/* WARNING: We're really tight on SRAM on B137. So, the boot trace area overlaps
+   the initial stack area. We typically only use about 500 bytes of the initial stack,
+   and once we jump into main_task, we never use the initial stack again. So, as long
+   as we don't do too much tracing before jumping into main_task, we'll be OK */
+#define PROFILE_BUF_SIZE	(0x0800ULL)
+#define PROFILE_BUF_BASE	(STACK_BASE)
+
+#define HEAP_END		(STACK_BASE)
+
+#endif /* APPLICATION_IBOOT */
+
+#endif /* ! __PLATFORM_MEMMAP_H */

platform/s5l8747x/include/platform/pinconfig.h

@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_PINCONFIG_H
+#define __PLATFORM_PINCONFIG_H
+
+/* Default S5L8747X SoC Pin Configuration */
+
+static const struct gpio_default_config gpio_default_config[GPIO_GROUP_COUNT] = {
+/* P0  */  PINCONFIG(
+		PCON_DISABLE,	NO_PUPDN,	// I2S0_MCK ->
+		PCON_DISABLE,	NO_PUPDN,	// I2S0_LRCK ->
+		PCON_DISABLE,	NO_PUPDN,	// I2S0_BCK ->
+		PCON_DISABLE,	NO_PUPDN,	// I2S0_DOUT ->
+		PCON_DISABLE,	NO_PUPDN,	// I2S0_DIN ->
+		PCON_DISABLE,	NO_PUPDN,	// UART0_RXD ->
+		PCON_DISABLE,	NO_PUPDN,	// UART0_TXD ->
+		PCON_DISABLE,	NO_PUPDN	// UART0_NRTS ->
+	       ),
+/* P1  */  PINCONFIG(
+		PCON_DISABLE,	NO_PUPDN,	// UART0_NCTS ->
+		PCON_DISABLE,	NO_PUPDN,	// I2C0_SCL ->
+		PCON_DISABLE,	NO_PUPDN,	// I2C0_SDA ->
+		PCON_DISABLE,	PUP,		// SPI0_CEN ->		SPI0_CS
+		PCON_DISABLE,	PDN,		// SPI0_CLK ->		SPI0_CLK
+		PCON_DISABLE,	NO_PUPDN,	// SPI0_MOSI ->		SPI0_MOSI
+		PCON_DISABLE,	NO_PUPDN,	// SPI0_MISO ->		SPI0_MISO
+		PCON_DISABLE,	NO_PUPDN	// - ->
+	       ),
+/* P2  */  PINCONFIG(
+		PCON_DISABLE,	NO_PUPDN,	// GPIO0 ->
+		PCON_DISABLE,	NO_PUPDN,	// GPIO1 ->		BOOT_CONFIG[0]
+		PCON_DISABLE,	NO_PUPDN,	// GPIO2 ->		BOOT_CONFIG[1]
+		PCON_DISABLE,	NO_PUPDN,	// GPIO3 ->		BOARD_ID[1]
+		PCON_DISABLE,	NO_PUPDN,	// GPIO4 ->		BOARD_ID[2]
+		PCON_DISABLE,	NO_PUPDN,	// GPIO5 ->		BOARD_ID[3]
+		PCON_DISABLE,	NO_PUPDN,	// GPIO6 ->		BOARD_ID[4]
+		PCON_DISABLE,	NO_PUPDN	// GPIO7 ->
+	       ),
+/* P3  */  PINCONFIG(
+		PCON_DISABLE,	NO_PUPDN,	// CLK0_OUT ->
+		PCON_DISABLE,	NO_PUPDN,	// CLK1_OUT ->
+		PCON_DISABLE,	NO_PUPDN,	// HDMI_HPD ->
+		PCON_DISABLE,	NO_PUPDN,	// HDMI_CEC ->
+		PCON_IN,	PDN,		// FORCE_DFU ->		FORCE_DFU
+		PCON_DISABLE,	PDN,		// DFU_STATUS ->	DFU_STATUS
+		PCON_DISABLE,	NO_PUPDN,	// I2C1_SCL ->
+		PCON_DISABLE,	NO_PUPDN	// I2C1_SDA ->
+	       ),
+/* P4  */  PINCONFIG(
+		PCON_DISABLE,	NO_PUPDN,	// UART2_RXD ->
+		PCON_DISABLE,	NO_PUPDN,	// UART2_TXD ->
+		PCON_DISABLE,	NO_PUPDN,	// UART2_NRTS ->
+		PCON_DISABLE,	NO_PUPDN,	// UART2_NCTS ->
+		PCON_DISABLE,	NO_PUPDN,	// SPI1_CEN ->
+		PCON_DISABLE,	NO_PUPDN,	// SPI1_CLK ->
+		PCON_DISABLE,	NO_PUPDN,	// SPI1_MOSI ->
+		PCON_DISABLE,	NO_PUPDN	// SPI1_MISO ->
+	       ),
+/* P5  */  PINCONFIG(
+		PCON_DISABLE,	NO_PUPDN,	// UART1_RXD ->
+		PCON_DISABLE,	NO_PUPDN,	// UART1_TXD ->
+		PCON_DISABLE,	NO_PUPDN,	// UART1_NRTS ->
+		PCON_DISABLE,	NO_PUPDN,	// UART1_NCTS ->
+		PCON_DISABLE,	NO_PUPDN,	// VGA_VDEN ->
+		PCON_DISABLE,	NO_PUPDN,	// VGA_HSYNC ->
+		PCON_DISABLE,	NO_PUPDN,	// VGA_VSYNC ->
+		PCON_DISABLE,	NO_PUPDN	// - ->
+	       ),
+};
+
+#endif /* ! __PLATFORM_PINCONFIG_H */

platform/s5l8747x/include/platform/soc/chipid.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_SOC_CHIPID_H
+#define __PLATFORM_SOC_CHIPID_H
+
+#include <platform/chipid.h>
+#include <platform/soc/hwregbase.h>
+
+#define	rEFUSE_READ_DONE		(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x00))
+#define	rCHIPIDL			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x04))
+#define	rCHIPIDH			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x08))
+#define	rDIEIDL				(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x0C))
+#define	rDIEIDH				(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x10))
+
+extern bool     chipid_get_ecid_image_personalization_required(void);
+
+#endif /* __PLATFORM_SOC_CHIPID_H */

platform/s5l8747x/include/platform/soc/clocks.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_CLOCKS_H
+#define __PLATFORM_SOC_CLOCKS_H
+
+#include <platform/soc/hwregbase.h>
+
+#define	rCLKCON0			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x00))
+#define	rCLKCON1			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x10))
+#define	rCLKCON2			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x20))
+#define	rCLKCON3			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x30))
+#define	rCLKCON4			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x40))
+#define	rCLKCON5			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x50))
+#define	rCLKCON6			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x60))
+#define	rCLKCON7			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x70))
+#define	rPLL0PMS			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x100))
+#define	rPLL1PMS			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x104))
+#define	rPLL2PMS			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x108))
+#define	rPLL3PMS			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x10C))
+#define	rPLL0LCNT			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x110))
+#define	rPLL1LCNT			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x114))
+#define	rPLL2LCNT			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x118))
+#define	rPLL3LCNT			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x11C))
+#define	rPLLLOCKINT			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x150))
+#define	rPLLLOCK			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x154))
+#define	rPLLCON				(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x158))
+#define	rCGCON0				(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x200))
+#define	rCGCON1				(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x204))
+#define	rCGCON2				(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x208))
+#define	rCGCON3				(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x20C))
+#define	rCGCON4				(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x210))
+#define	rSWRCON				(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x250))
+#define	rRSTSR				(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x254))
+#define	rKEEPMAP			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x300))
+#define	rVERSION			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0xA00))
+#define	rMONITOR01			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x400))
+#define	rMONITOR2			(*(volatile u_int32_t *)(CLKCON_BASE_ADDR + 0x404))
+
+enum {
+	CLKGEN_CLK_OSC = 0,
+	CLKGEN_CLK_PLL0,
+	CLKGEN_CLK_PLL1,
+	CLKGEN_CLK_PLL2,
+	CLKGEN_CLK_PLL3,
+	CLKGEN_CLK_SCLK,
+	CLKGEN_CLK_FCLK,
+	CLKGEN_CLK_DCLK,
+	CLKGEN_CLK_ACLK,
+	CLKGEN_CLK_HCLK,
+	CLKGEN_CLK_PCLK,
+	CLKGEN_CLK_NCLK,
+	CLKGEN_CLK_USBPHY,
+	CLKGEN_CLK_VCLK0,
+	CLKGEN_CLK_VCLK1,
+	CLKGEN_CLK_COUNT
+};
+
+
+#endif /* ! __PLATFORM_SOC_CLOCKS_H */

platform/s5l8747x/include/platform/soc/hwclocks.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWCLOCKS_H
+#define __PLATFORM_SOC_HWCLOCKS_H
+
+#include <platform/clocks.h>
+
+#if SUPPORT_FPGA
+#define OSC_FREQ	(27000000UL)
+#else
+#define OSC_FREQ	(24000000UL)
+#endif
+
+#define CLK_FCLK	(HWCLOCK_BASE+0)
+#define CLK_ACLK	(HWCLOCK_BASE+1)
+#define CLK_HCLK	(HWCLOCK_BASE+2)
+#define CLK_PCLK	(HWCLOCK_BASE+3)
+#define CLK_VCLK0	(HWCLOCK_BASE+4)
+#define CLK_VCLK1	(HWCLOCK_BASE+5)
+#define CLK_MCLK	(HWCLOCK_BASE+6)
+#define CLK_NCLK	(HWCLOCK_BASE+7)
+#define CLK_USBPHYCLK	(HWCLOCK_BASE+8)
+#define CLK_DCLK	(HWCLOCK_BASE+9)
+
+/* S5L8747X clock gate devices */
+enum {
+	CLK_AES,
+	CLK_CHIPID,
+	CLK_DMAC0,
+	CLK_DMAC1,
+	CLK_GPIO,
+	CLK_IIC0,
+	CLK_IIC1,
+	CLK_IIC2,
+	CLK_PKE,
+	CLK_SHA1,
+	CLK_SPI0,
+	CLK_SPI1,
+	CLK_TIMER,
+	CLK_UART0,
+	CLK_UART1,
+	CLK_UART2,
+	CLK_USBOTG0,
+	CLK_USBOTG1,
+	CLK_USBPHY,
+	CLK_ROSC,
+};
+
+// USB PHY driver expects CLK_USBOTG, so give them what they want
+#define CLK_USBOTG	CLK_USBOTG1
+
+#endif /* ! __PLATFORM_SOC_HWCLOCKS_H */

platform/s5l8747x/include/platform/soc/hwisr.h

@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWISR_H
+#define __PLATFORM_SOC_HWISR_H
+
+#define EINT_G6			0	// External Interrupt 6
+#define EINT_G5			1	// External Interrupt 5		
+#define EINT_G4			2	// External Interrupt 4 	
+#define EINT_G3			3	// External Interrupt 3	 	
+#define INT_SWI			4	// SW Interrupt
+#define INT_CMMSTX		5	// COMMS TX Interrupt	
+#define INT_CMMSRX		6	// COMMS RX Interrupt
+#define INT_TIMERFIQ		7	// TIMER FIQ Interrupt
+#define INT_TIMERIRQ		8	// TIMER IRQ Interrupt 
+#define INT_SPI0		9	// SPI0 Interrupt
+#define INT_SPI1		10	// SPI1 Interrupt
+#define INT_RESERVED11		11	// Reserved
+#define INT_VP			12	// VP Interrupt
+#define INT_RGBOUT		13	// RGBOUT Interrupt
+#define INT_RESERVED14		14	// Reserved
+#define INT_RESERVED15		15	// Reserved
+#define INT_DMA0		16	// DMA0 Interrupt 
+#define INT_DMA1		17	// DMA1 Interrupt
+#define INT_USB_OTG0		18	// USB OTG0 Interrupt
+#define INT_USB_OTG1		19	// USB OTG1 Interrupt
+#define INT_RESERVED20		20	// Reserved
+#define INT_IIC0		21	// IIC0 Interrupt
+#define INT_IIC1		22	// IIC1 Interrupt
+#define INT_IIC2		23	// IIC2 Interrupt
+#define INT_UART0 		24	// UART0 Interrupt
+#define INT_UART1 		25	// UART1 Interrupt
+#define INT_UART2		26	// UART2 Interrupt
+#define INT_RESERVED27		27	// Reserved
+#define INT_RESERVED28		28	// Reserved
+#define INT_RESERVED29		29	// Reserved
+#define INT_TVOUT		30	// TVOUT Interrupt
+#define EINT_G2			31	// External Interrupt 2
+#define EINT_G1			32	// External Interrupt 1
+#define EINT_G0			33	// External Interrupt 0		
+#define INT_RESERED34		34	// Reserved
+#define INT_MFC_DEC		35	// MFC DEC Interrupt	 	
+#define INT_PKE			36	// PKE Interrupt
+#define INT_SCALER		37	// SCALER Interrupt
+#define INT_MIXER		38	// MIXER Interrupt	
+#define INT_AES			39	// AES Interrupt
+#define INT_SHA1		40	// SHA1 Interrupt 
+#define INT_PRNG		41	// PRNG Interrupt
+#define INT_SHA2		42	// SHA2 Interrupt
+#define INT_RESERVED43		43	// Reserved
+#define INT_ADC			44	// ADC Interrupt
+#define INT_RESERVED45		45	// Reserved
+#define INT_I2S0		46	// I2S Interrupt
+#define INT_RESERVED47		47	// Reserved
+#define INT_RESERVED48		48	// Reserved 
+#define INT_RESERVED49		49	// Reserved
+#define INT_SUSPEND		50	// SUSPEND Interrupt
+#define INT_WDT			51	// WDT Interrupt
+#define INT_SPDIF		52	// SPDIF Interrupt
+#define INT_RESERVED53		53	// Reserved
+#define INT_RESERVED54		54	// Reserved
+#define INT_RESERVED55		55	// Reserved
+#define INT_RESERVED56 		56	// Reserved
+#define INT_RESERVED57 		57	// Reserved
+#define INT_RESERVED58		58	// Reserved
+#define INT_HDMI_CEC		59	// HDMI CEC Interrupt
+#define INT_HDMI		60	// HDMI Interrupt
+#define INT_CLKRSTGEN		61	// CLKRSTGEN Interrupt
+#define INT_PMU			62	// PMU Interrupt
+#define INT_ARF			63	// ARF Interrupt
+
+#endif /* ! __PLATFORM_SOC_HWISR_H */

platform/s5l8747x/include/platform/soc/hwregbase.h

@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2011 - 2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_SOC_HWREGBASE_H
+#define __PLATFORM_SOC_HWREGBASE_H
+
+#ifndef HWREG_REMAP
+# define HWREG_REMAP(_x)	_x
+#endif
+
+#define AIC_VERSION 			0
+#define AIC_INT_COUNT			(192)
+#define PMGR_WDG_VERSION		0
+
+/* S5L8747X Reg Base Defs */
+
+#define SHA1_BASE_ADDR			HWREG_REMAP(0x38000000)
+
+#define AHB_BASE_ADDR			HWREG_REMAP(0x38100000)
+
+#define DMAC0_BASE_ADDR			HWREG_REMAP(0x38200000)
+#define DMAC1_BASE_ADDR			HWREG_REMAP(0x38700000)
+
+#define SHA2_BASE_ADDR			HWREG_REMAP(0x38300000)
+
+#define USBOTG0_BASE_ADDR		HWREG_REMAP(0x38400000)
+#define USB_OHCI_BASE_ADDR		HWREG_REMAP(0x38500000)
+#define USB_EHCI_BASE_ADDR		HWREG_REMAP(0x39800000)
+#define USBOTG1_BASE_ADDR		HWREG_REMAP(0x39900000)
+#define USBOTG_BASE_ADDR                (USBOTG1_BASE_ADDR)
+#define USBPHY_BASE_ADDR		HWREG_REMAP(0x3C400000)
+#define USBPHY_VERSION			(1)
+
+#define RGBOUT_BASE_ADDR		HWREG_REMAP(0x38900000)
+
+#define AES_BASE_ADDR			HWREG_REMAP(0x38C00000)
+#define AES_VERSION			(1)
+
+#define VIC_BASE_ADDR			HWREG_REMAP(0x38E00000)
+#define VIC_STRIDE			(0x00001000)
+#define VICS_COUNT			(2)
+
+#define EDGEIC_BASE_ADDR		HWREG_REMAP(0x38E02000)
+
+#define SDO_BASE_ADDR			HWREG_REMAP(0x39300000)
+
+#define AAM_BASE_ADDR			HWREG_REMAP(0x39700000)
+#define EINT_NUM_GROUPS			(7)
+#define EINTS_PER_GROUP			(32)
+
+#define SPI0_BASE_ADDR			HWREG_REMAP(0x3C300000)
+#define SPI1_BASE_ADDR			HWREG_REMAP(0x3CE00000)
+#define SPI_VERSION			(1)
+#define SPIS_COUNT			(2)
+
+#define CLKCON_BASE_ADDR		HWREG_REMAP(0x3C500000)
+
+#define IIC0_BASE_ADDR			HWREG_REMAP(0x3C600000)
+#define IIC1_BASE_ADDR			HWREG_REMAP(0x3E500000)
+#define IIC2_BASE_ADDR			HWREG_REMAP(0x3E400000)
+#define IICS_COUNT			(3)
+
+#define TIMER_BASE_ADDR			HWREG_REMAP(0x3C700000)
+#define TIMER_VERSION			(1)
+
+#define WDT_BASE_ADDR			HWREG_REMAP(0x3C800000)
+
+#define UART0_BASE_ADDR			HWREG_REMAP(0x3CC00000)
+#define UART1_BASE_ADDR			HWREG_REMAP(0x3DB00000)
+#define UART2_BASE_ADDR			HWREG_REMAP(0x3DC00000)
+#define UART_VERSION			(1)
+#define UARTS_COUNT			(3)
+
+#define GPIO_BASE_ADDR			HWREG_REMAP(0x3CF00000)
+#define GPIO_FSEL_OFFSET		(0x200)
+// There are 9 groups listed in the user manual, but the last 3
+// aren't actually implemented.
+#define GPIO_GROUP_COUNT		(6) 
+#define GPIO_PAD_SPI			(GPIO_GROUP_COUNT)
+
+#define PKE_BASE_ADDR			HWREG_REMAP(0x3D000000)
+#define PKE_SW_RESET_AVAILABLE		(1)
+
+#define CHIPID_BASE_ADDR		HWREG_REMAP(0x3D100000)
+
+#define AXI_SPINE_BASE_ADDR		HWREG_REMAP(0x3D500000)
+#define DREX_BASE_ADDR	  		HWREG_REMAP(0x3D700000)
+
+#define BUS_BASE_ADDR			HWREG_REMAP(0x3E000000)
+
+#define SRAM_MIU_BASE_ADDR		HWREG_REMAP(0x3E100000)
+
+#define HDMI_LINK_BASE_ADDR		HWREG_REMAP(0x3E200000)
+#define DITHER_VERSION			(1)
+
+#define HDMI_CEC_BASE_ADDR		HWREG_REMAP(0x3E300000)
+
+#endif /* ! __PLATFORM_SOC_HWREGBASE_H */

platform/s5l8747x/include/platform/soc/miu.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2007 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_SOC_MIU_H
+#define __PLATFORM_SOC_MIU_H
+
+#include <platform/soc/hwregbase.h>
+
+#define rAHB_MST0			(*(volatile u_int32_t *)(AHB_BASE_ADDR + 0x004))
+#define rAHB2AXIID_CON			(*(volatile u_int32_t *)(AHB_BASE_ADDR + 0x040))
+#define rAHB2AXIID0			(*(volatile u_int32_t *)(AHB_BASE_ADDR + 0x044))
+#define rAHB2AXIID1			(*(volatile u_int32_t *)(AHB_BASE_ADDR + 0x048))
+#define rAHB2AXIID2			(*(volatile u_int32_t *)(AHB_BASE_ADDR + 0x04C))
+#define rAHB2AXIID3			(*(volatile u_int32_t *)(AHB_BASE_ADDR + 0x050))
+#define rAHB2AXIID4			(*(volatile u_int32_t *)(AHB_BASE_ADDR + 0x054))
+#define rLEVEL1SEL			(*(volatile u_int32_t *)(AHB_BASE_ADDR + 0x090))
+
+#define rPWRDWN_BUS			(*(volatile u_int32_t *)(BUS_BASE_ADDR + 0x008))
+#define rREMAP				(*(volatile u_int32_t *)(BUS_BASE_ADDR + 0x00C))
+#define rDDR1				(*(volatile u_int32_t *)(BUS_BASE_ADDR + 0x010))
+#define rMFC_ARF_CON			(*(volatile u_int32_t *)(BUS_BASE_ADDR + 0x3000))
+#define rMFC_ARF_BASE_ADDR		(*(volatile u_int32_t *)(BUS_BASE_ADDR + 0x3004))
+#define rMFC_ARF_ADDR_MASK		(*(volatile u_int32_t *)(BUS_BASE_ADDR + 0x3008))
+
+enum remap_select {
+  REMAP_SRAM = 0,
+  REMAP_SDRAM
+};
+
+extern void miu_select_remap(enum remap_select sel);
+
+#endif /* ! __PLATFORM_SOC_MIU_H */

platform/s5l8747x/include/platform/soc/power.h

@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2007 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_SOC_POWER_H
+#define __PLATFORM_SOC_POWER_H
+
+#include <platform/soc/hwregbase.h>
+
+#define rPWRCONF			(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x000))
+#define rPWRCMD				(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x004))
+#define rOSCCNT				(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x038))
+#define rPLLCNT				(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x03C))
+#define rSTATESAVE0			(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x044))
+#define rSTATESAVE1			(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x048))
+#define rSTATESAVE2			(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x04C))
+#define rSTATESAVE3			(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x050))
+#define rTMCMD				(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x06C))
+#define rTMDATA				(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x070))
+#define rTMPRE				(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x074))
+#define rTMCNT				(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x078))
+#define rTMALARM			(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x07C))
+#define rSECCONF			(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x104))
+#define rVERSION			(*(volatile u_int32_t *)(AAM_BASE_ADDR + 0x108))
+
+#endif /* ! __PLATFORM_SOC_POWER_H */

platform/s5l8747x/include/platform/soc/sdo.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2008 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_SOC_SDO_H
+#define __PLATFORM_SOC_SDO_H
+
+#include <platform/soc/hwregbase.h>
+
+#define	rDAC0_SCALE			(*(volatile u_int32_t *)(SDO_BASE_ADDR + 0x1C))
+#define	rDAC1_SCALE			(*(volatile u_int32_t *)(SDO_BASE_ADDR + 0x20))
+#define	rDAC2_SCALE			(*(volatile u_int32_t *)(SDO_BASE_ADDR + 0x24))
+
+extern int sdo_init(void);
+
+#endif /* ! __PLATFORM_SOC_SDO_H */

platform/s5l8747x/include/platform/trampoline.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_TRAMPOLINE_H
+#define __PLATFORM_TRAMPOLINE_H
+
+#include <platform/memmap.h>
+#include <platform/soc/hwregbase.h>
+
+#define SECURITY_REG		(AAM_BASE_ADDR + 0x104)
+#define ROM_READ_DISABLE	(1 << 2)
+
+#endif /* ! __PLATFORM_TRAMPOLINE_H */

platform/s5l8747x/include/platform/usbconfig.h

@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2007-2009 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_USBCONFIG_H
+#define __PLATFORM_USBCONFIG_H
+
+#define USBPHY_CLK_TYPE		(2) /* Use CLKCORE */
+
+#define USBPHY_UOTGTUNE1	(0x347)
+#define USBPHY_UOTGTUNE2	(0xE3F)
+
+#define USBOTG_AHB_DMA_BURST	(DWCUSB_GAHBCFG_HBST_SINGLE)
+
+#endif /* ! __PLATFORM_USBCONFIG_H */

platform/s5l8747x/init.c

@@ -0,0 +1,855 @@
+/*
+ * Copyright (C) 2007-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <debug.h>
+#include <arch.h>
+#include <arch/arm/arm.h>
+#include <drivers/aes.h>
+#include <drivers/flash_nor.h>
+#include <drivers/iic.h>
+#include <drivers/power.h>
+#include <drivers/spi.h>
+#include <drivers/uart.h>
+#include <drivers/usb/usb_public.h>
+#include <drivers/usbphy.h>
+#include <lib/devicetree.h>
+#include <lib/env.h>
+#include <lib/random.h>
+#include <platform.h>
+#include <platform/clocks.h>
+#include <platform/gpio.h>
+#include <platform/gpiodef.h>
+#include <platform/int.h>
+#include <platform/miu.h>
+#include <platform/memmap.h>
+#include <platform/power.h>
+#include <platform/timer.h>
+#include <platform/trampoline.h>
+#include <platform/soc/chipid.h>
+#include <platform/soc/hwclocks.h>
+#include <platform/soc/miu.h>
+#include <platform/soc/power.h>
+#include <sys.h>
+#include <sys/boot.h>
+#include <target.h>
+
+static void platform_init_boot_strap(void);
+
+static uint8_t boot_debug;
+
+
+int platform_early_init(void)
+{
+#if PRODUCT_LLB || PRODUCT_IBSS
+	/* Verify that SecureROM has been disabled */
+	if (((*(volatile u_int32_t *)SECURITY_REG) & ROM_READ_DISABLE) == 0) {
+		panic("SecureROM is enabled");
+	}
+#endif
+
+#if WITH_HW_PLATFORM_POWER
+	/* initialize the s5l8747x power control driver */
+	platform_power_init();
+#endif
+
+#if WITH_HW_MIU
+	miu_init();
+#endif
+#if WITH_HW_CLOCKS
+	/* initialize the clock driver */
+	clocks_init();
+#endif
+#if WITH_HW_VIC
+	/* initialize the vic, mask all interrupts */
+	interrupt_init();
+#endif
+#if WITH_HW_TIMER
+	timer_init(0);
+#endif
+#if WITH_HW_USBPHY
+	usbphy_power_down();
+#endif
+#if WITH_HW_UART
+	/* do whatever uart initialization we need to get a simple console */
+	uart_init();
+#endif
+#if WITH_IIC
+	iic_init();
+#endif
+#if !PRODUCT_IBOOT && !PRODUCT_IBEC
+	platform_init_power();
+	
+#if WITH_BOOT_STAGE
+	boot_check_stage();
+#endif
+#endif
+
+#if WITH_BOOT_STAGE
+	boot_set_stage(kPowerNVRAMiBootStageProductStart);
+#endif
+
+#if WITH_HW_POWER
+	power_get_nvram(kPowerNVRAMiBootDebugKey, &boot_debug);
+	debug_enable_uarts(boot_debug);
+#endif
+
+#if WITH_HW_DMA
+        /* initialize the dma engine */
+        dma_init();
+#endif
+
+#if WITH_TARGET_CONFIG
+	target_early_init();
+#endif
+	
+	return 0;
+}
+
+int platform_late_init(void)
+{
+	// Chips older then B0 are not supported
+	if (platform_get_chip_revision() < 0x10) platform_not_supported();
+
+#if WITH_ENV
+	/* publish secure-boot flag for restore mode */
+	env_set_uint("secure-boot", 1, 0);
+#endif
+
+#if WITH_HW_USB && WITH_USB_MODE_RECOVERY
+	usb_early_init();
+#endif
+
+#if WITH_HW_POWER
+	power_late_init();
+#endif
+
+#if WITH_TARGET_CONFIG
+	target_late_init();
+#endif
+
+	return 0;
+}
+
+int platform_init_setup_clocks(void)
+{
+#if WITH_HW_CLOCKS
+	clocks_set_default();
+#endif
+
+	return 0;
+}
+
+int platform_init_hwpins(void)
+{
+	// need board id to select the right pinconfig
+	platform_init_boot_strap();
+
+#if WITH_HW_GPIO
+	/* finish initializing the gpio driver */
+	gpio_init_pinconfig();
+#endif
+
+	return 0;
+}
+
+int platform_init_internal_mem(void)
+{
+#if WITH_HW_MIU
+	/* initialize sram bus */
+	miu_initialize_internal_ram();
+#endif
+
+	return 0;
+}
+
+int platform_init_mainmem(bool resume)
+{
+#if WITH_HW_MIU && APPLICATION_IBOOT
+	/* initialize sdram */
+	miu_initialize_dram(resume);
+#endif
+
+	return 0;
+}
+
+int platform_init_power(void)
+{
+#if WITH_HW_POWER
+	power_init();
+#endif
+
+	return 0;
+}
+
+int platform_quiesce_hardware(enum boot_target target)
+{
+	bool quiesce_clocks = false;
+
+#if APPLICATION_SECUREROM
+	quiesce_clocks = true;
+#endif
+
+#if WITH_TARGET_CONFIG
+	target_quiesce_hardware();
+#endif
+
+#if WITH_HW_USB
+	usb_quiesce();
+#endif
+
+	switch (target) {
+		case BOOT_HALT:
+		case BOOT_DARWIN_RESTORE:
+			break;
+		case BOOT_IBOOT:
+		case BOOT_DARWIN:
+#if WITH_BOOT_STAGE
+			boot_set_stage(kPowerNVRAMiBootStageProductEnd);
+#endif
+			break;
+		case BOOT_DIAGS:
+		case BOOT_SECUREROM:
+			quiesce_clocks = true;
+			// fall through to default
+		default:
+#if WITH_BOOT_STAGE
+			boot_set_stage(kPowerNVRAMiBootStageOff);
+#endif
+			break;
+	}
+
+#if WITH_HW_DMA
+#error "Need to quiesce DMA here if a DMA API is ever added"
+#endif
+#if WITH_HW_TIMER
+	timer_stop_all();
+#endif
+#if WITH_HW_VIC
+	interrupt_mask_all();
+#endif
+
+	if (quiesce_clocks) {
+#if WITH_HW_CLOCKS
+		clocks_quiesce();
+#endif
+	}
+
+	return 0;
+}
+
+int platform_bootprep(enum boot_target target)
+{
+	u_int32_t gids = ~0, uids = ~0;	/* leave crypto keys alone by default */
+
+	/* prepare hardware for booting into various targets */
+
+#if WITH_HW_CLOCKS
+	if (target != BOOT_IBOOT) clocks_set_performance(kPerformanceHigh);
+#endif
+
+#if WITH_TARGET_CONFIG
+	target_bootprep(target);
+#endif
+
+	/* If we're not restoring, reset the watchdog-on-wake until enabled */
+	if ((boot_debug & kPowerNVRAMiBootDebugWDTWake) && (target == BOOT_DARWIN))
+	{
+		boot_debug &= ~kPowerNVRAMiBootDebugWDTWake;
+#if WITH_HW_POWER
+		power_set_nvram(kPowerNVRAMiBootDebugKey, boot_debug);
+#endif
+	}
+
+	switch (target) {
+#if APPLICATION_IBOOT
+		case BOOT_DARWIN_RESTORE:
+			platform_quiesce_display();
+		case BOOT_DARWIN:
+			if (boot_debug & kPowerNVRAMiBootDebugWDTWake)
+			    wdt_enable();
+			/* even when trusted, Darwin only gets the UID / GID1 */
+			uids = 1;
+			gids = 2;
+#if WITH_HW_MIU
+			miu_select_remap(REMAP_SDRAM);
+#endif
+			break;
+
+		case BOOT_DIAGS:
+			platform_quiesce_display();
+#if WITH_BOOT_STAGE
+			boot_clear_error_count();
+#endif
+			break;
+
+		case BOOT_IBOOT:
+#endif
+
+		case BOOT_SECUREROM:
+			platform_quiesce_display();
+#if WITH_HW_MIU
+			miu_select_remap(REMAP_SDRAM);
+#endif
+			break;
+			
+		case BOOT_UNKNOWN:
+			platform_quiesce_display();
+			break;
+
+		default:
+			; // do nothing
+	}
+
+	/* Let security override keys */
+	if (!security_allow_modes(kSecurityModeGIDKeyAccess))
+		gids = 0;
+	if (!security_allow_modes(kSecurityModeUIDKeyAccess))
+		uids = 0;
+
+	/* disable all keys not requested */
+	platform_disable_keys(~gids, ~uids);
+
+	return 0;
+}
+
+void platform_mmu_setup(bool resume)
+{
+	RELEASE_ASSERT(false == resume);
+
+	/* mark usable ram as cached/buffered */
+	arm_mmu_map_section_range(SRAM_BASE, SRAM_BASE, ROUNDUP(SRAM_BANK_LEN, MB)/MB, kARMMMUNormal, false, false);
+#if APPLICATION_IBOOT
+	arm_mmu_map_section_range(SDRAM_BASE, SDRAM_BASE, ROUNDUP(SDRAM_BANK_LEN * SDRAM_BANK_COUNT, MB)/MB, kARMMMUNormal, false, false);
+#endif
+#if APPLICATION_SECUREROM
+	arm_mmu_map_section_range(VROM_BASE, VROM_BASE, ROUNDUP(VROM_BANK_LEN, MB)/MB, kARMMMUNormal, false, false);
+#endif
+
+	/* Remap text base is to zero (for exception vectors) */
+	arm_mmu_map_section(0, TEXT_BASE, kARMMMUNormalRX, false);
+
+#ifdef MMU_NONCACHE0_SIZE
+	/* create the noncached0 mapping */
+	arm_mmu_map_section_range(MMU_NONCACHE0_VBASE, MMU_NONCACHE0_PBASE, ROUNDUP(MMU_NONCACHE0_SIZE, MB)/MB, kARMMMUStronglyOrdered, false, false);
+#endif
+
+#ifdef MMU_NONCACHE1_SIZE
+	/* create the noncached1 mapping */
+	arm_mmu_map_section_range(MMU_NONCACHE1_VBASE, MMU_NONCACHE1_PBASE, ROUNDUP(MMU_NONCACHE1_SIZE, MB)/MB, kARMMMUStronglyOrdered, false, false);
+#endif
+}
+
+int platform_init(void)
+{
+#if WITH_HW_SPI
+	spi_init();
+#endif
+
+#if APPLICATION_IBOOT
+	target_init();
+#endif
+
+	return 0;
+}
+
+int platform_debug_init(void)
+{
+#if WITH_HW_USB
+	u_int32_t usb_enabled = 1;
+#if WITH_ENV && SUPPORT_FPGA
+	usb_enabled = env_get_uint("usb-enabled", 1);
+#endif
+	if (usb_enabled) usb_init();
+#endif
+
+#if WITH_TARGET_CONFIG
+	target_debug_init();
+#endif
+
+	return 0;
+}
+
+void platform_poweroff(void)
+{
+	platform_quiesce_display();
+
+#if WITH_TARGET_CONFIG
+	target_poweroff();
+#endif
+
+#if WITH_HW_POWER
+	boot_set_stage(kPowerNVRAMiBootStageOff);
+
+	power_shutdown();
+#endif
+	for(;;);
+}
+
+u_int32_t platform_set_performance(u_int32_t performance_level)
+{
+	u_int32_t old_performance_level = kPerformanceHigh;
+
+#if WITH_HW_CLOCKS
+	old_performance_level = clocks_set_performance(performance_level);
+#endif
+
+	return old_performance_level;
+}
+
+#if WITH_DEVICETREE
+
+int platform_update_device_tree(void)
+{
+	DTNode *node;
+	u_int32_t propSize;
+	char *propName;
+	void *propData;
+	
+	// Find the cpu0 node.
+	if (FindNode(0, "cpus/cpu0", &node)) {
+		
+		// Fill in the cpu frequency
+		propName = "clock-frequency";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			 *(uint32_t *)propData = clock_get_frequency(CLK_CPU);
+		}
+		
+		// Fill in the memory frequency
+		propName = "memory-frequency";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			*(uint32_t *)propData = clock_get_frequency(CLK_MEM);
+		}
+		
+		// Fill in the bus frequency
+		propName = "bus-frequency";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			*(uint32_t *)propData = clock_get_frequency(CLK_BUS);
+		}
+		
+		// Fill in the peripheral frequency
+		propName = "peripheral-frequency";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			*(uint32_t *)propData = clock_get_frequency(CLK_PERIPH);
+		}
+		
+		// Fill in the fixed frequency
+		propName = "fixed-frequency";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			*(uint32_t *)propData = clock_get_frequency(CLK_FIXED);
+		}
+		
+		// Fill in the time base frequency
+		propName = "timebase-frequency";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			*(uint32_t *)propData = clock_get_frequency(CLK_TIMEBASE);
+		}
+	}
+
+	// Find the arm-io node
+	if (FindNode(0, "arm-io", &node)) {
+
+		// Fill in the usb-phy frequency
+		propName = "usbphy-frequency";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			 *(uint32_t *)propData = clock_get_frequency(CLK_USBPHYCLK);
+		}
+	}
+
+#if WITH_HW_PLATFORM_CHIPID
+	// Find the arm-io node
+	if (FindNode(0, "arm-io", &node)) {
+		// Fill in the chip-revision property
+		propName = "chip-revision";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			*(uint32_t *)propData = platform_get_chip_revision();
+		}
+	}
+#endif
+
+#if WITH_HW_USBPHY
+	// Fill in the otgphyctrl0 node
+	if (FindNode(0, "arm-io/otgphyctrl0", &node)) {
+		 usbphy_update_device_tree(node);
+	}
+	// Fill in the otgphyctrl1 node
+	if (FindNode(0, "arm-io/otgphyctrl1", &node)) {
+		 usbphy_update_device_tree(node);
+	}
+#endif
+
+	// Carve mfcram out of base of vram. mfcram node should already have size populated
+	if (FindNode(0, "mfcram", &node)) {
+		uint32_t *mfcramPropData;
+		propName = "reg";
+		if (FindProperty(node, &propName, &propData, &propSize)) {
+			mfcramPropData = propData;
+			if (FindNode(0, "vram", &node)) {
+				propName = "reg";
+				if (FindProperty(node, &propName, &propData, &propSize)) {
+					uint32_t *vramPropData = propData;
+					mfcramPropData[0] = vramPropData[0];
+					vramPropData[0] += mfcramPropData[1];
+					vramPropData[1] -= mfcramPropData[1];
+				}
+			}
+		}
+	}
+
+	return target_update_device_tree();
+}
+
+#endif
+
+static void platform_init_boot_strap(void)
+{
+	u_int32_t boot_strap, chip_board_id, gpio_board_id, boot_config;
+
+	// If rSTATESAVE0[0] set then boot strap already valid
+	if ((rSTATESAVE0 & 1) != 0) return;
+
+	gpio_configure_pupdn(GPIO_BOARD_ID0, GPIO_PDN);
+	gpio_configure_pupdn(GPIO_BOARD_ID1, GPIO_PDN);
+	gpio_configure_pupdn(GPIO_BOARD_ID2, GPIO_PDN);
+	gpio_configure_pupdn(GPIO_BOARD_ID3, GPIO_PDN);
+
+	gpio_configure_pupdn(GPIO_BOOT_CONFIG0, GPIO_PDN);
+	gpio_configure_pupdn(GPIO_BOOT_CONFIG1, GPIO_PDN);
+
+	gpio_configure(GPIO_BOARD_ID0, GPIO_CFG_IN);
+	gpio_configure(GPIO_BOARD_ID1, GPIO_CFG_IN);
+	gpio_configure(GPIO_BOARD_ID2, GPIO_CFG_IN);
+	gpio_configure(GPIO_BOARD_ID3, GPIO_CFG_IN);
+
+	gpio_configure(GPIO_BOOT_CONFIG0, GPIO_CFG_IN);
+	gpio_configure(GPIO_BOOT_CONFIG1, GPIO_CFG_IN);
+
+#if !SUPPORT_FPGA
+	platform_power_spin(100); // Wait 100us
+#endif
+
+	chip_board_id = chipid_get_board_id();
+
+	gpio_board_id =
+		(gpio_read(GPIO_BOARD_ID3) << 3) |
+		(gpio_read(GPIO_BOARD_ID2) << 2) |
+		(gpio_read(GPIO_BOARD_ID1) << 1) |
+		(gpio_read(GPIO_BOARD_ID0) << 0);
+
+	boot_config =
+		(gpio_read(GPIO_BOOT_CONFIG1) << 1) |
+		(gpio_read(GPIO_BOOT_CONFIG0) << 0);
+
+	gpio_configure(GPIO_BOARD_ID0, GPIO_CFG_DFLT);
+	gpio_configure(GPIO_BOARD_ID1, GPIO_CFG_DFLT);
+	gpio_configure(GPIO_BOARD_ID2, GPIO_CFG_DFLT);
+	gpio_configure(GPIO_BOARD_ID3, GPIO_CFG_DFLT);
+
+	gpio_configure(GPIO_BOOT_CONFIG0, GPIO_CFG_DFLT);
+	gpio_configure(GPIO_BOOT_CONFIG1, GPIO_CFG_DFLT);
+
+	boot_strap = (((chip_board_id << 4) | gpio_board_id) << 16) |
+		     (boot_config << 8) |
+		     (0x01 << 0);
+
+	rSTATESAVE0 = (rSTATESAVE0 & 0xFF000000) | (boot_strap & 0x00FFFFFF);
+}
+
+u_int32_t platform_get_board_id(void)
+{
+	u_int32_t board_id;
+
+	ASSERT((rSTATESAVE0 & kPlatformScratchFlagBootStrap) != 0);
+
+	board_id = (rSTATESAVE0 >> 16) & 0xFF;
+
+#if SUPPORT_FPGA
+	board_id = 0x3F;
+#endif
+
+	return board_id;
+}
+
+u_int32_t platform_get_boot_config(void)
+{
+	u_int32_t boot_config;
+
+	boot_config = (rSTATESAVE0 >> 8) & 0xFF;
+
+	return boot_config;
+}
+
+bool platform_get_boot_device(int32_t index, enum boot_device *boot_device, u_int32_t *boot_flag, u_int32_t *boot_arg)
+{
+	u_int32_t boot_config = platform_get_boot_config();
+
+	/* S5L8747X supports one boot device then USB-DFU per boot config.
+	   Unlike other platforms, the USB-DFU device is selectable. */
+
+#ifdef HACK_BOOT_CONFIG_OVERRIDE
+	boot_config = HACK_BOOT_CONFIG_OVERRIDE;
+#endif
+	
+	/* If the index is not zero force DFU mode */
+	if (index != 0) index = 1;
+
+	switch (boot_config) {
+		case 0: /* SPI 0, then USB0 FDU */
+		case 1: /* SPI 0, then USB1 DFU */
+			if (index == 0) {
+				*boot_device = BOOT_DEVICE_SPI;
+				*boot_flag = 0;
+				*boot_arg = 0;
+			} else {
+				*boot_device = BOOT_DEVICE_USBDFU;
+				*boot_flag = 0;
+				*boot_arg = 0;
+			}
+			return true;
+
+		case 2: /* SPI 0, then USB0 FDU with TEST_MODE */
+		case 3: /* SPI 0, then USB1 DFU with TEST_MODE */
+			if (index == 0) {
+				*boot_device = BOOT_DEVICE_SPI;
+				*boot_flag = BOOT_FLAG_TEST_MODE;
+				*boot_arg = 0;
+			} else {
+				*boot_device = BOOT_DEVICE_USBDFU;
+				*boot_flag = BOOT_FLAG_TEST_MODE;
+				*boot_arg = 0;
+			}
+			return true;
+
+		default:
+			return false;
+	}
+}
+
+/*
+ *  boot_interface_pin tables
+ *    tables are executed in order for disable and reverse order for enable
+ *
+ */
+
+struct boot_interface_pin {
+	gpio_t	  pin;
+	u_int32_t enable;
+	u_int32_t disable;
+};
+
+#if WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI
+#ifdef SPI_NOR0
+static const struct boot_interface_pin spi0_boot_interface_pins[] =
+{
+#if SUPPORT_FPGA
+	{ GPIO( 1, 3), GPIO_CFG_FUNC1, GPIO_CFG_DFLT },	// SPI0_CEN
+#else
+	{ GPIO( 1, 3), GPIO_CFG_OUT_1, GPIO_CFG_DFLT },	// SPI0_CEN
+#endif
+	{ GPIO( 1, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// SPI0_CLK
+	{ GPIO( 1, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// SPI0_MOSI
+	{ GPIO( 1, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT }	// SPI0_MISO
+};
+#endif
+#endif /* WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI */
+
+void platform_enable_boot_interface(bool enable, enum boot_device boot_device, u_int32_t boot_arg)
+{
+	const struct boot_interface_pin *pins = 0;
+	u_int32_t cnt, func, pin_count = 0;
+	gpio_t pin;
+
+	switch (boot_device) {
+#if WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI
+		case BOOT_DEVICE_SPI :
+#ifdef SPI_NOR0
+			if (boot_arg == 0) {
+				pins = spi0_boot_interface_pins;
+				pin_count = (sizeof(spi0_boot_interface_pins) / sizeof(spi0_boot_interface_pins[0]));
+			}
+#endif
+			break;
+#endif /* WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI */
+
+#if WITH_USB_DFU
+		case BOOT_DEVICE_USBDFU :
+			/* USB is always configured */
+			break;
+#endif /* WITH_USB_DFU */
+
+		default :
+			break;
+	}
+
+	for (cnt = 0; cnt < pin_count; cnt++) {
+		if (enable) {
+			pin = pins[pin_count - 1 - cnt].pin;
+			func = pins[pin_count - 1 - cnt].enable;
+		} else {
+			pin = pins[cnt].pin;
+			func = pins[cnt].disable;
+		}
+
+		dprintf(DEBUG_INFO, "platform_enable_boot_interface: %x, %x\n", pin, func);
+		gpio_configure(pin, func);
+	}
+}
+
+u_int64_t platform_get_nonce(void)
+{
+	u_int64_t	nonce;
+	u_int32_t	*nonce_words = (u_int32_t *)&nonce;
+	u_int8_t	*nonce_bytes = (u_int8_t *)&nonce;
+
+	// If rSTATESAVE0[1] set then the nonce has already been generated
+	if ((rSTATESAVE0 & kPlatformScratchFlagNonce) == 0) {
+#if WITH_RANDOM
+		if (random_get_bytes(nonce_bytes, sizeof(nonce)) != 0)
+#endif
+		{
+			memset(nonce_bytes, 0, sizeof(nonce));
+		}
+
+		rSTATESAVE2 = nonce_words[0];
+		rSTATESAVE3 = nonce_words[1];
+
+		rSTATESAVE0 |= kPlatformScratchFlagNonce;
+	} else {
+		nonce_words[0] = rSTATESAVE2;
+		nonce_words[1] = rSTATESAVE3;
+	}
+
+	return nonce;
+}
+
+bool platform_get_ecid_image_personalization_required(void)
+{
+	return chipid_get_ecid_image_personalization_required();
+}
+
+u_int32_t platform_get_osc_frequency(void)
+{
+	return chipid_get_osc_frequency();
+}
+
+u_int32_t platform_get_base_soc_voltage(void)
+{
+	return 1200;
+}
+
+int platform_get_soc_voltages(u_int32_t count, u_int32_t *voltages)
+{
+	u_int32_t cnt;
+
+	if (voltages == 0) return -1;
+
+	for (cnt = 0; cnt < count; cnt++) {
+		voltages[cnt] = platform_get_base_soc_voltage();
+	}
+
+	return 0;
+}
+
+bool platform_get_usb_cable_connected(void)
+{
+#if WITH_HW_USBPHY
+	return usbphy_is_cable_connected();
+#else
+	return false;
+#endif
+}
+
+void platform_set_dfu_status(bool dfu)
+{
+	gpio_write(GPIO_DFU_STATUS, dfu);
+}
+
+bool platform_get_force_dfu(void)
+{
+	return gpio_read(GPIO_FORCE_DFU);
+}
+
+int platform_translate_key_selector(u_int32_t key_selector, u_int32_t *key_opts)
+{
+	switch (key_selector) {
+		case IMAGE_KEYBAG_SELECTOR_PROD :
+			break;
+
+		default :
+			return -1;
+	}
+
+	*key_opts = AES_KEY_TYPE_GID0 | AES_KEY_SIZE_128;
+
+	return 0;
+}
+
+#if APPLICATION_IBOOT
+u_int64_t platform_get_memory_size(void)
+{
+        return (2 * 128 * 1024 * 1024);
+}
+
+uintptr_t platform_get_memory_region_base_optional(memory_region_type_t region)
+{
+	uintptr_t base;
+
+	switch (region) {
+		case kMemoryRegion_Panic:
+			base = SDRAM_BASE + platform_get_memory_size() - PANIC_SIZE;
+			break;
+
+		case kMemoryRegion_Display:
+			base = SDRAM_BASE + platform_get_memory_size() - PURPLE_GFX_MEMORY_LEN - PANIC_SIZE;
+			break;
+
+		case kMemoryRegion_Kernel:
+			base = SDRAM_BASE;
+			break;
+
+		default:
+			base = (uintptr_t)-1;
+	}
+
+	return base;
+}
+
+size_t platform_get_memory_region_size_optional(memory_region_type_t region)
+{
+	size_t size;
+
+	switch (region) {
+		case kMemoryRegion_Panic:
+			size = PANIC_SIZE;
+			break;
+
+		case kMemoryRegion_Display:
+			size = PURPLE_GFX_MEMORY_LEN;
+			break;
+
+#if defined(SLEEP_TOKEN_BUFFER_SIZE)
+		case kMemoryRegion_SleepToken:
+			size = SLEEP_TOKEN_BUFFER_SIZE;
+			break;
+
+#endif
+
+		case kMemoryRegion_Kernel:
+			size = platform_get_memory_size() - PURPLE_GFX_MEMORY_LEN - PANIC_SIZE;
+			break;
+
+		default:
+			size = (size_t)-1;
+	}
+
+	return size;
+}
+
+#endif
+

platform/s5l8747x/miu/miu.c

@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <arch.h>
+#include <drivers/miu.h>
+#include <platform.h>
+#include <platform/miu.h>
+#include <platform/clocks.h>
+#include <platform/memmap.h>
+#include <platform/power.h>
+#include <platform/soc/hwclocks.h>
+#include <platform/soc/miu.h>
+#include <platform/soc/power.h>
+#include <sys.h>
+
+/* memory controller stuff */
+
+#if APPLICATION_IBOOT
+
+int miu_initialize_dram(bool resume)
+{
+#if APPLICATION_IBOOT
+	/* Turn off alias from 0x10000000 to 0x08000000 */
+	rDDR1 = 1;
+
+	/* bring up sdram */
+	mcu_initialize_dram(resume);
+#endif	
+	return 0;
+}
+
+#endif /* APPLICATION_IBOOT */
+
+int miu_initialize_internal_ram(void)
+{
+#if APPLICATION_SECUREROM
+	// Ensure that rSTATESAVE0 and rSTATESAVE1 get cleared
+	rSTATESAVE0 = 0;
+	rSTATESAVE1 = 0;
+#endif /* APPLICATION_SECUREROM */
+
+	// Save the Security Epoch in the top byte of SAVESTATE0
+	rSTATESAVE0 &= ~0xFF000000;
+	rSTATESAVE0 |= (platform_get_security_epoch()) << 24;
+
+	return 0;
+}
+
+void 
+miu_select_remap(enum remap_select sel)
+{
+	switch (sel) {
+		case REMAP_SRAM:
+			rREMAP = (rREMAP & ~3) | (1 << 0) | (1 << 1); // remap, remap_sel = 1
+			break;
+		case REMAP_SDRAM:
+			rREMAP = (rREMAP & ~3) | (1 << 0) | (0 << 1); // remap, remap_sel = 0
+			break;
+	}
+}
+
+void
+miu_setup_mfc_address_filter(void)
+{
+#if ((PURPLE_GFX_MEMORY_LEN + PANIC_SIZE) & 0xFFFFF) != 0
+#error "PurpleGfxMemory must be 1 MB-aligned"
+#endif
+	uint32_t range_end = SDRAM_BASE + (uint32_t)platform_get_memory_size();
+	uint32_t range_base = range_end - PANIC_SIZE - PURPLE_GFX_MEMORY_LEN;
+	rMFC_ARF_BASE_ADDR = range_base;
+	rMFC_ARF_ADDR_MASK = ~(range_end - range_base) & 0xFFF00000;
+	rMFC_ARF_CON = 1;
+}
+
+int miu_init(void)
+{
+#if APPLICATION_IBOOT && !PRODUCT_IBEC
+	// Verify that the Security Epoch in STATESAVE0 matches
+	if ((rSTATESAVE0 >> 24) != platform_get_security_epoch()) {
+		panic("miu_init: Epoch Mismatch\n");
+	}
+#endif
+
+	/* remap whatever bank of ram we're in to zero */
+	if (TEXT_BASE == SRAM_BASE)
+		miu_select_remap(REMAP_SRAM);
+	else if ((TEXT_BASE >= SDRAM_BASE) && (TEXT_BASE < SDRAM_END))
+		miu_select_remap(REMAP_SDRAM);
+
+#if APPLICATION_IBOOT
+	miu_setup_mfc_address_filter();
+#endif
+
+	return 0;
+}

platform/s5l8747x/miu/rules.mk

@@ -0,0 +1,15 @@
+# Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+#
+# This document is the property of Apple Computer, Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Computer, Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_MIU=1
+
+ALL_OBJS += $(LOCAL_DIR)/miu.o

platform/s5l8747x/pmgr/pmgr.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <arch.h>
+#include <platform.h>
+#include <platform/timer.h>
+#include <platform/power.h>
+#include <platform/soc/power.h>
+#include <sys.h>
+#include <sys/boot.h>
+#include <sys/menu.h>
+
+
+void platform_power_init(void)
+{
+	// configure the AAM clock
+	rPWRCONF = (0 << 25) | (1<<24) | (0<<20) |		// AAM clock 12MHz, prescalar on /1
+		   (2<<16) |					// enable 2 synch flip flops
+		   (1<<14) |					// enable all OSCs in normal mode
+		   (1<<13) |					// enable all OSCs in normal mode
+		   (1<<12) |					// enable all OSCs in normal mode
+		   (1<<1);
+
+	rTMCMD = 0;    	       	  				// Stop the AAM timer
+	rTMPRE = platform_get_osc_frequency() / 1000000;	// Set timer prescale for 1 MHz
+}
+
+void platform_power_spin(u_int32_t usecs)
+{
+	rTMDATA = usecs;
+	rTMCMD = (1 << 1) | (1 << 0);				// Clear and start the AAM timer
+
+	while ((rTMALARM & 1) == 0);				// Wait for the timer to fire
+
+	rTMCMD = (1 << 1) | (0 << 0);				// Clear and stop the AAM timer
+}
+
+void platform_disable_keys(u_int32_t gid, u_int32_t uid)
+{
+	if (gid) rSECCONF = 1 << 1;
+	if (uid) rSECCONF = 1 << 0;
+}
+
+

platform/s5l8747x/pmgr/rules.mk

@@ -0,0 +1,17 @@
+# Copyright (C) 2007 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_CLOCKS=1 \
+	WITH_HW_PLATFORM_POWER=1 \
+	WITH_HW_POWER_GATING=0
+
+ALL_OBJS += $(LOCAL_DIR)/pmgr.o

platform/s5l8747x/rules.mk

@@ -0,0 +1,92 @@
+# Copyright (C) 2011-2013 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+GLOBAL_INCLUDES += $(LOCAL_DIR)/include
+
+# modules implied by this platform
+MODULES		+= \
+	platform/defaults \
+	platform/generic \
+	arch/$(ARCH)
+
+##############################################################################
+# Code running on the main CPU
+#
+ifeq ($(PLATFORM_VARIANT),)
+
+ARM_ARCH := armv7
+ARM_CPU := cortex-a5
+
+# Devmap chip ID based on sub-platform identifier
+ifeq ($(SUB_PLATFORM),s5l8747x)
+DEVMAP_CHIP_ID := 8747
+endif
+
+MAX_DFU_SIZE	:=	98304
+
+ifeq ($(TEXT_BANK),srom)
+TEXT_BASE := 0x00000000
+endif
+ifeq ($(TEXT_BANK),sram)
+TEXT_BASE := 0x22000000
+endif
+ifeq ($(TEXT_BANK),sdram)
+TEXT_BASE := 0x0FF00000
+endif
+
+OPTIONS += \
+	WITH_CLASSIC_SUSPEND_TO_RAM=1 \
+	WITH_LEGACY_PANIC_LOGS=1 \
+	WITH_NON_COHERENT_DMA=1 \
+	WITH_ROM_TRAMPOLINE=1 \
+	WITH_CONJOINED_USB_PHYS=1 \
+	PLATFORM_ENTROPY_RATIO=60 \
+	PLATFORM_IRQ_COUNT=192 \
+	TEXT_BASE="$(TEXT_BASE)" \
+	TEXT_FOOTPRINT="$(TEXT_FOOTPRINT)"
+
+GLOBAL_LDFLAGS += -seg1addr $(TEXT_BASE)
+
+ifeq ($(APPLICATION),SecureROM)
+# This selects the start of the DATA segment and the end of the INSECURE_MEMORY area
+DATA_BASE := 0x22019000
+
+OPTIONS += \
+	DATA_BASE="$(DATA_BASE)"
+
+GLOBAL_LDFLAGS += -segaddr __DATA $(DATA_BASE)
+
+# Simulation trace uses STATESAVE2 and STATESAVE3
+# We have to duplicate the literal values here as debug.h is 
+# not necessarily going have hwregbase.h in scope all the time.
+OPTIONS	+= \
+	SIMULATION_TRACE_IP_REGISTER=0x3970004c \
+	SIMULATION_TRACE_PARAMETER_REGISTER=0x39700050
+endif
+
+# SecureROM turns off the timers on G1, so turn them back on as early
+# as possible to get accurate measurements of boot time.
+# By default only do this in development builds though.
+ifeq ($(APPLICATION),iBoot)
+ifeq ($(BUILD),DEVELOPMENT)
+OPTIONS += \
+	PLATFORM_START_FUNCTION=_platform_start
+endif
+endif
+
+ALL_OBJS += \
+	 $(LOCAL_DIR)/asm.o \
+	 $(LOCAL_DIR)/init.o
+
+MODULES_ELIDE += lib/libcorecrypto
+
+endif
+

platform/s5l8940x/amc/amc_s5l8940x.c

@@ -0,0 +1,269 @@
+/*
+ * Copyright (C) 2009-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#include <drivers/amc/amc.h>
+#include <drivers/amc/amc_phy.h>
+#include <drivers/amc/amc_regs.h>
+#include <drivers/dram.h>
+#include <drivers/miu.h>
+#include <sys.h>
+#include <debug.h>
+
+int mcu_initialize_dram (bool resume)
+{
+	return amc_init(resume);
+}
+
+void mcu_bypass_prep (int step)
+{
+	amc_phy_bypass_prep(step);
+}
+
+uint64_t mcu_get_memory_size (void)
+{
+	return amc_get_memory_size();
+}
+
+void amc_configure_address_decoding_and_mapping (void)
+{
+	amc_configure_default_address_decoding_and_mapping();
+}
+
+void amc_enable_slow_boot (bool enable)
+{
+	int slow_freqsel;
+	
+	if (enable) {
+		if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
+			rAMC_FREQSEL = amc_params.freqsel;
+			return;
+		}
+
+		slow_freqsel = 3;
+		rAMC_BOOTCLK = (amc_params.bootclkdivsr << 8) | 1;
+		spin(5);
+		rAMC_FREQSEL = slow_freqsel;
+		amc_phy_scale_dll(slow_freqsel, amc_params.bootclkdivsr);		
+	} else {
+		if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
+			return;
+		}
+		
+		rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_small;
+		spin(2);
+
+		rAMC_BOOTCLK &= ~1;
+		spin(5);
+		rAMC_FREQSEL = amc_params.freqsel;
+		amc_phy_scale_dll(amc_params.freqsel, 1);
+
+		rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_guided;
+	}
+}
+
+void amc_finalize (bool resume)
+{
+	uint8_t odts;
+
+#if SUPPORT_FPGA
+	rAMC_PWRMNGTEN |= 0x00000001;			// Sharing clocks between channels so do not enable clock stopping for PD or SR
+#else // SUPPORT_FPGA
+	rAMC_PWRMNGTEN |= 0x00001001;
+#endif // SUPPORT_FPGA
+
+	amc_mrcmd(MR_READ, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x4, (uintptr_t)&odts);
+	rAMC_ODTS         = 0x00010080;			// [16] => TempDrtEn, [9:0] RdIntrvl XXX based on tREFI
+
+	rAMC_PWRMNGTEN |= 0x00010000;			// Enable srclkoff as well
+	
+	if (!resume) {
+		amc_enable_autorefresh();
+	}
+	
+#if !SUPPORT_FPGA
+	// Turn of Fast Critical Word Forwarding feature and AIU CWF feature
+	// Disabled for NRT <rdar://problem/9416881>
+	rAMC_AIUPRT_RD_CWF     = 0x0001011f;
+	rAMC_QBRPARAM          = 0x00020200;
+	rAMC_QBREN             = 0x00111001;
+#endif	
+}
+
+void amc_dram_workarounds (bool resume)
+{
+	const struct amc_memory_device_info *dev_info;
+	uint32_t chip_id = platform_get_chip_id();
+	uint8_t i;
+	
+	dev_info = amc_get_memory_device_info();
+	
+	switch (dev_info->vendor_id) {
+	case JEDEC_MANUF_ID_SAMSUNG:
+
+		// <rdar://problem/9454992> H4P Samsung 35nm LPDDR2 Transition for N94
+		// TMRS for Samsung 46nm part only
+		if ((chip_id == 0x8940) && (!resume) && (dev_info->rev_id == 0)) {
+			// Test MRS Entry
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xff);
+
+			// Apply Samsung workaround <rdar://problem/9032765>
+
+			// Column Select Line pull in (230ps) TMRS(1)
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x80);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x04);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x08);
+
+			// Latch command
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
+
+			// Column Select Line pull in (230ps) TMRS(2)
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x40);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x01);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
+
+			// Latch command
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
+		}
+			
+		// <rdar://problem/11060879> Samsung 3xnm DRAMs - not functional
+		else if ((chip_id == 0x8942) && (!resume) && (dev_info->rev_id == 1) && (dev_info->rev_id2 == 0)) {
+			// Test MRS Entry
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xff);
+				
+			// PDL_M(-500ps)
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x80);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x01);
+			
+			// Latch Command
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
+			amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
+		}
+
+		break;
+
+	case JEDEC_MANUF_ID_HYNIX:
+
+		if (dev_info->rev_id == 0) {
+			if (!resume) {
+				// Test MRS Exit "just in case" <rdar://problem/8769095>
+				amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
+
+				// Apply Hynix cold clamp disable workaround <rdar://problem/8907487>
+				// (but only for revid2 == 0 <rdar://problem/8943860>)
+				if ((chip_id == 0x8940) && (dev_info->rev_id2 == 0)) {
+					// Test MRS Entry
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xb0);
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xe0);
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x90);
+
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xa2);
+				}
+
+				// IOSTBP Start Time control (600ps delay)
+				if ((chip_id == 0x8942) && (dev_info->density == JEDEC_DENSITY_1Gb)) {
+					// Test MRS Entry
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xb0);
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xe0);
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x90);
+					
+					for (i = 0; i < 13; i++) {
+						amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x99);
+					}
+				}
+			}
+
+#if !SUB_TARGET_K93 && !SUB_TARGET_K94 && !SUB_TARGET_K95 && !SUB_TARGET_J33
+			// <rdar://problem/9585266> H4G UM Update: Modified setting for tMRR timing parameter
+			// override tMRR to 3 cycles (only if performing dynamic calibration)
+			if (dev_info->density == JEDEC_DENSITY_2Gb) {
+				rAMC_MODE_FREQ(0) = amc_params.freq[0].modereg | 0x3;
+			}
+#endif
+ 		} else if ((dev_info->rev_id == 1) && (dev_info->rev_id2 == 0)) {
+			
+			// <rdar://problem/11059277> Hynix 3xnm workaround solution
+			if ((chip_id == 0x8942) && (!resume)) {
+				// Test MRS Entry
+				amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xb0);
+				amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xe0);
+				amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x90);
+				
+				// Yi Enable +1 step
+				for (i = 0; i < 4; i++) {
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xf1);
+				}
+				
+				// Yi Pulse +1 step
+				for (i = 0; i < 4; i++) {
+					amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x94);
+				}
+			}
+		}
+		break;
+
+	default:
+		break;
+	}
+}
+
+// Shift dq offset as needed.
+// In the future, it's possible the shift value changes based on SOC or DRAM vendor.
+// Thus, we need to have this function per SOC.
+void amc_dram_shift_dq_offset (int8_t *dq_offset, uint8_t num_bytes) {
+	int8_t shift_val;
+	uint8_t i;
+	const struct amc_memory_device_info *dev_info;
+    uint32_t chip_id = platform_get_chip_id();
+
+    // Do nothing for H4P
+	if (chip_id == 0x8940)
+        return;
+
+    // <rdar://problem/11802718> H4A: Need additional DQ WR/RD static offsets
+    dev_info = amc_get_memory_device_info();
+    shift_val = 0;
+    
+    switch (dev_info->vendor_id) {			
+        
+        case JEDEC_MANUF_ID_SAMSUNG:
+        case JEDEC_MANUF_ID_HYNIX:
+            
+            // -3 step shift for DRAMs not used in K93A or J33
+            if (dev_info->rev_id > 0)
+                shift_val = -3;
+
+            break;            
+
+        case JEDEC_MANUF_ID_ELPIDA:
+            
+            // -3 step shift for DRAMs not used in K93A or J33
+            if (dev_info->rev_id > 1)
+                shift_val = -3;
+
+            break;
+			
+        default:
+            dprintf(DEBUG_INFO, "Not applyig any shift to dq offsets for vendor: %d\n", dev_info->vendor_id);
+            break;
+    }
+    
+    for (i = 0; i < num_bytes; i++)
+        dq_offset[i] += shift_val;
+}

platform/s5l8940x/amc/amc_s5l8947x.c

@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2010-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#include <drivers/amc/amc.h>
+#include <drivers/amc/amc_phy.h>
+#include <drivers/amc/amc_regs.h>
+#include <drivers/dram.h>
+#include <drivers/miu.h>
+#include <sys.h>
+
+int mcu_initialize_dram (bool resume)
+{
+	return amc_init(resume);
+}
+
+void mcu_bypass_prep (int step)
+{
+	amc_phy_bypass_prep(step);
+}
+
+uint64_t mcu_get_memory_size (void)
+{
+	return amc_get_memory_size();
+}
+
+void amc_configure_address_decoding_and_mapping (void)
+{
+	amc_configure_default_address_decoding_and_mapping();
+}
+
+void amc_enable_slow_boot (bool enable)
+{
+	int slow_freqsel;
+	
+	if (enable) {
+		if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
+			rAMC_FREQSEL = amc_params.freqsel;
+			return;
+		}
+
+		slow_freqsel = 3;
+		rAMC_BOOTCLK = (amc_params.bootclkdivsr << 8) | 1;
+		spin(5);
+		rAMC_FREQSEL = slow_freqsel;
+		amc_phy_scale_dll(slow_freqsel, amc_params.bootclkdivsr);		
+	} else {
+		if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
+			return;
+		}
+		
+		rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_small;
+		spin(2);
+
+		rAMC_BOOTCLK &= ~1;
+		spin(5);
+		rAMC_FREQSEL = amc_params.freqsel;
+		amc_phy_scale_dll(amc_params.freqsel, 1);
+
+		rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_guided;
+	}
+}
+
+void amc_finalize (bool resume)
+{
+	uint8_t odts;
+
+#if SUPPORT_FPGA
+	rAMC_PWRMNGTEN |= 0x00000001;			// Sharing clocks between channels so do not enable clock stopping for PD or SR
+#else
+	rAMC_PWRMNGTEN |= 0x00011011;
+#endif
+
+	rAMC_AREFPARAM    |= (0x00001000);		// Turn on freq change waiting for refresh and self-refresh exit
+
+	amc_mrcmd(MR_READ, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x4, (uintptr_t)&odts);
+	rAMC_ODTS         = 0x00010320;			// [16] => TempDrtEn, [9:0] RdIntrvl XXX based on tREFI
+
+	if (!resume) {
+		amc_enable_autorefresh();
+	}
+
+#if SUPPORT_FPGA
+	rAMC_FREQSEL = amc_params.freqsel;
+#endif
+
+#if !SUPPORT_FPGA
+	// Turn of Fast Critical Word Forwarding feature and AIU CWF feature
+	// Disabled for NRT <rdar://problem/9416881>
+	rAMC_AIUPRT_RD_CWF     = 0x00161600;
+	rAMC_QBRPARAM          = 0x00810000;
+	rAMC_QBREN             = 0x00111001;
+#endif
+}
+
+void amc_dram_workarounds (bool resume)
+{
+	// XXX - Possibly look in s5l8950x amc.c to see possible workarounds.
+	return;
+}
+
+// Shift dq offset as needed.
+// In the future, it's possible the shift value changes based on SOC or DRAM vendor.
+// Thus, we need to have this function per SOC.
+void amc_dram_shift_dq_offset (int8_t *dq_offset, uint8_t num_bytes) {
+	int8_t shift_val;
+	uint8_t i;
+	const struct amc_memory_device_info *dev_info;
+	
+	dev_info = amc_get_memory_device_info();
+	
+	switch (dev_info->vendor_id) {			
+		case JEDEC_MANUF_ID_HYNIX:
+		case JEDEC_MANUF_ID_SAMSUNG:
+		case JEDEC_MANUF_ID_ELPIDA:
+			
+			// shift 2 steps
+			shift_val = -2;
+			break;
+			
+		default:
+			shift_val = 0;
+			break;
+	}
+	
+	for (i = 0; i < num_bytes; i++)
+		dq_offset[i] += shift_val;	
+}

platform/s5l8940x/amc/rules.mk

@@ -0,0 +1,21 @@
+# Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_AMC=1
+
+ifneq ($(SUB_PLATFORM), s5l8947x)
+ALL_OBJS += \
+	$(LOCAL_DIR)/amc_s5l8940x.o
+else
+ALL_OBJS += \
+	$(LOCAL_DIR)/amc_s5l8947x.o
+endif

platform/s5l8940x/chipid/chipid.c

@@ -0,0 +1,288 @@
+/*
+ * Copyright (C) 2009-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <lib/env.h>
+#include <platform.h>
+#include <platform/soc/chipid.h>
+#include <platform/soc/hwclocks.h>
+
+#if SUPPORT_FPGA
+#define _rCFG_FUSE0				(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x00))
+#undef rCFG_FUSE0
+// XXX ECID (1 << 7)?
+// XXX double-check memory values
+#define rCFG_FUSE0		((0 << 31) | (3 << 28) | (0xE << 24) | (2 << 22) | \
+			 (0 << 9) | (1 << 8) | (3 << 4) | (kPlatformSecurityDomainDarwin << 2) | (0 << 1) | (0 << 0) | \
+			 _rCFG_FUSE0)
+#endif
+
+#if SUB_PLATFORM_S5L8940X
+#define DEFAULT_SOC_VOLTAGE_LOW		1000
+#define DEFAULT_SOC_VOLTAGE_MED		1100
+#define DEFAULT_SOC_VOLTAGE_HIGH	1200
+#define DEFAULT_CPU_VOLTAGE_LOW		1000
+#define DEFAULT_CPU_VOLTAGE_MED		1150
+#define DEFAULT_CPU_VOLTAGE_HIGH	1250
+#define BASE_SOC_VOLTAGE_LOW		875
+#define BASE_SOC_VOLTAGE_MED		975
+#define BASE_SOC_VOLTAGE_HIGH		1075
+#define BASE_CPU_VOLTAGE_LOW		875
+#define BASE_CPU_VOLTAGE_MED		975
+#define BASE_CPU_VOLTAGE_HIGH		1075
+#elif SUB_PLATFORM_S5L8942X
+#define DEFAULT_SOC_VOLTAGE_LOW		925
+#define DEFAULT_SOC_VOLTAGE_MED		1000
+#define DEFAULT_SOC_VOLTAGE_HIGH	1100
+#define DEFAULT_CPU_VOLTAGE_LOW		925
+#define DEFAULT_CPU_VOLTAGE_MED		1025
+#define DEFAULT_CPU_VOLTAGE_HIGH	1125
+#define BASE_SOC_VOLTAGE_LOW		800
+#define BASE_SOC_VOLTAGE_MED		825
+#define BASE_SOC_VOLTAGE_HIGH		925
+#define BASE_CPU_VOLTAGE_LOW		800
+#define BASE_CPU_VOLTAGE_MED		875
+#define BASE_CPU_VOLTAGE_HIGH		975
+#elif SUB_PLATFORM_S5L8947X
+#define DEFAULT_SOC_VOLTAGE_LOW		1100
+#define DEFAULT_SOC_VOLTAGE_MED		1100
+#define DEFAULT_SOC_VOLTAGE_HIGH	1100
+#define DEFAULT_CPU_VOLTAGE_LOW		1100
+#define DEFAULT_CPU_VOLTAGE_MED		1100
+#define DEFAULT_CPU_VOLTAGE_HIGH	1100
+#define BASE_SOC_VOLTAGE_LOW		1075
+#define BASE_SOC_VOLTAGE_MED		1075
+#define BASE_SOC_VOLTAGE_HIGH		1075
+#define BASE_CPU_VOLTAGE_LOW		1075
+#define BASE_CPU_VOLTAGE_MED		1075
+#define BASE_CPU_VOLTAGE_HIGH		1075
+#endif
+
+bool chipid_get_production_mode(void)
+{
+	return ((rCFG_FUSE0 >> 0) & 1) != 0;
+}
+
+void chipid_clear_production_mode(void)
+{
+#if SUPPORT_FPGA
+	_rCFG_FUSE0 &= ~1;
+#else
+	rCFG_FUSE0 &= ~1;
+#endif
+}
+
+bool chipid_get_secure_mode(void)
+{
+	return ((rCFG_FUSE0 >> 1) & 1) != 0;
+}
+
+u_int32_t chipid_get_security_domain(void)
+{
+	return (rCFG_FUSE0 >> 2) & 3;
+}
+
+u_int32_t chipid_get_board_id(void)
+{
+	return (rCFG_FUSE0 >> 4) & 3;
+}
+
+bool chipid_get_ecid_image_personalization_required(void)
+{
+	return ((rCFG_FUSE0 >> 7) & 1) != 0;
+}
+
+u_int32_t chipid_get_minimum_epoch(void)
+{
+	return (rCFG_FUSE0 >> 9) & 0x7F;
+}
+
+u_int32_t chipid_get_chip_id(void)
+{
+#if SUB_PLATFORM_S5L8940X
+        return 0x8940;
+#elif SUB_PLATFORM_S5L8942X
+	return 0x8942;
+#elif SUB_PLATFORM_S5L8947X
+	return 0x8947;
+#endif
+}
+
+u_int32_t chipid_get_chip_revision(void)
+{
+	return (((rECIDHI >> 13) & 0x7) << 4) | (((rECIDHI >> 10) & 0x7) << 0);
+}
+
+u_int32_t chipid_get_osc_frequency(void)
+{
+	return OSC_FREQ;
+}
+
+u_int64_t chipid_get_ecid_id(void)
+{
+	u_int64_t ecid = 0;
+
+#if SUPPORT_FPGA
+	ecid = 0x000012345678ABCDULL;
+#else
+	ecid |= ((rECIDLO >>  0)) & ((1ULL << (21 -  0)) - 1);	// LOT_ID
+
+	ecid <<= (26 - 21);
+	ecid |= ((rECIDLO >> 21)) & ((1ULL << (26 - 21)) - 1);	// WAFER_NUM
+
+	ecid <<= (10 -  2);
+	ecid |= ((rECIDHI >>  2)) & ((1ULL << (10 -  2)) - 1);	// Y_POS
+
+	ecid <<= (32 - 26);
+	ecid |= ((rECIDLO >> 26)) & ((1ULL << (32 - 26)) - 1);	// X_POS_H
+
+	ecid <<= ( 2 -  0);
+	ecid |= ((rECIDHI >>  0)) & ((1ULL << ( 2 -  0)) - 1);	// X_POS_L
+#endif
+
+	return ecid;
+}
+
+u_int64_t chipid_get_die_id(void)
+{
+	return ((u_int64_t)rECIDHI << 32) | rECIDLO;
+}
+
+u_int32_t chipid_get_soc_voltage(u_int32_t index)
+{
+	u_int32_t soc_voltage = 0;
+	u_int32_t soc_bin_offset_data = 0, soc_bin_data = (rCFG_FUSE1 >> 5) & 0x1FF;
+	int32_t   soc_bin_offset;
+
+#if DEBUG_BUILD && WITH_ENV
+	soc_bin_offset_data = env_get_uint("soc-bin-offset", 0);
+
+	switch (index) {
+		case CHIPID_SOC_VOLTAGE_LOW	: soc_bin_offset_data = (soc_bin_offset_data >>  0) & 0xff;		break;
+		case CHIPID_SOC_VOLTAGE_MED	: soc_bin_offset_data = (soc_bin_offset_data >>  8) & 0xff;		break;
+		case CHIPID_SOC_VOLTAGE_HIGH	: soc_bin_offset_data = (soc_bin_offset_data >> 16) & 0xff;		break;
+		default				:									break;
+	}
+#endif
+
+	// if bin data is all zeros, bin data is not valid
+	if (soc_bin_data == 0) {
+		switch (index) {
+			case CHIPID_SOC_VOLTAGE_LOW	: soc_voltage = DEFAULT_SOC_VOLTAGE_LOW;	break;
+			case CHIPID_SOC_VOLTAGE_MED	: soc_voltage = DEFAULT_SOC_VOLTAGE_MED;	break;
+			case CHIPID_SOC_VOLTAGE_HIGH	: soc_voltage = DEFAULT_SOC_VOLTAGE_HIGH;	break;
+			default				:						break;
+		}
+	} else {
+		switch (index) {
+			case CHIPID_SOC_VOLTAGE_LOW	: soc_voltage = BASE_SOC_VOLTAGE_LOW  + 25 * ((soc_bin_data>>6)&7);	break;
+			case CHIPID_SOC_VOLTAGE_MED	: soc_voltage = BASE_SOC_VOLTAGE_MED  + 25 * ((soc_bin_data>>3)&7);	break;
+			case CHIPID_SOC_VOLTAGE_HIGH	: soc_voltage = BASE_SOC_VOLTAGE_HIGH + 25 * ((soc_bin_data>>0)&7);	break;
+			default				:									break;
+		}
+	}
+
+	soc_bin_offset = soc_bin_offset_data | (((soc_bin_offset_data & 0x80) == 0) ? 0 : 0xffffff00);
+	soc_bin_offset *= 25;
+
+	return soc_voltage + soc_bin_offset;
+}
+
+u_int32_t chipid_get_cpu_voltage(u_int32_t index)
+{
+	u_int32_t cpu_voltage = 0;
+	u_int32_t cpu_bin_offset_data = 0, cpu_bin_data = ((((u_int64_t)rCFG_FUSE1 << 32) | rCFG_FUSE0) >> 28) & 0x1FF;
+	int32_t   cpu_bin_offset;
+
+#if DEBUG_BUILD && WITH_ENV
+	cpu_bin_offset_data = env_get_uint("cpu-bin-offset", 0);
+
+	switch (index) {
+		case CHIPID_CPU_VOLTAGE_LOW	: cpu_bin_offset_data = (cpu_bin_offset_data >>  0) & 0xff;		break;
+		case CHIPID_CPU_VOLTAGE_MED	: cpu_bin_offset_data = (cpu_bin_offset_data >>  8) & 0xff;	 	break;
+		case CHIPID_CPU_VOLTAGE_HIGH	: cpu_bin_offset_data = (cpu_bin_offset_data >> 16) & 0xff;		break;
+		default				:									break;
+	}
+
+#endif
+	// if bin data is all zeros, bin data is not valid
+	if (cpu_bin_data == 0) {
+		switch (index) {
+			case CHIPID_CPU_VOLTAGE_LOW	: cpu_voltage = DEFAULT_CPU_VOLTAGE_LOW;	break;
+			case CHIPID_CPU_VOLTAGE_MED	: cpu_voltage = DEFAULT_CPU_VOLTAGE_MED;	break;
+			case CHIPID_CPU_VOLTAGE_HIGH	: cpu_voltage = DEFAULT_CPU_VOLTAGE_HIGH;	break;
+			default				:						break;
+		}
+	} else {
+		switch (index) {
+			case CHIPID_CPU_VOLTAGE_LOW	: cpu_voltage = BASE_CPU_VOLTAGE_LOW  + 25 * ((cpu_bin_data>>6)&7);	break;
+			case CHIPID_CPU_VOLTAGE_MED	: cpu_voltage = BASE_CPU_VOLTAGE_MED  + 25 * ((cpu_bin_data>>3)&7);	break;
+			case CHIPID_CPU_VOLTAGE_HIGH	: cpu_voltage = BASE_CPU_VOLTAGE_HIGH + 25 * ((cpu_bin_data>>0)&7);	break;
+			default				:									break;
+		}
+	}
+
+	cpu_bin_offset = cpu_bin_offset_data | (((cpu_bin_offset_data & 0x80) == 0) ? 0 : 0xffffff00);
+	cpu_bin_offset *= 25;
+
+	return cpu_voltage + cpu_bin_offset;
+}
+
+bool chipid_get_fuse_lock(void)
+{
+	return (rCFG_FUSE1 & (1 << 31)) != 0;
+}
+
+void chipid_set_fuse_lock(bool locked)
+{
+	if (locked) rCFG_FUSE1 |= 1 << 31;
+}
+
+u_int32_t chipid_get_memory_density(void)
+{
+	u_int32_t data = (rCFG_FUSE0 >> 24) & 0x7;
+
+	if (chipid_get_memory_manufacturer() == 0) data = 5;
+
+	return 1 << (24 + data);
+}
+
+u_int32_t chipid_get_memory_manufacturer(void)
+{
+	return (rCFG_FUSE0 >> 20) & 0xF;
+}
+
+u_int32_t chipid_get_memory_ranks(void)
+{
+	u_int32_t data = (rCFG_FUSE0 >> 27) & 0x1;
+
+	if (chipid_get_memory_manufacturer() ==	0) data	= 0;
+
+	return 1 << data;
+}
+
+u_int32_t chipid_get_memory_width(void)
+{
+	u_int32_t data = (rCFG_FUSE0 >> 18) & 0x3;
+
+	if (chipid_get_memory_manufacturer() ==	0) data	= 2;
+
+	return 16 << data;
+}
+
+bool chipid_get_memory_dqcal(u_int32_t *cal_data)
+{
+	/* Swizzle the fuses into a standard format.  One word each
+	 * for CH0 read, CH0 write, etc. */
+	cal_data[0] = rCFG_FUSE2 & 0xffff;
+	cal_data[1] = rCFG_FUSE3 & 0xffff;
+	cal_data[2] = rCFG_FUSE2 >> 16;
+	cal_data[3] = rCFG_FUSE3 >> 16;
+	return true;
+}

platform/s5l8940x/chipid/rules.mk

@@ -0,0 +1,15 @@
+# Copyright (C) 2009 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_PLATFORM_CHIPID=1
+
+ALL_OBJS += $(LOCAL_DIR)/chipid.o

platform/s5l8940x/include/platform/amcconfig.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#include SUB_PLATFORM_HEADER(amcconfig)

platform/s5l8940x/include/platform/amcconfig_s5l8940x.h

@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2009-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#if WITH_TARGET_AMC_PARAMS
+#include <target/amcconfig.h>
+#else
+static const struct amc_param amc_params = {
+	.flags                  = FLAG_AMC_PARAM_ENABLE_AIU | FLAG_AMC_PARAM_SLOW_BOOT,
+
+	.freqsel                = 0,
+	.tREFi                  = 0x5d,
+	.longsrcnt              = 0x0802,
+	.srextrarefcnt		= 0x00010000,
+	.tREFi_1Gb              = 0xbb,
+	.longsrcnt_1Gb          = 0x0401,
+	.rdlat                  = 6,
+	.wrlat                  = 3,
+	.phyrdlat               = 6,				// rdlat
+	.phywrlat   		= 3,
+	.pdn                    = 0x33000303,
+	.read                   = 0x00000103,
+	.bustat                 = 0x00020002,
+	.derate                 = 0x28831258,
+	.mcphyupdate            = 0x00000009,			// <rdar://problem/8199905> <rdar://problem/8256572>
+	.pwrmngtparam_small     = 0x00013000,
+	.pwrmngtparam_guided    = 0x00fa3000,
+	.bootclkdivsr           = 8,
+	.aref_freq0		= 0x00100100,
+	.aref_freq1		= 0x00100000,
+	.chnldec		= 0x00000F00,
+	.arefparam              = 0x06000000,
+	.readleveling           = 0x02000301,
+
+	.freq                   = {
+		{	// 400MHz
+			.cas         = 0x00000308,
+			.pch         = 0x00030611,
+			.act         = 0x14040908,
+			.autoref     = 0x1834a000,
+			.selfref     = 0x00038060,
+			.modereg     = 0x00240502,
+			.mifcassch   = 0x001f0111,
+			.mifqmaxctrl = 0x00000000,
+		},
+		{	// 200MHz
+			.cas         = 0x00000004,
+			.pch         = 0x00000009,
+			.act         = 0x0a020504,
+			.autoref     = 0x0c1a0000,
+			.selfref     = 0x0001c000,
+			.modereg     = 0x00120000,
+			.mifcassch   = 0x00000000,
+			.mifqmaxctrl = 0x00000000,
+		},
+		{	// 100MHz
+			.cas         = 0x00000003,
+			.pch         = 0x00000005,
+			.act         = 0x08020303,
+			.autoref     = 0x060d0000,
+			.selfref     = 0x0000e000,
+			.modereg     = 0x00090000,
+			.mifcassch   = 0x00000000,
+			.mifqmaxctrl = 0x00000000,
+		},
+		{	// 50 & 24MHz
+			.cas         = 0x00000003,
+			.pch         = 0x00000003,
+			.act         = 0x08020303,
+			.autoref     = 0x03070000,
+			.selfref     = 0x00007000,
+			.modereg     = 0x00060000,
+			.mifcassch   = 0x00000010,
+			.mifqmaxctrl = 0x00000001,
+		}
+	}
+};
+
+static const struct amc_tunable amc_tunables[] = {
+	// These settings are common across all H4x and H5P.  Channel decode and hashing
+	// is done in mainline init code.  Any tunables that match hardware defaults are
+	// omitted here.
+	
+	{ &rAMC_AIUPRT_CFG,		0x00070000 },		// address error enable
+	{ &rAMC_AIUPRT_RD_GEN,		0x00000018 },		// fence read detect on GFX
+	{ &rAMC_AIUPRT_WR,		0x00000001 },		// out-of-order write, ignore B-bit
+
+	{ &rAMC_AIU_RDBRSTLEN,		0x01010101 },		// burst len is 64B
+	{ &rAMC_AIU_RDMINCRD,		0x7B7B7C7B },		// RT:NRT:CPU:GFX = 40:40:5:10
+	{ &rAMC_AIU_WRBRSTLEN,		0x01010101 },		// burst len is 64B
+	{ &rAMC_AIU_WRMINCRD,		0x7B7B7C7B },		// RT:NRT:CPU:GFX = 40:40:5:10
+
+	{ &rAMC_AIU_CPUSPCREQ,		0x00000019 },		// CPU ageout timer
+	{ &rAMC_AIU_GFXSPCREQ,		0x00000032 },		// GFX ageout timer
+	{ &rAMC_AIU_NRTSPCREQ,		0x00000032 },		// Hperf-NRT ageout timer
+	{ &rAMC_AIU_RTSPCREQ,		0x00000019 },		// Hperf-RT ageout timer
+	{ &rAMC_AIU_WPQSCH,		0x10001000 },		// only supported for Hperf-RT
+	{ &rAMC_AIU_THOTLCPUPARAM,	0x0A4640C4 },
+	{ &rAMC_AIU_THOTLRTPARAM,	0x0A4640C4 },
+	{ &rAMC_AIU_THOTLNRTPARAM,	0x00000000 },
+	{ &rAMC_AIU_THOTLGFXPARAM,	0x00000000 },
+	{ &rAMC_AIU_PUSHEN,		0x00001100 },		// only supported for Hperf-RT
+
+	{ &rAMC_OPIDLETMR,		0x00200000 },
+	{ &rAMC_OPTMRADJEN,		0x00000001 },
+	{ &rAMC_OPTMRADJPARAM,		0x20400064 },
+
+	{ &rAMC_MIFACTSCH,		0x00000001 },
+
+	{ &rAMC_PSQRQTIMER0,		0x00000040 },		// RTG bypass up to 64 transactions
+	{ &rAMC_PSQRQTIMER1,		0x00000018 },		// RTY bypass up to 24 transactions
+	{ &rAMC_PSQRQTIMER2,		0x00000020 },		// RTG bypass up to 32 transactions
+	{ &rAMC_PSQRQBRST,		0x040c040c },		// RTR transactions don't affect read burst size
+	{ &rAMC_PSQRQSCHCRD,		0x002028f5 },		// read credits = 2 * write credits
+	{ &rAMC_PSQWQBRST,		0x0208040c },		// RTR reads cause reduced write burst size
+	{ &rAMC_PSQWQSCHCRD,		0x001014f5 },		// write credits = 1/2 * read credits
+	{ &rAMC_MCUQOS,			0x00010f04 },		// RTG=4, RTY=15, enable pick-oldest-RTY
+
+	// Platform specific
+	
+	{ &rAMC_AIU_RDMAXCRD,		0x2828050a },		// RT:NRT:CPU:GFX = 40:40:5:10
+	{ &rAMC_AIU_RDREFL,		0x21210408 },		// 5/6 of AIURDMAXCRD fields
+	{ &rAMC_AIU_WRMAXCRD,		0x2828050a }, 		// RT:NRT:CPU:GFX = 40:40:5:10
+	{ &rAMC_AIU_WRREFL,		0x21210408 },		// 5/6 of AIUWRMAXCRD fields
+	{ &rAMC_AIU_THOTLEN,		0x00001111 },		// enable throttling
+	{ &rAMC_PSQWQCTL1,		0x000000C0 },		// ages write out faster than default (1/2 SelfRef)
+	{ &rAMC_MCUQOSLLT,		0x00010104 },
+	{ &rAMC_PWRMNGTPARAM,		0x01801000 },		// SelfRef timer = 384 cycles
+
+	// There is a bug around write merge, which we believe is avoided 
+	// in current drivers: <rdar://problem/9076703>
+	// Power and performance measurements of disabling write merging were
+	// done: <rdar://problem/9092558> <rdar://problem/9087726>
+	{ &rAMC_PSQWQCTL0,		0x00010100 },		// Write merge enable
+};
+#endif

platform/s5l8940x/include/platform/amcconfig_s5l8942x.h

@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2011-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#if WITH_TARGET_AMC_PARAMS
+#include <target/amcconfig.h>
+#else
+static const struct amc_param amc_params = {
+	.flags     	 	= (FLAG_AMC_PARAM_SLOW_BOOT | FLAG_AMC_PARAM_RECONFIG | FLAG_AMC_PARAM_ENABLE_AIU),
+
+	.freqsel                = 0,
+	.tREFi                  = 0x5d,
+	.longsrcnt              = 0x0802,
+	.srextrarefcnt		= 0x00010000,
+	.tREFi_1Gb              = 0xbb,
+	.longsrcnt_1Gb          = 0x0401,
+	.rdlat                  = 6,
+	.wrlat                  = 3,
+	.phyrdlat               = 6,				// rdlat
+	.phywrlat   		= 3,
+	.pdn                    = 0x33000303,
+	.read                   = 0x00000103,
+	.bustat                 = 0x00020002,
+	.derate                 = 0x28831258,
+	.mcphyupdate            = 0x00000009,			// <rdar://problem/8199905> <rdar://problem/8256572>
+	.pwrmngtparam_small     = 0x00013000,
+	.pwrmngtparam_guided    = 0x00fa3000,
+	.bootclkdivsr           = 8,
+	.aref_freq0		= 0x00100100,
+	.aref_freq1		= 0x00100000,
+	.chnldec		= 0x00000F00,
+	.arefparam              = 0x06000000,
+	.readleveling           = 0x02000301,
+
+	.freq                   = {
+		{	// 400MHz
+			.cas         = 0x00000308,
+			.pch         = 0x00030611,
+			.act         = 0x14040908,
+			.autoref     = 0x1834a000,
+			.selfref     = 0x00038060,
+			.modereg     = 0x00240502,
+			.mifcassch   = 0x001f0111,
+			.mifqmaxctrl = 0x00000000,
+		},
+		{	// 200MHz
+			.cas         = 0x00000004,
+			.pch         = 0x00000009,
+			.act         = 0x0a020504,
+			.autoref     = 0x0c1a0000,
+			.selfref     = 0x0001c000,
+			.modereg     = 0x00120000,
+			.mifcassch   = 0x00000000,
+			.mifqmaxctrl = 0x00000000,
+		},
+		{	// 100MHz
+			.cas         = 0x00000003,
+			.pch         = 0x00000005,
+			.act         = 0x08020303,
+			.autoref     = 0x060d0000,
+			.selfref     = 0x0000e000,
+			.modereg     = 0x00090000,
+			.mifcassch   = 0x00000000,
+			.mifqmaxctrl = 0x00000000,
+		},
+		{	// 50 & 24MHz
+			.cas         = 0x00000003,
+			.pch         = 0x00000003,
+			.act         = 0x08020303,
+			.autoref     = 0x03070000,
+			.selfref     = 0x00007000,
+			.modereg     = 0x00060000,
+			.mifcassch   = 0x00000010,
+			.mifqmaxctrl = 0x00000001,
+		}
+	}
+};
+
+static const struct amc_tunable amc_tunables[] = {
+	// These settings are common across all H4x and H5P.  Channel decode and hashing
+	// is done in mainline init code.  Any tunables that match hardware defaults are
+	// omitted here.
+	
+	{ &rAMC_AIUPRT_CFG,		0x00070000 },		// address error enable
+	{ &rAMC_AIUPRT_RD_GEN,		0x00000018 },		// fence read detect on GFX
+	{ &rAMC_AIUPRT_WR,		0x00000001 },		// out-of-order write, ignore B-bit
+
+	{ &rAMC_AIU_RDBRSTLEN,		0x01010101 },		// burst len is 64B
+	{ &rAMC_AIU_RDMINCRD,		0x7B7B7C7B },		// RT:NRT:CPU:GFX = 40:40:5:10
+	{ &rAMC_AIU_WRBRSTLEN,		0x01010101 },		// burst len is 64B
+	{ &rAMC_AIU_WRMINCRD,		0x7B7B7C7B },		// RT:NRT:CPU:GFX = 40:40:5:10
+
+	{ &rAMC_AIU_CPUSPCREQ,		0x00000019 },		// CPU ageout timer
+	{ &rAMC_AIU_GFXSPCREQ,		0x00000032 },		// GFX ageout timer
+	{ &rAMC_AIU_NRTSPCREQ,		0x00000032 },		// Hperf-NRT ageout timer
+	{ &rAMC_AIU_RTSPCREQ,		0x00000019 },		// Hperf-RT ageout timer
+	{ &rAMC_AIU_WPQSCH,		0x10001000 },		// only supported for Hperf-RT
+	{ &rAMC_AIU_THOTLCPUPARAM,	0x0A4640C4 },
+	{ &rAMC_AIU_THOTLRTPARAM,	0x0A4640C4 },
+	{ &rAMC_AIU_THOTLNRTPARAM,	0x00000000 },
+	{ &rAMC_AIU_THOTLGFXPARAM,	0x00000000 },
+	{ &rAMC_AIU_PUSHEN,		0x00001100 },		// only supported for Hperf-RT
+
+	{ &rAMC_OPIDLETMR,		0x00200000 },
+	{ &rAMC_OPTMRADJEN,		0x00000001 },
+	{ &rAMC_OPTMRADJPARAM,		0x20400064 },
+
+	{ &rAMC_MIFACTSCH,		0x00000001 },
+
+	{ &rAMC_PSQRQTIMER0,		0x00000040 },		// RTG bypass up to 64 transactions
+	{ &rAMC_PSQRQTIMER1,		0x00000018 },		// RTY bypass up to 24 transactions
+	{ &rAMC_PSQRQTIMER2,		0x00000020 },		// RTG bypass up to 32 transactions
+	{ &rAMC_PSQRQBRST,		0x040c040c },		// RTR transactions don't affect read burst size
+	{ &rAMC_PSQRQSCHCRD,		0x002028f5 },		// read credits = 2 * write credits
+	{ &rAMC_PSQWQBRST,		0x0208040c },		// RTR reads cause reduced write burst size
+	{ &rAMC_PSQWQSCHCRD,		0x001014f5 },		// write credits = 1/2 * read credits
+	{ &rAMC_MCUQOS,			0x00010f04 },		// RTG=4, RTY=15, enable pick-oldest-RTY
+
+	// Platform specific
+	
+	{ &rAMC_AIU_RDMAXCRD,		0x2828050a },		// RT:NRT:CPU:GFX = 40:40:5:10
+	{ &rAMC_AIU_RDREFL,		0x21210408 },		// 5/6 of AIURDMAXCRD fields
+	{ &rAMC_AIU_WRMAXCRD,		0x2828050a }, 		// RT:NRT:CPU:GFX = 40:40:5:10
+	{ &rAMC_AIU_WRREFL,		0x21210408 },		// 5/6 of AIUWRMAXCRD fields
+	{ &rAMC_AIU_THOTLEN,		0x00001111 },		// enable throttling
+	{ &rAMC_PSQWQCTL1,		0x000000C0 },		// ages write out faster than default (1/2 SelfRef)
+	{ &rAMC_MCUQOSLLT,		0x00010104 },
+	{ &rAMC_PWRMNGTPARAM,		0x01801000 },		// SelfRef timer = 384 cycles
+
+	// There is a bug around write merge, which we believe is avoided 
+	// in current drivers: <rdar://problem/9076703>
+	// Power and performance measurements of disabling write merging were
+	// done: <rdar://problem/9092558> <rdar://problem/9087726>
+	{ &rAMC_PSQWQCTL0,		0x00010100 },		// Write merge enable
+};
+#endif

platform/s5l8940x/include/platform/amcconfig_s5l8947x.h

@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2011-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#if WITH_TARGET_AMC_PARAMS
+#include <target/amcconfig.h>
+#else
+static const struct amc_param amc_params = {
+	.flags     	 	= (FLAG_AMC_PARAM_SLOW_BOOT | FLAG_AMC_PARAM_RECONFIG | FLAG_AMC_PARAM_ENABLE_AIU | FLAG_AMC_PARAM_MRR_BYTE_SWIZZLE | FLAG_AMC_PARAM_MRR_BIT_SWIZZLE),
+
+	.tREFi      		= 0x5d,
+	.longsrcnt  		= 0x2008,
+	.tREFi_1Gb		= 0x5d,
+	.longsrcnt_1Gb		= 0x2008,
+	.rdlat      		= 8,	
+	.wrlat      		= 4,	
+	.phyrdlat   		= 8,	
+	.phywrlat   		= 4,	
+	.pdn        		= 0x33000503,
+	.read       		= 0x00000103,
+	.bustat     		= 0x00222212,
+	.bustat2    		= 0x00222212,
+	.derate     		= 0x34b3187b,
+	.mcphyupdate		= 0x05030000,
+	.autoref_params		= 0x22,		// <rdar://problem/9133484> MIF: tREFBW violation due to freq change
+	.pwrmngtparam_small	= 0x00011000,
+	.pwrmngtparam_guided	= 0x03001000,
+	.chnldec		= 0x00000100,
+	.chnldec2		= 0x003ffffd,
+	.arefparam		= 0x0600a000,
+	.bootclkdivsr		= 0xa,	     
+	.aref_freq0		= 0x00100100,
+	.aref_freq1		= 0x00100100,
+	.srextrarefcnt		= 0x00010000,
+	.readleveling           = 0x01000301,
+
+	.freq     		= {
+		{	// 532.8MHz
+			.cas         = 0x0000040a,
+			.pch         = 0x00040817,
+			.act         = 0x1b060c0a,
+			.autoref     = 0x20469000,
+			.selfref     = 0x0004b080,
+			.modereg     = 0x00300502,
+			.mifcassch   = 0x001f0111,
+		},
+		{	// 400MHz
+			.cas         = 0x00000008,
+			.pch         = 0x00000012,
+			.act         = 0x14050a08,
+			.autoref     = 0x18340000,
+			.selfref     = 0x00038000,
+			.modereg     = 0x00240000,
+			.mifcassch   = 0x00000010,
+		},
+		{	// 106.6MHz
+			.cas         = 0x00000003,
+			.pch         = 0x00000005,
+			.act         = 0x08020303,
+			.autoref     = 0x070e0000,
+			.selfref     = 0x0000f000,
+			.modereg     = 0x000a0000,
+			.mifcassch   = 0x00000000,
+		},
+		{	// 53.3MHz
+			.cas         = 0x00000003,
+			.pch         = 0x00000003,
+			.act         = 0x08020303,
+			.autoref     = 0x04070000,
+			.selfref     = 0x00008000,
+			.modereg     = 0x00060000,
+			.mifcassch   = 0x00000010,
+		}
+	}
+};
+
+static const struct amc_tunable amc_tunables[] = {
+	// These settings are common across all H4x and H5P.  Channel decode and hashing
+	// is done in mainline init code.  Any tunables that match hardware defaults are
+	// omitted here.
+
+	{ &rAMC_AIUPRT_CFG,		0x00070000 },		// address error enable
+	{ &rAMC_AIUPRT_RD_GEN,		0x00000018 },		// fence read detect on GFX
+	{ &rAMC_AIUPRT_WR,		0x00000001 },		// out-of-order write, ignore B-bit
+	{ &rAMC_AIU_RDBRSTLEN,		0x01010101 },		// burst len is 64B
+	{ &rAMC_AIU_WRBRSTLEN,		0x01010101 },		// burst len is 64B
+	{ &rAMC_AIU_CPUSPCREQ,		0x00000019 },		// CPU ageout timer
+	{ &rAMC_AIU_GFXSPCREQ,		0x00000032 },		// GFX ageout timer
+	{ &rAMC_AIU_NRTSPCREQ,		0x00000032 },		// Hperf-NRT ageout timer
+	{ &rAMC_AIU_RTSPCREQ,		0x00000019 },		// Hperf-RT ageout timer
+	{ &rAMC_AIU_PUSHEN,		0x00001100 },		// only supported for Hperf-RT
+
+	{ &rAMC_OPIDLETMR,		0x00200000 },
+	{ &rAMC_OPTMRADJPARAM,		0x20400064 },
+	{ &rAMC_MIFACTSCH,		0x00000001 },
+	{ &rAMC_PSQRQTIMER0,		0x00000040 },		// RTG bypass up to 64 transactions
+	{ &rAMC_PSQRQTIMER1,		0x00000018 },		// RTY bypass up to 24 transactions
+	{ &rAMC_PSQRQTIMER2,		0x00000020 },		// RTG bypass up to 32 transactions
+	{ &rAMC_PSQRQBRST,		0x040c040c },		// RTR transactions don't affect read burst size
+	{ &rAMC_PSQRQSCHCRD,		0x002028f5 },		// read credits = 2 * write credits
+	{ &rAMC_PSQWQBRST,		0x0208040c },		// RTR reads cause reduced write burst size
+	{ &rAMC_PSQWQSCHCRD,		0x001014f5 },		// write credits = 1/2 * read credits
+	{ &rAMC_MCUQOS,			0x00010f04 },		// RTG=4, RTY=15, enable pick-oldest-RTY
+	{ &rAMC_ADDRMAP_MODE,		0x00000002 },		// RIBI2 achieves much better performance for both linear and tiled mode frame buffers, and has better power profile as well
+	{ &rAMC_PWRMNGTPARAM,		0x03001000 },		// Use AiuReq to exiting self refresh state.
+
+	// Platform specific
+	
+	{ &rAMC_AIU_CHNLDEC2,		0x003FFFFD },		// The goal is randomize the channel in most cases to create a balanced distribution.
+	{ &rAMC_AIU_RDMAXCRD,		0x3012097f },		// RT:NRT:CPU:GFX = 48:18:09:MAX
+	{ &rAMC_AIU_RDREFL,		0x280f087f },		// 5/6 of AIURDMAXCRD fields
+	{ &rAMC_AIU_WRMAXCRD,		0x3012097f },		// RT:NRT:CPU:GFX = 48:18:09:MAX
+	{ &rAMC_AIU_WRREFL,		0x280f087f },		// 5/6 of AIUWRMAXCRD fields
+
+	{ &rAMC_AIU_ADDRBANKHASH0,	0x00006db6 },		// Enable bank hashing, bank[0] derived from bits 0,3,6,..
+	{ &rAMC_AIU_ADDRBANKHASH1,	0x00005b6d },		// Enable bank hashing, bank[1] derived from bits 1,4,7,..
+	{ &rAMC_AIU_ADDRBANKHASH2,	0x000036db },		// Enable bank hashing, bank[2] derived from bits 2,5,8,..
+	{ &rAMC_AIU_CHNLCRD,		0x00180018 },
+	{ &rAMC_AIU_LLTSCHCTL,		0x00000001 },		// Ensure LLT traffic from all ports is treated as medium priority request in the AIU arbitration
+	{ &rAMC_MCUQOSLLT,		0x00010108 },
+
+	{ &rAMC_AIU_CHNLTM,		0x40006101 },
+	{ &rAMC_AIU_WPQSCH,		0x08000800 },		// set starvation counts to 8
+	{ &rAMC_PSQRQCTL1,		0x0000132a },
+	{ &rAMC_PSQWQCTL0,		0x00010100 },		// enable write merging
+	{ &rAMC_PSQWQCTL1,		0x00000180 },		// ages write out faster than default (1/2 SelfRef)
+};
+#endif

platform/s5l8940x/include/platform/amgconfig.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+/*
+ * The amg_param struct is defined in drivers/apple/amg/amg.h, and this
+ * file should only by included from amg.c.
+ */
+
+#if WITH_TARGET_AMG_PARAMS
+// Default overrided by ipad2, j33, fpga
+#include <target/amgconfig.h>
+#else
+// Default shared by n94, k93a, n78
+static const struct amg_params amc_phy_params = {
+	.flags         = 0,
+	.core_config   = 0x00001053,
+	.read_latency  = 0x0000669b,
+	.gate_offset   = 0x08080808,
+};
+#endif

platform/s5l8940x/include/platform/ampconfig.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#if WITH_TARGET_AMP_PARAMS
+#include <target/ampconfig.h>
+#else
+static const struct amp_params amc_phy_params = {
+	.flags = (FLAG_AMP_PARAM_SUPPORT_FMCLK_OFF | FLAG_AMP_PARAM_FULLDIFFMODE),
+	.freq = {
+		{
+			.scl = 0x08,
+			.rdcapcfg = 0x00010308,
+		},
+		{
+			.scl = 0x0b,
+			.rdcapcfg = 0x00010306,
+		},
+		{
+			.scl = 0x28,
+			.rdcapcfg = 0x00010301,
+		},
+		{
+			.scl = 0x3f,
+			.rdcapcfg = 0x00010301,
+		},
+	},
+};
+#endif

platform/s5l8940x/include/platform/boot_pins.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_BOOT_PINS_H
+#define __PLATFORM_BOOT_PINS_H
+
+#include <platform.h>
+#include <platform/gpio.h>
+#include <sys/types.h>
+
+struct boot_interface_pin {
+	gpio_t	  pin;
+	u_int32_t enable;
+	u_int32_t disable;
+};
+
+#include SUB_PLATFORM_HEADER(boot_pins)
+
+#endif /* ! __PLATFORM_BOOT_PINS_H */

platform/s5l8940x/include/platform/boot_pins_s5l8940x.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_BOOT_PINS_S5L8940X_H
+#define __PLATFORM_BOOT_PINS_S5L8940X_H
+
+/*
+ *  boot_interface_pin tables
+ *    tables are executed in order for disable and reverse order for enable
+ *
+ */
+
+#if WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI
+static const struct boot_interface_pin spi0_boot_interface_pins[] =
+{
+#if SUPPORT_FPGA
+	{ GPIO(20, 5), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// SPI0_SSIN
+#else
+	{ GPIO(20, 5), GPIO_CFG_OUT_1, GPIO_CFG_IN },	// SPI0_SSIN
+#endif
+	{ GPIO(20, 2), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// SPI0_SCLK
+	{ GPIO(20, 3), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// SPI0_MOSI
+	{ GPIO(20, 4), GPIO_CFG_FUNC0, GPIO_CFG_IN }	// SPI0_MISO
+};
+
+static const struct boot_interface_pin spi3_boot_interface_pins[] =
+{
+#if SUPPORT_FPGA
+	{ GPIO(18, 7), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// SPI3_SSIN
+#else
+	{ GPIO(18, 7), GPIO_CFG_OUT_1, GPIO_CFG_IN },	// SPI3_SSIN
+#endif
+	{ GPIO(18, 6), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// SPI3_SCLK
+	{ GPIO(18, 4), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// SPI3_MOSI
+	{ GPIO(18, 5), GPIO_CFG_FUNC0, GPIO_CFG_IN }	// SPI3_MISO
+};
+#endif /* WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI */
+
+#if WITH_HW_BOOTROM_NAND
+
+/* Note: The code in init.c expects this table to begin with CS3 through CS0 */
+static const struct boot_interface_pin fmi0_boot_interface_pins[] =
+{
+	{ GPIO( 8, 0), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_CEN3
+	{ GPIO( 8, 1), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_CEN2
+	{ GPIO( 8, 2), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_CEN1
+	{ GPIO( 8, 3), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_CEN0
+	{ GPIO( 8, 4), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_CLE
+	{ GPIO( 8, 5), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_ALE
+	{ GPIO( 8, 6), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_REN
+	{ GPIO( 8, 7), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_WEN
+	{ GPIO(10, 0), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_IO0
+	{ GPIO( 9, 7), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_IO1
+	{ GPIO( 9, 6), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_IO2
+	{ GPIO( 9, 5), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_IO3
+	{ GPIO( 9, 3), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_IO4
+	{ GPIO( 9, 2), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_IO5
+	{ GPIO( 9, 1), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI0_IO6
+	{ GPIO( 9, 0), GPIO_CFG_FUNC0, GPIO_CFG_IN }	// FMI0_IO7
+};
+
+/* Note: The code in init.c expects this table to begin with CS3 through CS0 */
+static const struct boot_interface_pin fmi1_boot_interface_pins[] =
+{
+	{ GPIO(10, 1), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_CEN3
+	{ GPIO(10, 2), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_CEN2
+	{ GPIO(10, 3), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_CEN1
+	{ GPIO(10, 4), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_CEN0
+	{ GPIO(10, 5), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_CLE
+	{ GPIO(10, 6), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_ALE
+	{ GPIO(10, 7), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_REN
+	{ GPIO(11, 0), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_WEN
+	{ GPIO(12, 0), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_IO0
+	{ GPIO(12, 1), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_IO1
+	{ GPIO(11, 7), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_IO2
+	{ GPIO(11, 6), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_IO3
+	{ GPIO(11, 4), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_IO4
+	{ GPIO(11, 3), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_IO5
+	{ GPIO(11, 2), GPIO_CFG_FUNC0, GPIO_CFG_IN },	// FMI1_IO6
+	{ GPIO(11, 1), GPIO_CFG_FUNC0, GPIO_CFG_IN }	// FMI1_IO7
+};
+#endif /* WITH_HW_BOOTROM_NAND */
+
+#endif /* ! __PLATFORM_BOOT_PINS_S5L8940X_H */

platform/s5l8940x/include/platform/boot_pins_s5l8942x.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_BOOT_PINS_S5L8942X_H
+#define __PLATFORM_BOOT_PINS_S5L8942X_H
+
+/*
+ *  boot_interface_pin tables
+ *    tables are executed in order for disable and reverse order for enable
+ *
+ */
+
+#if WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI
+static const struct boot_interface_pin spi0_boot_interface_pins[] =
+{
+#if SUPPORT_FPGA
+	{ GPIO(12, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// SPI0_SSIN
+#else
+	{ GPIO(12, 3), GPIO_CFG_OUT_1, GPIO_CFG_DFLT },	// SPI0_SSIN
+#endif
+	{ GPIO(12, 0), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// SPI0_SCLK
+	{ GPIO(12, 1), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// SPI0_MOSI
+	{ GPIO(12, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT }	// SPI0_MISO
+};
+
+static const struct boot_interface_pin spi3_boot_interface_pins[] =
+{
+#if SUPPORT_FPGA
+	{ GPIO(16, 3), GPIO_CFG_FUNC1, GPIO_CFG_DFLT },	// SPI3_SSIN
+#else
+	{ GPIO(16, 3), GPIO_CFG_OUT_1, GPIO_CFG_DFLT },	// SPI3_SSIN
+#endif
+	{ GPIO(16, 0), GPIO_CFG_FUNC1, GPIO_CFG_DFLT },	// SPI3_SCLK
+	{ GPIO(16, 1), GPIO_CFG_FUNC1, GPIO_CFG_DFLT },	// SPI3_MOSI
+	{ GPIO(16, 2), GPIO_CFG_FUNC1, GPIO_CFG_DFLT }	// SPI3_MISO
+};
+#endif /* WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI */
+
+#if WITH_HW_BOOTROM_NAND
+
+/* Note: The code in init.c expects this table to begin with CS3 through CS0 */
+static const struct boot_interface_pin fmi0_boot_interface_pins[] =
+{
+	{ GPIO(17, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_CEN3
+	{ GPIO(17, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_CEN2
+	{ GPIO(17, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_CEN1
+	{ GPIO(17, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_CEN0
+	{ GPIO(17, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_CLE
+	{ GPIO(17, 7), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_ALE
+	{ GPIO(18, 0), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_REN
+	{ GPIO(18, 1), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_WEN
+	{ GPIO(20, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO0
+	{ GPIO(20, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO1
+	{ GPIO(20, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO2
+	{ GPIO(20, 1), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO3
+	{ GPIO(18, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO4
+	{ GPIO(18, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO5
+	{ GPIO(18, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO6
+	{ GPIO(18, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT }	// FMI0_IO7
+};
+
+/* Note: The code in init.c expects this table to begin with CS3 through CS0 */
+static const struct boot_interface_pin fmi1_boot_interface_pins[] =
+{
+	{ GPIO(20, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_CEN3
+	{ GPIO(20, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_CEN2
+	{ GPIO(20, 7), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_CEN1
+	{ GPIO(21, 0), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_CEN0
+	{ GPIO(21, 1), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_CLE
+	{ GPIO(21, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_ALE
+	{ GPIO(21, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_REN
+	{ GPIO(21, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_WEN
+	{ GPIO(22, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO0
+	{ GPIO(22, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO1
+	{ GPIO(22, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO2
+	{ GPIO(22, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO3
+	{ GPIO(22, 0), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO4
+	{ GPIO(21, 7), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO5
+	{ GPIO(21, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO6
+	{ GPIO(21, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT }	// FMI1_IO7
+};
+#endif /* WITH_HW_BOOTROM_NAND */
+
+#endif /* ! __PLATFORM_BOOT_PINS_S5L8942X_H */

platform/s5l8940x/include/platform/boot_pins_s5l8947x.h

@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_BOOT_PINS_S5L8947X_H
+#define __PLATFORM_BOOT_PINS_S5L8947X_H
+
+/*
+ *  boot_interface_pin tables
+ *    tables are executed in order for disable and reverse order for enable
+ *
+ */
+
+#if WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI
+static const struct boot_interface_pin spi0_boot_interface_pins[] =
+{
+#if SUPPORT_FPGA
+	{ GPIO(17, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// SPI0_SSIN
+#else
+	{ GPIO(17, 3), GPIO_CFG_OUT_1, GPIO_CFG_DFLT },	// SPI0_SSIN
+#endif
+	{ GPIO(17, 0), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// SPI0_SCLK
+	{ GPIO(17, 1), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// SPI0_MOSI
+	{ GPIO(17, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT }	// SPI0_MISO
+};
+#endif /* WITH_HW_FLASH_NOR && WITH_HW_FLASH_NOR_SPI */
+
+#if WITH_HW_BOOTROM_NAND
+
+/* Note: The code in init.c expects this table to begin with CS3 through CS0 */
+static const struct boot_interface_pin fmi0_boot_interface_pins[] =
+{
+	{ GPIO( 5, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_CEN1
+	{ GPIO( 5, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_CEN0
+	{ GPIO( 5, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_CLE
+	{ GPIO( 5, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_ALE
+	{ GPIO( 5, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_REN
+	{ GPIO( 5, 7), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_WEN
+	{ GPIO( 7, 0), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO0
+	{ GPIO( 6, 7), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO1
+	{ GPIO( 6, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO2
+	{ GPIO( 6, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO3
+	{ GPIO( 6, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO4
+	{ GPIO( 6, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO5
+	{ GPIO( 6, 1), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI0_IO6
+	{ GPIO( 6, 0), GPIO_CFG_FUNC0, GPIO_CFG_DFLT }	// FMI0_IO7
+};
+
+/* Note: The code in init.c expects this table to begin with CS3 through CS0 */
+static const struct boot_interface_pin fmi1_boot_interface_pins[] =
+{
+	{ GPIO( 7, 1), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_CEN1
+	{ GPIO( 7, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_CEN0
+	{ GPIO( 7, 3), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_CLE
+	{ GPIO( 7, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_ALE
+	{ GPIO( 7, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_REN
+	{ GPIO( 7, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_WEN
+	{ GPIO( 8, 7), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO0
+	{ GPIO( 8, 6), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO1
+	{ GPIO( 8, 5), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO2
+	{ GPIO( 8, 4), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO3
+	{ GPIO( 8, 2), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO4
+	{ GPIO( 8, 1), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO5
+	{ GPIO( 8, 0), GPIO_CFG_FUNC0, GPIO_CFG_DFLT },	// FMI1_IO6
+	{ GPIO( 7, 7), GPIO_CFG_FUNC0, GPIO_CFG_DFLT }	// FMI1_IO7
+};
+#endif /* WITH_HW_BOOTROM_NAND */
+
+#endif /* ! __PLATFORM_BOOT_PINS_S5L8947X_H */

platform/s5l8940x/include/platform/gpiodef.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_GPIODEF_H
+#define __PLATFORM_GPIODEF_H
+
+/* S5L8940X specific gpio -> pin mappings */
+
+#include <platform.h>
+#include <platform/gpio.h>
+#include <platform/soc/hwregbase.h>
+
+#if WITH_TARGET_CONFIG
+# include <target/gpiodef.h>
+#endif
+
+#include SUB_PLATFORM_HEADER(gpiodef)
+
+#endif /* ! __PLATFORM_GPIODEF_H */

platform/s5l8940x/include/platform/gpiodef_s5l8940x.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2011-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_GPIODEF_S5L8940X_H
+#define __PLATFORM_GPIODEF_S5L8940X_H
+
+/* S5L8940X specific gpio -> pin mappings */
+
+#if !SUB_PLATFORM_S5L8940X
+#error "Only include for S5L8940X platform"
+#endif
+
+/* define platform-specific gpios in a generic fashion here. */
+#define GPIO_IIC0_SCL		GPIO(21, 3)
+#define GPIO_IIC0_SDA		GPIO(21, 2)
+#define GPIO_IIC1_SCL		GPIO(21, 5)
+#define GPIO_IIC1_SDA		GPIO(21, 4)
+#define GPIO_IIC2_SCL		GPIO(20, 1)
+#define GPIO_IIC2_SDA		GPIO(20, 0)
+
+#define GPIO_BOARD_ID0		GPIO(20, 2)
+#define GPIO_BOARD_ID1		GPIO(20, 3)
+#define GPIO_BOARD_ID2		GPIO(20, 4)
+#define GPIO_BOARD_ID3		GPIO( 2, 0)
+
+#define GPIO_BOOT_CONFIG0	GPIO( 2, 2)
+#define GPIO_BOOT_CONFIG1	GPIO( 3, 1)
+#define GPIO_BOOT_CONFIG2	GPIO( 3, 4)
+#define GPIO_BOOT_CONFIG3	GPIO( 3, 5)
+
+#define GPIO_REQUEST_DFU1	GPIO( 0, 1)	// formerly known as HOLD_KEY
+#define GPIO_REQUEST_DFU2	GPIO( 0, 0)	// formerly known as MENU_KEY
+#define GPIO_FORCE_DFU		GPIO( 3, 2)
+#define GPIO_DFU_STATUS		GPIO( 3, 3)
+
+#define SPI_NOR0		(0)
+#define SPI_NOR3		(3)
+
+#if SUPPORT_FPGA
+#define GPIO_SPI0_CS		GPIO(GPIO_PAD_SPI, 0)
+#define GPIO_SPI3_CS		GPIO(GPIO_PAD_SPI, 3)
+#else
+#define GPIO_SPI0_CS		GPIO(20, 5)
+#define GPIO_SPI3_CS		GPIO(18, 7)
+#endif
+
+#define GPIO_UART1_TXD		GPIO( 5, 3)
+
+#define GPIO_SYSTEM_RESET	GPIO(28, 0)
+
+#endif /* ! __PLATFORM_GPIODEF_S5L8940X_H */

platform/s5l8940x/include/platform/gpiodef_s5l8942x.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2011-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_GPIODEF_S5L8942X_H
+#define __PLATFORM_GPIODEF_S5L8942X_H
+
+/* S5L8942X specific gpio -> pin mappings */
+
+#if !SUB_PLATFORM_S5L8942X
+#error "Only include for S5L8942X platform"
+#endif
+
+/* define platform-specific gpios in a generic fashion here. */
+#define GPIO_IIC0_SCL		GPIO( 6, 5)
+#define GPIO_IIC0_SDA		GPIO( 6, 4)
+#define GPIO_IIC1_SCL		GPIO( 6, 7)
+#define GPIO_IIC1_SDA		GPIO( 6, 6)
+#define GPIO_IIC2_SCL		GPIO(24, 1)
+#define GPIO_IIC2_SDA		GPIO(24, 0)
+
+#define GPIO_BOARD_ID0		GPIO(12, 0)
+#define GPIO_BOARD_ID1		GPIO(12, 1)
+#define GPIO_BOARD_ID2		GPIO(12, 2)
+#define GPIO_BOARD_ID3		GPIO( 2, 0)
+
+#define GPIO_BOOT_CONFIG0	GPIO( 2, 2)
+#define GPIO_BOOT_CONFIG1	GPIO( 3, 1)
+#define GPIO_BOOT_CONFIG2	GPIO( 3, 4)
+#define GPIO_BOOT_CONFIG3	GPIO( 3, 5)
+
+#define GPIO_REQUEST_DFU1	GPIO( 0, 1)	// formerly known as HOLD_KEY
+#define GPIO_REQUEST_DFU2	GPIO( 0, 0)	// formerly known as MENU_KEY
+#define GPIO_FORCE_DFU		GPIO( 3, 2)
+#define GPIO_DFU_STATUS		GPIO( 3, 3)
+
+#define SPI_NOR0		(0)
+#define SPI_NOR3		(3)
+
+#if SUPPORT_FPGA
+#define GPIO_SPI0_CS		GPIO(GPIO_PAD_SPI, 0)
+#define GPIO_SPI3_CS		GPIO(GPIO_PAD_SPI, 3)
+#else
+#define GPIO_SPI0_CS		GPIO(12, 3)
+#define GPIO_SPI3_CS		GPIO(16, 3)
+#endif
+
+#define GPIO_UART1_TXD		GPIO( 5, 0)
+
+#define GPIO_SYSTEM_RESET	GPIO(25, 0)
+
+#endif /* ! __PLATFORM_GPIODEF_S5L8942X_H */

platform/s5l8940x/include/platform/gpiodef_s5l8947x.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2011-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_GPIODEF_S5L8947X_H
+#define __PLATFORM_GPIODEF_S5L8947X_H
+
+/* S5L8947X specific gpio -> pin mappings */
+
+#if !SUB_PLATFORM_S5L8947X
+#error "Only include for S5L8947X platform"
+#endif
+
+/* define platform-specific gpios in a generic fashion here. */
+#define GPIO_IIC0_SCL		GPIO(17, 1)
+#define GPIO_IIC0_SDA		GPIO(17, 0)
+#define GPIO_IIC1_SCL		GPIO( 1, 2)
+#define GPIO_IIC1_SDA		GPIO( 1, 1)
+#define GPIO_IIC2_SCL		GPIO( 1, 6)
+#define GPIO_IIC2_SDA		GPIO( 1, 5)
+
+#define GPIO_BOARD_ID0		GPIO(17, 3)
+#define GPIO_BOARD_ID1		GPIO(17, 4)
+#define GPIO_BOARD_ID2		GPIO(17, 5)
+#define GPIO_BOARD_ID3		GPIO(14, 0)
+
+#define GPIO_BOOT_CONFIG0	GPIO(14, 2)
+#define GPIO_BOOT_CONFIG1	GPIO(16, 3)
+#define GPIO_BOOT_CONFIG2	GPIO(16, 6)
+#define GPIO_BOOT_CONFIG3	GPIO(16, 7)
+
+#define GPIO_REQUEST_DFU1	GPIO(12, 1)	// formerly known as HOLD_KEY
+#define GPIO_REQUEST_DFU2	GPIO(12, 0)	// formerly known as MENU_KEY
+#define GPIO_FORCE_DFU		GPIO(16, 4)
+#define GPIO_DFU_STATUS		GPIO(16, 5)
+
+#define SPI_NOR0		(0)
+
+#if SUPPORT_FPGA
+#define GPIO_SPI0_CS		GPIO(GPIO_PAD_SPI, 0)
+#else
+#define GPIO_SPI0_CS		GPIO(17, 3)
+#endif
+
+#define GPIO_UART1_TXD		GPIO( 0, 7)
+
+#define GPIO_SYSTEM_RESET	GPIO( 3, 4)
+
+#endif /* ! __PLATFORM_GPIODEF_S5L8947X_H */

platform/s5l8940x/include/platform/image_devices.h

@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2009 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_IMAGE_DEVICES_H
+#define __PLATFORM_IMAGE_DEVICES_H
+
+static const struct image_device platform_image_devices[] = {
+#if defined(WITH_NAND_BOOT)
+    { "nand_firmware", 0x00000 }
+#else    
+    { "nor0", 0x00000 }
+#endif
+};
+
+#if WITH_SYSCFG
+static const struct image_device platform_syscfg_devices[] = {
+#if defined(WITH_NAND_BOOT)
+       { "nand_syscfg", 0x00000 }
+#else
+       { "nor0", 0x00000 }
+#endif
+};
+#endif /* WITH_SYSCFG */
+
+#endif /* ! __PLATFORM_IMAGE_DEVICES_H */

platform/s5l8940x/include/platform/memconfig.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2009 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_MEMCONFIG_H
+#define __PLATFORM_MEMCONFIG_H
+
+/* S5L8940X SoC Mem Pin Configuration */
+
+static const gpio_t memory_interface_gpios[] = {
+	/* Not needed */
+};
+#endif /* ! __PLATFORM_MEMCONFIG_H */

platform/s5l8940x/include/platform/memmap.h

@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2009-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_MEMMAP_H
+#define __PLATFORM_MEMMAP_H
+
+#include <platform/memmap_defaults.h>
+
+/*
+ * 0xa0000000	SDRAM_END
+ * 0x9fffc000	PANIC_BASE
+ * 0x9ff00000	IBOOT_BASE
+ * 0x9f000000	DISPLAY_BASE
+ * 0x9e800000	MONITOR_BASE
+ */
+/* S5L8940X specific memory map */
+#define SDRAM_BASE			(0x80000000ULL)
+#define SDRAM_BANK_LEN			(0x10000000ULL)
+#define SDRAM_BANK_COUNT		(2)
+#define SDRAM_END			(SDRAM_BASE + (SDRAM_BANK_LEN * SDRAM_BANK_COUNT))
+#define VROM_BASE			(0x3F000000ULL)
+#define VROM_BANK_LEN			(0x00100000ULL)
+#define VROM_LEN			(0x00010000ULL)
+#define SRAM_BASE			(0x34000000ULL)
+#define SRAM_BANK_LEN			(0x00100000ULL)
+#define SRAM_LEN			(0x00040000ULL)
+
+/* Sleep token is stored at first physical page in kernel memory */
+#define SLEEP_TOKEN_BUFFER_BASE		(SDRAM_BASE)
+
+/* reserved area for panic info */
+#define PANIC_SIZE		(0x00004000ULL)
+#define PANIC_BASE		(SDRAM_END - PANIC_SIZE)
+
+/* reserved area for iBoot */
+#define IBOOT_SIZE		(0x00100000 - PANIC_SIZE)
+#define IBOOT_BASE		(PANIC_BASE - IBOOT_SIZE)
+#define PROTECTED_REGION_SIZE	IBOOT_SIZE
+
+/* reserved area for display */
+#ifndef DISPLAY_SIZE
+#define DISPLAY_SIZE		(0x00F00000ULL)
+#endif
+#define DISPLAY_BASE		(IBOOT_BASE - DISPLAY_SIZE)
+
+/* where to load the monitor/hypervisor */
+#ifdef HACK_MONITOR
+#define MONITOR_SIZE		(0x00800000ULL)
+#else  /* !defined(HACK_MONITOR) */
+#define MONITOR_SIZE		(0)
+#endif /* defined(HACK_MONITOR) */
+#define MONITOR_BASE		(DISPLAY_BASE - MONITOR_SIZE)
+
+/* where to stick the mmu tt, default heap and insecure memory*/
+#if APPLICATION_SECUREROM
+#define MMU_TT_SIZE		(0x4000ULL)
+#define MMU_TT_BASE		(SRAM_BASE + SRAM_LEN - MMU_TT_SIZE)
+#define MMU_NONCACHE0_SIZE	(SRAM_BANK_LEN)
+#define MMU_NONCACHE0_PBASE	(SRAM_BASE)
+#define MMU_NONCACHE0_VBASE	(SRAM_BASE + SRAM_BANK_LEN * 3)
+
+#define STACK_SIZE		(0x3000ULL)
+#define STACK_BASE		(MMU_TT_BASE - STACK_SIZE)
+
+#define HEAP_END		(STACK_BASE)
+
+#ifndef __ASSEMBLY__
+
+#define INSECURE_MEMORY_BASE	(SRAM_BASE)
+#define INSECURE_MEMORY_SIZE	((uintptr_t)__segment_start(__DATA) - INSECURE_MEMORY_BASE)
+
+#endif /* ! __ASSEMBLY__ */
+
+#endif /* APPLICATION_SECUREROM */
+
+#if APPLICATION_IBOOT
+#define MMU_TT_SIZE		(0x4000ULL)
+#define MMU_TT_BASE		(TEXT_BASE + TEXT_FOOTPRINT - MMU_TT_SIZE)
+#define MMU_NONCACHE0_SIZE	(SRAM_BANK_LEN)
+#define MMU_NONCACHE0_PBASE	(SRAM_BASE)
+#define MMU_NONCACHE0_VBASE	(SRAM_BASE + SRAM_BANK_LEN * 3)
+#define MMU_NONCACHE1_SIZE	(0x40000000ULL)
+#define MMU_NONCACHE1_PBASE	(0x80000000ULL)
+#define MMU_NONCACHE1_VBASE	(0xC0000000ULL)
+
+#if WITH_DFU_MODE
+#define STACK_SIZE		(0x3000ULL)
+
+#define INSECURE_MEMORY_SIZE	(0x00200000ULL)
+#define INSECURE_MEMORY_BASE	(SDRAM_BASE + SDRAM_BANK_LEN - INSECURE_MEMORY_SIZE)
+
+#define HEAP_EXT_SIZE		(0x00100000ULL)
+#define HEAP_EXT_BASE		(INSECURE_MEMORY_BASE - HEAP_EXT_SIZE)
+
+#else /* !WITH_DFU_MODE */
+#define STACK_SIZE		(0x1000ULL)
+
+#define INSECURE_MEMORY_BASE	(SDRAM_BASE)
+#define INSECURE_MEMORY_SIZE	(DEFAULT_KERNEL_ADDRESS - SDRAM_BASE)
+
+#define SECURE_MEMORY_BASE	(INSECURE_MEMORY_BASE + INSECURE_MEMORY_SIZE)
+/* If only 1 bank is populated, this only clears to the alias of
+ * DISPLAY_BASE in the first bank. If 2 banks are populated, this
+ * clears all the was to DISPLAY_BASE in the second bank. */
+#define SECURE_MEMORY_SIZE	(DISPLAY_BASE - SECURE_MEMORY_BASE - SDRAM_BANK_LEN * 2 + platform_get_memory_size())
+
+#define HEAP_EXT_BASE		(DEFAULT_FREE_ADDRESS)
+#define HEAP_EXT_SIZE		(MONITOR_BASE - SDRAM_BANK_LEN - HEAP_EXT_BASE)
+#endif /* !WITH_DFU_MODE */
+
+#define STACK_BASE		(MMU_TT_BASE - STACK_SIZE)
+
+#define HEAP_END		(STACK_BASE)
+
+#endif /* APPLICATION_IBOOT */
+
+#if APPLICATION_EMBEDDEDIOP
+# if ARCH_ARMv7
+#  define MMU_TT_SIZE		(0x4000ULL)
+# endif
+
+#define AUDIO_SRAM_RESERVE	(0x1000ULL)
+#define USB_SRAM_RESERVE	(0x10000ULL)
+
+#if TARGET_S5L8940XAE2
+#define HEAP_EXT_BASE		(SRAM_BASE + AUDIO_SRAM_RESERVE)
+#define HEAP_EXT_SIZE		(SRAM_LEN - AUDIO_SRAM_RESERVE - USB_SRAM_RESERVE)
+#endif /* TARGET_S5L8940XAE2 */
+
+
+#endif /* !APPLICATION_EMBEDDEDIOP */
+
+#define SCRATCH_BASE     (0x33600000ULL)
+#define SCRATCH_LEN      (2048)
+
+#endif /* ! __PLATFORM_MEMMAP_H */

platform/s5l8940x/include/platform/pinconfig_s5l8940x.h

@@ -0,0 +1,310 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_PINCONFIG_S5L8940X_H
+#define __PLATFORM_PINCONFIG_S5L8940X_H
+
+/* Default S5L8940X SoC Pin Configuration */
+
+#define FMI_DRIVE_STR	DRIVE_X3
+
+static const u_int32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
+/* Port  0 */
+	CFG_IN,								// GPIO0		-> MENU_KEY
+	CFG_IN,								// GPIO1		-> HOLD_KEY
+	CFG_DISABLED,							// GPIO2		->
+	CFG_DISABLED,							// GPIO3		->
+	CFG_DISABLED,							// GPIO4		->
+	CFG_DISABLED | PULL_DOWN,					// GPIO5		->
+	CFG_DISABLED,							// GPIO6		->
+	CFG_DISABLED | PULL_DOWN,					// GPIO7		->
+
+/* Port  1 */
+	CFG_DISABLED,							// GPIO8		->
+	CFG_DISABLED,							// GPIO9		->
+	CFG_DISABLED,							// GPIO10		->
+	CFG_DISABLED,							// GPIO11		->
+	CFG_DISABLED,							// GPIO12		->
+	CFG_DISABLED,							// GPIO13		->
+	CFG_DISABLED,							// GPIO14		->
+	CFG_DISABLED,							// GPIO15		->
+
+/* Port  2 */
+	CFG_DISABLED,							// GPIO16		-> BOARD_ID[3]
+	CFG_DISABLED,							// GPIO17		->
+	CFG_DISABLED,							// GPIO18		-> BOOT_CONFIG[0]
+	CFG_DISABLED | PULL_DOWN,					// GPIO19		->
+	CFG_DISABLED,							// GPIO20		->
+	CFG_DISABLED,							// GPIO21		->
+	CFG_DISABLED | PULL_DOWN,					// GPIO22		->
+	CFG_DISABLED,							// GPIO23		->
+
+/* Port  3 */
+	CFG_DISABLED | PULL_DOWN,					// GPIO24		->
+	CFG_DISABLED,							// GPIO25		-> BOOT_CONFIG[1]
+	CFG_IN | PULL_DOWN,						// GPIO26		-> FORCE_DFU
+	CFG_DISABLED | PULL_DOWN,					// GPIO27		-> DFU_STATUS
+	CFG_DISABLED,							// GPIO28		-> BOOT_CONFIG[2]
+	CFG_DISABLED,							// GPIO29		-> BOOT_CONFIG[3]
+	CFG_DISABLED,							// GPIO30		->
+	CFG_DISABLED,							// GPIO31		->
+
+/* Port  4 */
+	CFG_DISABLED,							// GPIO32		->
+	CFG_DISABLED,							// GPIO33		->
+	CFG_DISABLED,							// GPIO34		->
+	CFG_DISABLED,							// GPIO35		->
+	CFG_DISABLED,							// GPIO36		->
+	CFG_DISABLED,							// GPIO37		->
+	CFG_DISABLED,							// GPIO38		->
+	CFG_DISABLED,							// GPIO39		->
+
+/* Port  5 */
+	CFG_DISABLED,							// EHCI_PORT_PWR[0]	->
+	CFG_DISABLED,							// EHCI_PORT_PWR[1]	->
+	CFG_DISABLED,							// EHCI_PORT_PWR[2]	->
+	CFG_DISABLED,							// UART1_TXD		->
+	CFG_DISABLED,							// UART1_RXD		->
+	CFG_DISABLED,							// UART1_RTSN		->
+	CFG_DISABLED,							// UART1_CTSN		->
+	CFG_DISABLED,							// UART2_TXD		->
+
+/* Port  6 */
+	CFG_DISABLED,							// UART2_RXD		->
+	CFG_DISABLED,							// UART2_RTSN		->
+	CFG_DISABLED,							// UART2_CTSN		->
+	CFG_DISABLED,							// UART3_TXD		->
+	CFG_DISABLED,							// UART3_RXD		->
+	CFG_DISABLED,							// UART3_RTSN		->
+	CFG_DISABLED,							// UART3_CTSN		->
+	CFG_DISABLED,							// UART5_RTXD		->
+
+/* Port  7 */
+	CFG_DISABLED,							// UART6_TXD		->
+	CFG_DISABLED,							// UART6_RXD		->
+	CFG_DISABLED,							// UART6_RTSN		->
+	CFG_DISABLED,							// UART6_CTSN		->
+	CFG_DISABLED,							// UART4_TXD/SPI4_MOSI	->
+	CFG_DISABLED,							// UART4_RXD/SPI4_MISO	->
+	CFG_DISABLED,							// UART4_RTSN/SPI4_SCLK	->
+	CFG_DISABLED,							// UART4_CTSN/SPI4_SSIN	->
+
+/* Port  8 */
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN3		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN2		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN1		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_WEN		->
+
+/* Port  9 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO5		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO4		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO2		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO1		->
+
+/* Port 10 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO0		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN3		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN2		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN1		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_REN		->
+
+/* Port 11 */
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO5		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO4		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO2		->
+
+/* Port 12 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO1		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO0		->
+	CFG_DISABLED,							// FMI2_CEN3		->
+	CFG_DISABLED,							// FMI2_CEN2		->
+	CFG_DISABLED,							// FMI2_CEN1		->
+	CFG_DISABLED,							// FMI2_CEN0		->
+	CFG_DISABLED,							// FMI2_CLE		->
+	CFG_DISABLED,							// FMI2_ALE		->
+
+/* Port 13 */
+	CFG_DISABLED,							// FMI2_REN		->
+	CFG_DISABLED,							// FMI2_WEN		->
+	CFG_DISABLED,							// FMI2_IO7		->
+	CFG_DISABLED,							// FMI2_IO6		->
+	CFG_DISABLED,							// FMI2_IO5		->
+	CFG_DISABLED,							// FMI2_IO4		->
+	CFG_DISABLED,							// FMI2_DQS		->
+	CFG_DISABLED,							// FMI2_IO3		->
+
+/* Port 14 */
+	CFG_DISABLED,							// FMI2_IO2		->
+	CFG_DISABLED,							// FMI2_IO1		->
+	CFG_DISABLED,							// FMI2_IO0		->
+	CFG_DISABLED,							// FMI0_CEN7		->
+	CFG_DISABLED,							// FMI0_CEN6		->
+	CFG_DISABLED,							// FMI0_CEN5		->
+	CFG_DISABLED,							// FMI0_CEN4		->
+	CFG_DISABLED,							// FMI1_CEN7		->
+
+/* Port 15 */
+	CFG_DISABLED,							// FMI1_CEN6		->
+	CFG_DISABLED,							// FMI1_CEN5		->
+	CFG_DISABLED,							// FMI1_CEN4		->
+	CFG_DISABLED,							// FMI3_CEN3		->
+	CFG_DISABLED,							// FMI3_CEN2		->
+	CFG_DISABLED,							// FMI3_CEN1		->
+	CFG_DISABLED,							// FMI3_CEN0		->
+	CFG_DISABLED,							// FMI3_CLE		->
+
+/* Port 16 */
+	CFG_DISABLED,							// FMI3_ALE		->
+	CFG_DISABLED,							// FMI3_REN		->
+	CFG_DISABLED,							// FMI3_WEN		->
+	CFG_DISABLED,							// FMI3_IO7		->
+	CFG_DISABLED,							// FMI3_IO6		->
+	CFG_DISABLED,							// FMI3_IO5		->
+	CFG_DISABLED,							// FMI3_IO4		->
+	CFG_DISABLED,							// FMI3_DQS		->
+
+/* Port 17 */
+	CFG_DISABLED,							// FMI3_IO3		->
+	CFG_DISABLED,							// FMI3_IO2		->
+	CFG_DISABLED,							// FMI3_IO1		->
+	CFG_DISABLED,							// FMI3_IO0		->
+	CFG_DISABLED,							// FMI2_CEN7		->
+	CFG_DISABLED,							// FMI2_CEN6		->
+	CFG_DISABLED,							// FMI2_CEN5		->
+	CFG_DISABLED,							// FMI2_CEN4		->
+
+/* Port 18 */
+	CFG_DISABLED,							// FMI3_CEN7		->
+	CFG_DISABLED,							// FMI3_CEN6		->
+	CFG_DISABLED,							// FMI3_CEN5		->
+	CFG_DISABLED,							// FMI3_CEN4		->
+	CFG_DISABLED,							// SPI3_MOSI		-> 
+	CFG_DISABLED,							// SPI3_MISO		-> 
+	CFG_DISABLED,							// SPI3_SCLK		-> 
+	CFG_DISABLED,							// SPI3_SSIN		-> 
+
+/* Port 19 */
+	CFG_DISABLED,							// ISP0_PRE_FLASH	->
+	CFG_DISABLED,							// ISP0_FLASH		->
+	CFG_DISABLED,							// ISP1_PRE_FLASH	->
+	CFG_DISABLED,							// ISP1_FLASH		->
+	CFG_DISABLED,							// SPI1_SCLK		->
+	CFG_DISABLED,							// SPI1_MOSI		->
+	CFG_DISABLED,							// SPI1_MISO		->
+	CFG_DISABLED,							// SPI1_SSIN		->
+
+/* Port 20 */
+	CFG_DISABLED,							// I2C2_SDA		->
+	CFG_DISABLED,							// I2C2_SCL		->
+	CFG_DISABLED,							// SPI0_SCLK		-> SPI0_SCLK/BOARD_ID[0]
+	CFG_DISABLED,							// SPI0_MOSI		-> SPI0_MOSI/BOARD_ID[1]
+	CFG_DISABLED,							// SPI0_MISO		-> SPI0_MISO/BOARD_ID[2]
+	CFG_DISABLED | PULL_UP,						// SPI0_SSIN		-> SPI0_SSIN
+	CFG_DISABLED,							// SPI2_SCLK		->
+	CFG_DISABLED,							// SPI2_MOSI		->
+
+/* Port 21 */
+	CFG_DISABLED,							// SPI2_MISO		->
+	CFG_DISABLED,							// SPI2_SSIN		->
+	CFG_DISABLED,							// I2C0_SDA		->
+	CFG_DISABLED,							// I2C0_SCL		->
+	CFG_DISABLED,							// I2C1_SDA		->
+	CFG_DISABLED,							// I2C1_SCL		->
+	CFG_DISABLED,							// ISP0_SDA		->
+	CFG_DISABLED,							// ISP0_SCL		->
+
+/* Port 22 */
+	CFG_DISABLED,							// ISP1_SDA		->
+	CFG_DISABLED,							// ISP1_SCL		->
+	CFG_DISABLED,							// SDIO_CLK		->
+	CFG_DISABLED,							// SDIO_CMD		->
+	CFG_DISABLED,							// SDIO_DATA0		->
+	CFG_DISABLED,							// SDIO_DATA1		->
+	CFG_DISABLED,							// SDIO_DATA2		->
+	CFG_DISABLED,							// SDIO_DATA3		->
+
+/* Port 23 */
+	CFG_DISABLED,							// MIPI_VSYNC		->
+	CFG_DISABLED,							// TMR32_PWM0		->
+	CFG_DISABLED,							// TMR32_PWM1		->
+	CFG_DISABLED,							// TMR32_PWM2		->
+	CFG_DISABLED,							// SWI_DATA		->
+	CFG_DISABLED,							// DWI_DI		->
+	CFG_DISABLED,							// DWI_DO		->
+	CFG_DISABLED,							// DWI_CLK		->
+
+/* Port 24 */
+	CFG_DISABLED,							// SENSOR0_RST		->
+	CFG_DISABLED,							// SENSOR0_CLK		->
+	CFG_DISABLED,							// SENSOR1_RST		->
+	CFG_DISABLED,							// SENSOR1_CLK		->
+	CFG_DISABLED,							// I2S0_MCK		->
+	CFG_DISABLED,							// I2S0_LRCK		->
+	CFG_DISABLED,							// I2S0_BCLK		->
+	CFG_DISABLED,							// I2S0_DOUT		->
+
+/* Port 25 */
+	CFG_DISABLED,							// I2S0_DIN		->
+	CFG_DISABLED,							// I2S1_MCK		->
+	CFG_DISABLED,							// I2S1_LRCK		->
+	CFG_DISABLED,							// I2S1_BCLK		->
+	CFG_DISABLED,							// I2S1_DOUT		->
+	CFG_DISABLED,							// I2S1_DIN		->
+	CFG_DISABLED,							// I2S2_MCK		->
+	CFG_DISABLED,							// I2S2_LRCK		->
+
+/* Port 26 */
+	CFG_DISABLED,							// I2S2_BCLK		->
+	CFG_DISABLED,							// I2S2_DOUT		->
+	CFG_DISABLED,							// I2S2_DIN		->
+	CFG_DISABLED,							// I2S3_MCK		->
+	CFG_DISABLED,							// I2S3_LRCK		->
+	CFG_DISABLED,							// I2S3_BCLK		->
+	CFG_DISABLED,							// I2S3_DOUT		->
+	CFG_DISABLED,							// I2S3_DIN		->
+
+/* Port 27 */
+	CFG_DISABLED,							// SPDIF		->
+	CFG_DISABLED | PULL_DOWN,					// GPIO217		->
+	CFG_DISABLED,							// GPIO218		->
+	CFG_DISABLED,							// DP_HPD		->
+	CFG_DISABLED,							// UART0_TXD		->
+	CFG_DISABLED,							// UART0_RXD		->
+	CFG_DISABLED,							// TST_CLKOUT		->
+	CFG_DISABLED,							// TST_STPCLK		->
+
+/* Port 28 */
+	CFG_DISABLED,							// WDOG			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+};
+
+#endif /* ! __PLATFORM_PINCONFIG_S5L8940X_H */

platform/s5l8940x/include/platform/pinconfig_s5l8942x.h

@@ -0,0 +1,281 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_PINCONFIG_S5L8942X_H
+#define __PLATFORM_PINCONFIG_S5L8942X_H
+
+/* Default S5L8942X SoC Pin Configuration */
+
+#define FMI_DRIVE_STR	DRIVE_X2
+#define FMI_SLEW_RATE	SLEW_RATE_SLOW
+
+static const u_int32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
+/* Port  0 */
+	CFG_IN,								// GPIO0		-> MENU_KEY
+	CFG_IN,								// GPIO1		-> HOLD_KEY
+	CFG_DISABLED,							// GPIO2		->
+	CFG_DISABLED,							// GPIO3		->
+	CFG_DISABLED,							// GPIO4		->
+	CFG_DISABLED,							// GPIO5		->
+	CFG_DISABLED,							// GPIO6		->
+	CFG_DISABLED,							// GPIO7		->
+
+/* Port  1 */
+	CFG_DISABLED,							// GPIO8		->
+	CFG_DISABLED,							// GPIO9		->
+	CFG_DISABLED,							// GPIO10		->
+	CFG_DISABLED,							// GPIO11		->
+	CFG_DISABLED,							// GPIO12		->
+	CFG_DISABLED,							// GPIO13		->
+	CFG_DISABLED,							// GPIO14		->
+	CFG_DISABLED,							// GPIO15		->
+
+/* Port  2 */
+	CFG_DISABLED,							// GPIO16		-> BOARD_ID[3]
+	CFG_DISABLED,							// GPIO17		->
+	CFG_DISABLED,							// GPIO18		-> BOOT_CONFIG[0]
+	CFG_DISABLED,							// GPIO19		-> KEEPACT
+	CFG_DISABLED,							// GPIO20		->
+	CFG_DISABLED,							// GPIO21		->
+	CFG_DISABLED,							// GPIO22		->
+	CFG_DISABLED,							// GPIO23		->
+
+/* Port  3 */
+	CFG_DISABLED,							// GPIO24		->
+	CFG_DISABLED,							// GPIO25		-> BOOT_CONFIG[1]
+	CFG_IN | PULL_DOWN,						// GPIO26		-> FORCE_DFU
+	CFG_DISABLED | PULL_DOWN,					// GPIO27		-> DFU_STATUS
+	CFG_DISABLED,							// GPIO28		-> BOOT_CONFIG[2]
+	CFG_DISABLED,							// GPIO29		-> BOOT_CONFIG[3]
+	CFG_DISABLED,							// GPIO30		->
+	CFG_DISABLED,							// GPIO31		->
+
+/* Port  4 */
+	CFG_DISABLED,							// GPIO32		->
+	CFG_DISABLED,							// GPIO33		->
+	CFG_DISABLED,							// GPIO34		->
+	CFG_DISABLED,							// GPIO35		->
+	CFG_DISABLED,							// GPIO36		->
+	CFG_DISABLED,							// EHCI_PORT_PWR[0]	-> BOARD_REV[0]
+	CFG_DISABLED,							// EHCI_PORT_PWR[1]	-> BOARD_REV[1]
+	CFG_DISABLED,							// EHCI_PORT_PWR[2]	-> BOARD_REV[2]
+
+/* Port  5 */
+	CFG_DISABLED,							// UART1_TXD		->
+	CFG_DISABLED,							// UART1_RXD		->
+	CFG_DISABLED,							// UART1_RTSN		->
+	CFG_DISABLED,							// UART1_CTSN		->
+	CFG_DISABLED,							// UART2_TXD		->
+	CFG_DISABLED,							// UART2_RXD		->
+	CFG_DISABLED,							// UART2_RTSN		->
+	CFG_DISABLED,							// UART2_CTSN		->
+
+/* Port  6 */
+	CFG_DISABLED,							// UART3_TXD		->
+	CFG_DISABLED,							// UART3_RXD		->
+	CFG_DISABLED,							// UART3_RTSN		->
+	CFG_DISABLED,							// UART3_CTSN		->
+	CFG_DISABLED,							// I2C0_SDA		->
+	CFG_DISABLED,							// I2C0_SCL		->
+	CFG_DISABLED,							// I2C1_SDA		->
+	CFG_DISABLED,							// I2C1_SCL		->
+
+/* Port  7 */
+	CFG_DISABLED,							// ISP0_SDA		->
+	CFG_DISABLED,							// ISP0_SCL		->
+	CFG_DISABLED,							// ISP1_SDA		->
+	CFG_DISABLED,							// ISP1_SCL		->
+	CFG_DISABLED,							// UART5_TXD/MIPI_VSYNC	->
+	CFG_DISABLED,							// TMR32_PWM0
+	CFG_DISABLED,							// TMR32_PWM1
+	CFG_DISABLED,							// TMR32_PWM2
+
+/* Port  8 */
+	CFG_DISABLED,							// SWI_DATA		->
+	CFG_DISABLED,							// DWI_DI		->
+	CFG_DISABLED,							// DWI_DO		->
+	CFG_DISABLED,							// DWI_CLK		->
+	CFG_DISABLED,							// SENSOR0_RST		->
+	CFG_DISABLED,							// SENSOR0_CLK		->
+	CFG_DISABLED,							// SENSOR1_RST		->
+	CFG_DISABLED,							// SENSOR1_CLK		->
+
+/* Port  9 */
+	CFG_DISABLED,							// ISP0_PRE_FLASH	->
+	CFG_DISABLED,							// ISP0_FLASH		->
+	CFG_DISABLED,							// ISP1_PRE_FLASH	->
+	CFG_DISABLED,							// ISP1_FLASH		->
+	CFG_DISABLED,							// I2S0_MCK		->
+	CFG_DISABLED,							// I2S0_LRCK		->
+	CFG_DISABLED,							// I2S0_SCLK		->
+	CFG_DISABLED,							// I2S0_DOUT		->
+
+/* Port 10 */
+	CFG_DISABLED,							// I2S0_DIN		->
+	CFG_DISABLED,							// I2S1_MCK		->
+	CFG_DISABLED,							// I2S1_LRCK		->
+	CFG_DISABLED,							// I2S1_SCLK		->
+	CFG_DISABLED,							// I2S1_DOUT		->
+	CFG_DISABLED,							// I2S1_DIN		->
+	CFG_DISABLED,							// I2S2_MCK		->
+	CFG_DISABLED,							// I2S2_LRCK		->
+
+/* Port 11 */
+	CFG_DISABLED,							// I2S2_BCLK		->
+	CFG_DISABLED,							// I2S2_DOUT		->
+	CFG_DISABLED,							// I2S2_DIN		->
+	CFG_DISABLED,							// I2S2_MCK		->
+	CFG_DISABLED,							// I2S3_LRCK		->
+	CFG_DISABLED,							// I2S3_BCLK		->
+	CFG_DISABLED,							// I2S3_DOUT		->
+	CFG_DISABLED,							// I2S3_DIN		->
+
+/* Port 12 */
+	CFG_DISABLED,							// SPI0_SCLK		-> BOARD_ID[0]
+	CFG_DISABLED,							// SPI0_MOSI		-> BOARD_ID[1]
+	CFG_DISABLED,							// SPI0_MISO		-> BOARD_ID[2]
+	CFG_DISABLED | PULL_UP,						// SPI0_SSIN		->
+	CFG_DISABLED,							// SPI1_SCLK		->
+	CFG_DISABLED,							// SPI1_MOSI		->
+	CFG_DISABLED,							// SPI1_MISO		->
+	CFG_DISABLED,							// SPI1_SSIN		->
+
+/* Port 13 */
+	CFG_DISABLED,							// SPI2_SCLK		->
+	CFG_DISABLED,							// SPI2_MOSI		->
+	CFG_DISABLED,							// SPI2_MISO		->
+	CFG_DISABLED,							// SPI2_SSIN		->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 14 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 15 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 16 */
+	CFG_DISABLED,							// UART4_TXD		-> SPI3_SCLK/FMI0_CEN7
+	CFG_DISABLED,							// UART4_RXD		-> SPI3_MOSI/FMI0_CEN6
+	CFG_DISABLED,							// UART4_RTSN		-> SPI3_MISO/FMI0_CEN5
+	CFG_DISABLED,							// UART4_CTSN		-> SPI3_SSIN/FMI0_CEN4
+	CFG_DISABLED,							// SDIO0_DATA3		-> FMI1_CEN7
+	CFG_DISABLED,							// SDIO0_DATA2		-> FMI1_CEN6
+	CFG_DISABLED,							// SDIO0_DATA1		-> FMI1_CEN5
+	CFG_DISABLED,							// SDIO0_DATA0		-> FMI1_CEN4
+
+/* Port 17 */
+	CFG_DISABLED,							// SDIO0_CMD		->
+	CFG_DISABLED,							// SDIO0_CLK		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN3		-> FMI0_RBN0
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN2		-> FMI0_RBN1
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN1		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_ALE		->
+
+/* Port 18 */
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO5		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO4		->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 19 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 20 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO2		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO1		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO0		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN3		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN2		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN1		->
+
+/* Port 21 */
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO5		->
+
+/* Port 22 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO4		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO2		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO1		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO0		->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 23 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 24 */
+	CFG_DISABLED,							// I2C2_SDA		->
+	CFG_DISABLED,							// I2C2_SCL		->
+	CFG_DISABLED,							// UART0_TXD		->
+	CFG_DISABLED,							// UART0_RXD		->
+	CFG_DISABLED,							// UART5_RTXD		-> UART5_RXD
+	CFG_DISABLED,							// DP_HPD		->
+	CFG_DISABLED,							// TST_CLKOUT		->
+	CFG_DISABLED,							// TST_STPCLK		->
+
+/* Port 25 */
+	CFG_DISABLED,							// WDOG			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+};
+
+#endif /* ! __PLATFORM_PINCONFIG_S5L8942X_H */

platform/s5l8940x/include/platform/pinconfig_s5l8947x.h

@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_PINCONFIG_S5L8947X_H
+#define __PLATFORM_PINCONFIG_S5L8947X_H
+
+/* Default S5L8947X SoC Pin Configuration */
+
+#define FMI_DRIVE_STR	DRIVE_X2
+#define FMI_SLEW_RATE	SLEW_RATE_SLOW
+
+static const u_int32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
+/* Port  0 */
+	CFG_DISABLED,							// I2S0_MCK		->
+	CFG_IN,								// I2S0_LRCK		->
+	CFG_DISABLED,							// I2S0_BCLK		->
+	CFG_DISABLED,							// I2S0_DOUT		->
+	CFG_DISABLED,							// I2S0_DIN		->
+	CFG_DISABLED,							// UART0_TXD		->
+	CFG_DISABLED,							// UART0_RXD		->
+	CFG_DISABLED,							// UART1_TXD		->
+
+/* Port  1 */
+	CFG_DISABLED,							// UART1_RXD		->
+	CFG_DISABLED,							// I2C1_SDA		->
+	CFG_DISABLED,							// I2C1_SCL		->
+	CFG_DISABLED,							// HDMI_HPD		->
+	CFG_DISABLED,							// HDMI_CEC		->
+	CFG_DISABLED,							// I2C2_SDA		->
+	CFG_DISABLED,							// I2C2_SCL		->
+	CFG_DISABLED,							// SPDIF		->
+
+/* Port  2 */
+	CFG_DISABLED,							// GPIO22		->
+	CFG_DISABLED,							// GPIO23		->
+	CFG_DISABLED,							// UART2_TXD		->
+	CFG_DISABLED,							// UART2_RXD		->
+	CFG_DISABLED,							// UART2_RTSN		->
+	CFG_DISABLED,							// UART2_CTSN		->
+	CFG_DISABLED,							// UART3_TXD		->
+	CFG_DISABLED,							// UART3_RXD		->
+
+/* Port  3 */
+	CFG_DISABLED,							// UART4_TXD		->
+	CFG_DISABLED,							// UART4_RXD		->
+	CFG_DISABLED,							// TST_CLKOUT		->
+	CFG_DISABLED | PULL_DOWN,					// TST_STPCLK		->
+	CFG_DISABLED,							// WDOG			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port  4 */
+	CFG_DISABLED,							// ENET_MDC		->
+	CFG_DISABLED,							// ENET_MDIO		->
+	CFG_DISABLED,							// RMII_CLK		->
+	CFG_DISABLED,							// RMII_RXER		->
+	CFG_DISABLED,							// RMII_TXD[0]		->
+	CFG_DISABLED,							// RMII_CRSDV		->
+	CFG_DISABLED,							// RMII_RXD[0]		->
+	CFG_DISABLED,							// RMII_RXD[1]		->
+
+/* Port  5 */
+	CFG_DISABLED,							// RMII_TXD[1]		->
+	CFG_DISABLED,							// RMII_TXEN		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN[1]		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN[0]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_WEN		->
+
+/* Port  6 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[7]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[6]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[5]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[4]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[3]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[2]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[1]		->
+
+/* Port  7 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO[0]		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN[1]		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN[0]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[7]		->
+
+/* Port  8 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[6]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[5]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[4]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[3]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[2]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[1]		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO[0]		->
+
+/* Port  9 */
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+
+/* Port 10 */
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+
+/* Port 11 */
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+	CFG_DISABLED,							//
+
+/* Port 12 */
+	CFG_IN,								// GPIO0		-> MENU_KEY
+	CFG_IN,								// GPIO1		-> HOLD_KEY
+	CFG_DISABLED,							// GPIO2		->
+	CFG_DISABLED,							// GPIO3		->
+	CFG_DISABLED,							// GPIO4		->
+	CFG_DISABLED,							// GPIO5		->
+	CFG_DISABLED,							// GPIO6		->
+	CFG_DISABLED,							// GPIO7		->
+
+/* Port 13 */
+	CFG_DISABLED,							// GPIO8		->
+	CFG_DISABLED,							// GPIO9		->
+	CFG_DISABLED,							// GPIO10		->
+	CFG_DISABLED,							// GPIO11		->
+	CFG_DISABLED,							// GPIO12		->
+	CFG_DISABLED,							// GPIO13		->
+	CFG_DISABLED,							// GPIO14		->
+	CFG_DISABLED,							// GPIO15		->
+
+/* Port 14 */
+	CFG_DISABLED,							// GPIO16		-> BOARD_ID[3]
+	CFG_DISABLED,							// GPIO17		->
+	CFG_DISABLED,							// GPIO18		-> BOOT_CONFIG[0]
+	CFG_DISABLED,							// GPIO19		-> KEEPACT
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 15 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 16 */
+	CFG_DISABLED,							// GPIO20		->
+	CFG_DISABLED,							// GPIO21		->
+	CFG_DISABLED,							// GPIO24		->
+	CFG_DISABLED,							// GPIO25		-> BOOT_CONFIG[1]
+	CFG_IN | PULL_DOWN,						// GPIO26		-> FORCE_DFU
+	CFG_DISABLED | PULL_DOWN,					// GPIO27		-> DFU_STATUS
+	CFG_DISABLED,							// GPIO28		-> BOOT_CONFIG{2]
+	CFG_DISABLED,							// GPIO29		-> BOOT_CONFIG[3]
+
+/* Port 17 */
+	CFG_DISABLED,							// I2C0_SDA		->
+	CFG_DISABLED,							// I2C0_SCL		->
+	CFG_DISABLED,							// TMR32_PWM0		->
+	CFG_DISABLED,							// SPI0_SCLK		-> SPI0_SCLK/BOARD_ID[0]
+	CFG_DISABLED,							// SPI0_MOSI		-> SPI0_MOSI/BOARD_ID[1]
+	CFG_DISABLED,							// SPI0_MISO		-> SPI0_MISO/BOARD_ID[2]
+	CFG_DISABLED | PULL_UP,						// SPI0_SSIN		->
+	CFG_DISABLED,							// SWI_DATA		->
+};
+
+#endif /* ! __PLATFORM_PINCONFIG_S5L8947X_H */

platform/s5l8940x/include/platform/soc/chipid.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2009-2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_CHIPID_H
+#define __PLATFORM_SOC_CHIPID_H
+
+#include <platform/chipid.h>
+#include <platform/soc/hwregbase.h>
+
+#define	rCFG_FUSE0			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x00))
+#define	rCFG_FUSE1			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x04))
+#define	rCFG_FUSE2			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x08))
+#define	rCFG_FUSE3			(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x0C))
+
+#define	rECIDLO				(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x10))
+#define	rECIDHI				(*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x14))
+
+extern bool	chipid_get_ecid_image_personalization_required(void);
+
+#define CHIPID_SOC_VOLTAGE_LOW		(0)
+#define CHIPID_SOC_VOLTAGE_MED		(1)
+#define CHIPID_SOC_VOLTAGE_HIGH		(2)
+extern u_int32_t chipid_get_soc_voltage(u_int32_t index);
+
+#define CHIPID_CPU_VOLTAGE_LOW		(0)
+#define CHIPID_CPU_VOLTAGE_MED		(1)
+#define CHIPID_CPU_VOLTAGE_HIGH		(2)
+extern u_int32_t chipid_get_cpu_voltage(u_int32_t index);
+
+#endif /* __PLATFORM_SOC_CHIPID_H */

platform/s5l8940x/include/platform/soc/display.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2012-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __APPLE_DISPLAY_H
+#define __APPLE_DISPLAY_H
+
+// Platform-specific displaypipe tunables
+static struct adfe_v1_tuneable adfe_tuneables[] = 
+{
+	{
+		.name = "default",
+		.disp_dpcclkcntl[0] = 			0,
+		.disp_dpbclklvl_clock_off_level[0] =	DPBCLKLVL_OFFLVL(0x01f0),
+		.disp_dpbclklvl_clock_on_level[0] =	DPBCLKLVL_ONLVL(0x0180),
+		.disp_dpusrcstrd[0] =			DPUSRCSTRD_SRCBURST_4BLOCKS,
+		.disp_dpcqoscnfg[0] =			(DPCQOSCNFG_QOS_TIMER(0x0040) | \
+							 DPCQOSCNFG_QOS_ENABLE),
+		.disp_dpbqoslvl_med_watermark[0] =	DPBQOSLVL_MED_WATERMARK(0x0100),
+		.disp_dpbqoslvl_high_watermark[0] =	DPBQOSLVL_HIGH_WATERMARK(0x0000),
+		.disp_dpureqcfg[0] =			0,
+
+		.disp_dpcclkcntl[1] = 			0,
+		.disp_dpbclklvl_clock_off_level[1] =	DPBCLKLVL_OFFLVL(0x01f0),
+		.disp_dpbclklvl_clock_on_level[1] =	DPBCLKLVL_ONLVL(0x01c0),
+		.disp_dpusrcstrd[1] =			DPUSRCSTRD_SRCBURST_4BLOCKS,
+		.disp_dpcqoscnfg[1] =			(DPCQOSCNFG_QOS_TIMER(0x0040) | \
+							 DPCQOSCNFG_QOS_ENABLE),
+		.disp_dpbqoslvl_med_watermark[1] =	DPBQOSLVL_MED_WATERMARK(0x0100),
+		.disp_dpbqoslvl_high_watermark[1] =	DPBQOSLVL_HIGH_WATERMARK(0x0000),
+		.disp_dpureqcfg[1] =			0,
+	},
+};
+
+#endif	/* ! __APPLE_DISPLAY_H */

platform/s5l8940x/include/platform/soc/display_timings.h

@@ -0,0 +1,222 @@
+/*
+ * Copyright (C) 2013-2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __APPLE_DISPLAY_TIMINGS_H
+#define __APPLE_DISPLAY_TIMINGS_H
+
+//Supported timings by this platform
+static struct display_timing timing_list[] =
+{
+#if DEBUG_BUILD || SUB_TARGET_K93 || SUB_TARGET_K94 || SUB_TARGET_K95 || SUB_TARGET_K93A
+	{ 
+	.display_name = 	"k48",	
+	.host_clock_id = 	CLK_VCLK0, 
+	.pixel_clock = 		68400000, 
+	.dot_pitch = 		132, 
+	.h_active =		1024,
+	.h_pulse_width = 	135, 
+	.h_back_porch = 	133,
+	.h_front_porch =        133,
+	.v_active = 		768, 
+	.v_pulse_width =  	12, 
+	.v_back_porch = 	10, 
+	.v_front_porch =        10, 
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	18, 
+	.display_type = 	DISPLAY_TYPE_PINOT, 
+	.display_config		= NULL,
+	},
+#endif
+#if DEBUG_BUILD || SUB_TARGET_N94
+	{ 
+	.display_name = 	"n94",	
+	.host_clock_id = 	CLK_VCLK0, 
+	.pixel_clock = 		51300000, 
+	.dot_pitch = 		326,
+	.h_active =		640, 
+	.h_pulse_width =	73, 
+	.h_back_porch =		71, 
+	.h_front_porch =       	71, 
+	.v_active = 		960, 
+	.v_pulse_width =  	16, 
+	.v_back_porch = 	12, 
+	.v_front_porch =       	12, 
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	24, 
+	.display_type = 	DISPLAY_TYPE_PINOT, 
+	.display_config		= NULL,
+	},
+	
+	{ 
+	.display_name = 	"n94-2",	
+	.host_clock_id = 	CLK_VCLK0, 
+	.pixel_clock = 		51300000, 
+	.dot_pitch = 		326, 
+	.h_active =		640, 
+	.h_pulse_width = 	73, 
+	.h_back_porch = 	71, 
+	.h_front_porch =       	71, 
+	.v_active = 		960,
+	.v_pulse_width =  	16, 
+	.v_back_porch = 	12, 
+	.v_front_porch =       	12, 
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	24, 
+	.display_type = 	DISPLAY_TYPE_PINOT, 
+	.display_config		= NULL,
+	},
+	
+	{ 
+	.display_name = 	"d300",	
+	.host_clock_id = 	CLK_VCLK0, 
+	.pixel_clock = 		60350000, 
+	.dot_pitch = 		326, 
+	.h_active =		640,
+	.h_pulse_width = 	48, 
+	.h_back_porch = 	48, 
+	.h_front_porch =       	48, 
+	.v_active = 		960,
+	.v_pulse_width =	3,  
+	.v_back_porch = 	13, 
+	.v_front_porch =       	307, 
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	24, 
+	.display_type = 	DISPLAY_TYPE_PINOT, 
+	.display_config		= NULL,
+	},
+#endif
+#if DEBUG_BUILD || SUB_TARGET_P105 || SUB_TARGET_P106 || SUB_TARGET_P107
+	{ 
+	.display_name = 	"ipad2b",	
+	.host_clock_id = 	CLK_VCLK0, 
+	.pixel_clock = 		68400000, 
+	.dot_pitch = 		163, 
+	.h_active =		768,
+	.h_pulse_width = 	80, 
+	.h_back_porch = 	76,
+	.h_front_porch =        76,
+	.v_active = 		1024,
+	.v_pulse_width =  	40, 
+	.v_back_porch = 	38, 
+	.v_front_porch =        38,
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	18, 
+	.display_type = 	DISPLAY_TYPE_PINOT, 
+	.display_config		= NULL,
+	},
+	
+	{ 
+	.display_name = 	"ipad2b-p0",
+	.host_clock_id =	CLK_VCLK0, 
+	.pixel_clock = 		68400000, 
+	.dot_pitch = 		163, 
+	.h_active =		768,
+	.h_pulse_width = 	80, 
+	.h_back_porch = 	113,
+	.h_front_porch =       	113,
+	.v_active = 		1024,
+	.v_pulse_width =  	18, 
+	.v_back_porch = 	10, 
+	.v_front_porch =       	10, 
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	18, 
+	.display_type = 	DISPLAY_TYPE_PINOT, 
+	.display_config		= NULL,
+	},
+#endif
+#if DEBUG_BUILD || WITH_HW_DISPLAY_DISPLAYPORT
+	{ 
+	.display_name = 	"720p",	
+	.host_clock_id = 	CLK_VCLK1, 
+	.pixel_clock = 		74250000,
+	.dot_pitch = 		243, 
+	.h_active =		1280,
+	.h_pulse_width = 	40,  
+	.h_back_porch = 	220, 
+	.h_front_porch =        110, 
+	.v_active = 		720,
+	.v_pulse_width =  	5, 
+	.v_back_porch = 	20, 
+	.v_front_porch =        5, 
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	24, 
+	.display_type = 	DISPLAY_TYPE_DP,     
+	.display_config		= NULL,
+	},
+#endif
+#if DEBUG_BUILD || SUB_TARGET_N78
+	{ 
+	.display_name = 	"n41",	
+	.host_clock_id = 	CLK_VCLK0, 
+	.pixel_clock = 		68400000, 
+	.dot_pitch = 		326, 
+	.h_active =		640,
+	.h_pulse_width = 	40,  
+	.h_back_porch = 	40, 
+	.h_front_porch =       	40,
+	.v_active = 		1136,
+	.v_pulse_width =  	3,  
+	.v_back_porch = 	13, 
+	.v_front_porch =       	348, 
+	.neg_vclk = 		0, 
+	.neg_hsync = 		0, 
+	.neg_vsync = 		0, 
+	.neg_vden = 		0, 
+	.display_depth = 	24, 
+	.display_type = 	DISPLAY_TYPE_PINOT, 
+	.display_config		= NULL,
+	},
+#endif
+#if DEBUG_BUILD || WITH_HW_DISPLAY_HDMI
+	{ 
+	.display_name =   	"720p-hdmi",	
+	.host_clock_id =  	CLK_VCLK1, 
+	.pixel_clock = 	  	74250000, 
+	.dot_pitch = 	  	243, 
+	.h_active =	  	1280,
+	.h_pulse_width =  	40, 
+	.h_back_porch =   	220, 
+	.h_front_porch =  	110, 
+	.v_active = 	  	720,
+	.v_pulse_width =  	5,  
+	.v_back_porch =   	20, 
+	.v_front_porch =  	5,
+	.neg_vclk = 	  	0, 
+	.neg_hsync = 	  	0, 
+	.neg_vsync = 	 	0, 
+	.neg_vden = 	  	0, 
+	.display_depth =  	24, 
+	.display_type =   	DISPLAY_TYPE_HDMI,     
+	.display_config		= NULL,
+	},
+#endif
+};
+#endif	/* ! __APPLE_DISPLAY_TIMINGS_H */

platform/s5l8940x/include/platform/soc/hwclocks.h

@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2009 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWCLOCKS_H
+#define __PLATFORM_SOC_HWCLOCKS_H
+
+#include <platform/clocks.h>
+
+#if SUPPORT_FPGA
+#if SUB_PLATFORM_S5L8947X
+#define OSC_FREQ			(7500000UL)
+#else
+#define OSC_FREQ			(5000000UL)
+#endif
+#else
+#define OSC_FREQ			(24000000UL)
+#endif
+
+#define CLK_FCLK	(HWCLOCK_BASE+0)
+#define CLK_ACLK	(HWCLOCK_BASE+1)
+#define CLK_HCLK	(HWCLOCK_BASE+2)
+#define CLK_PCLK	(HWCLOCK_BASE+3)
+#define CLK_VCLK0	(HWCLOCK_BASE+4)
+#define CLK_VCLK1	(HWCLOCK_BASE+5)
+#define CLK_MCLK	(HWCLOCK_BASE+6)
+#define CLK_NCLK	(HWCLOCK_BASE+7)
+#define CLK_USBPHYCLK	(HWCLOCK_BASE+8)
+#define CLK_NCOREF	(HWCLOCK_BASE+9)
+#define CLK_FMI		(HWCLOCK_BASE+10)
+
+/* S5L8940X clock gate devices */
+enum {
+	CLK_CPU0 = 0,
+	CLK_CPU1,
+	CLK_SCU,
+	CLK_L2RAM0,
+	CLK_L2RAM1,
+	CLK_CPU_REGS,
+	CLK_MCU,
+	CLK_GFX_SYS,
+	CLK_GFX_CORES,
+	CLK_HPERFNRT,
+	CLK_VDEC,
+	CLK_SCALER0,
+	CLK_SCALER1,
+	CLK_JPG,
+	CLK_VENCD,
+	CLK_HPERFRT,
+	CLK_ISP,
+	CLK_resv0,
+	CLK_resv1,
+	CLK_DISP0,
+	CLK_DISP1,
+	CLK_DISPOUT,
+	CLK_MIPI,
+	CLK_CLCD,
+	CLK_TVDAC,
+	CLK_RGBOUT,
+	CLK_DPLINK,
+	CLK_CDIO,
+	CLK_CDMA,
+	CLK_IOP,
+	CLK_UPERF,
+	CLK_USBOTG,
+	CLK_USB20,
+	CLK_USB11,
+	CLK_USBOHCI0,
+	CLK_USBOHCI1,
+	CLK_USBPHY,
+	CLK_AUDIO,
+	CLK_I2S0,
+	CLK_I2S1,
+	CLK_I2S2,
+	CLK_I2S3,
+	CLK_SPDIF,
+	CLK_HPARK,
+	CLK_SDIO,
+	CLK_SHA1,
+	CLK_SHA2,
+	CLK_FMI0,
+	CLK_FMI0BCH,
+	CLK_FMI1,
+	CLK_FMI1BCH,
+	CLK_FMI2,
+	CLK_FMI2BCH,
+	CLK_FMI3,
+	CLK_FMI3BCH,
+	CLK_SPI0,
+	CLK_SPI1,
+	CLK_SPI2,
+	CLK_SPI3,
+	CLK_SPI4,
+	CLK_UART0,
+	CLK_UART1,
+	CLK_UART2,
+	CLK_UART3,
+	CLK_UART4,
+	CLK_UART5,
+	CLK_UART6,
+	CLK_PKE,
+	CLK_I2C0,
+	CLK_I2C1,
+	CLK_I2C2,
+	CLK_PWM,
+	CLK_SCRT,
+	CLK_GPIO,
+	CLK_SWI,
+	CLK_DWI,
+	CLK_DEBUG,
+	CLK_AIC,
+#if SUB_PLATFORM_S5L8947X
+	CLK_MCA0,
+	CLK_ETH,
+	CLK_HDMI,
+	CLK_ADC,
+	CLK_USBOTG1,
+	CLK_USB20_1,
+	CLK_USBOHCI0_1,
+	CLK_USBREG1,
+#endif
+};
+
+#endif /* ! __PLATFORM_SOC_HWCLOCKS_H */

platform/s5l8940x/include/platform/soc/hwdmachannels.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWDMACHANNELS_H
+#define __PLATFORM_SOC_HWDMACHANNELS_H
+
+#include <platform.h>
+
+#include SUB_PLATFORM_HEADER(soc/hwdmachannels)
+
+#define DMA_SDIO_TIMEOUT_US (10 * 1000)
+
+#endif /* ! __PLATFORM_SOC_HWDMACHANNELS_H */

platform/s5l8940x/include/platform/soc/hwdmachannels_s5l8940x.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWDMACHANNELS_S5L8940X_H
+#define __PLATFORM_SOC_HWDMACHANNELS_S5L8940X_H
+
+#define DMA_MEMORY_TX		(1)
+#define DMA_MEMORY_RX		(2)
+#define DMA_SDIO		(3)
+#define DMA_FMI0DATA		(5)
+#define DMA_FMI0CHECK		(6)
+#define DMA_FMI1DATA		(7)
+#define DMA_FMI1CHECK		(8)
+#define DMA_FMI2DATA		(9)
+#define DMA_FMI2CHECK		(10)
+#define DMA_FMI3DATA		(11)
+#define DMA_FMI3CHECK		(12)
+
+#define DMA_CHANNEL_COUNT	(44)
+
+#define DMA_CHANNEL_CONFIG						\
+{									\
+	/*	low	high	AES OK	reqID	FIFO address */		\
+	{	3,	4,	false,	0x00,	0x30000020	},	\
+	{	3,	4,	false,	0x01,	0x301000A0	},	\
+	{	3,	4,	false,	0x01,	0x30200020	},	\
+	{	5,	12,	true,	0x00,	0x31200014	},	\
+	{	5,	12,	true,	0x01,	0x31200018	},	\
+ 	{	5,	12,	true,	0x02,	0x31300014	},	\
+	{	5,	12,	true,	0x03,	0x31300018	},	\
+	{	5,	12,	true,	0x04,	0x31400014	},	\
+	{	5,	12,	true,	0x05,	0x31400018	},	\
+ 	{	5,	12,	true,	0x06,	0x31500014	},	\
+	{	5,	12,	true,	0x07,	0x31500018	},	\
+}
+
+#endif /* ! __PLATFORM_SOC_HWDMACHANNELS_S5L8940X_H */

platform/s5l8940x/include/platform/soc/hwdmachannels_s5l8942x.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWDMACHANNELS_S5L8942X_H
+#define __PLATFORM_SOC_HWDMACHANNELS_S5L8942X_H
+
+#define DMA_MEMORY_TX		(1)
+#define DMA_MEMORY_RX		(2)
+#define DMA_SDIO		(3)
+#define DMA_FMI0DATA		(5)
+#define DMA_FMI0CHECK		(6)
+#define DMA_FMI1DATA		(7)
+#define DMA_FMI1CHECK		(8)
+
+#define DMA_CHANNEL_COUNT	(42)
+
+#define DMA_CHANNEL_CONFIG						\
+{									\
+	/*	low	high	AES OK	reqID	FIFO address */		\
+	{	3,	4,	false,	0x00,	0x30000010	},	\
+	{	3,	4,	false,	0x00,	0x30000020	},	\
+	{	3,	4,	false,	0x01,	0x301000A0	},	\
+	{	3,	4,	false,	0x01,	0x30200020	},	\
+	{	5,	8,	true,	0x00,	0x31200014	},	\
+	{	5,	8,	true,	0x01,	0x31200018	},	\
+ 	{	5,	8,	true,	0x02,	0x31300014	},	\
+	{	5,	8,	true,	0x03,	0x31300018	},	\
+}
+
+#endif /* ! __PLATFORM_SOC_HWDMACHANNELS_S5L8942X_H */

platform/s5l8940x/include/platform/soc/hwdmachannels_s5l8947x.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWDMACHANNELS_S5L8947X_H
+#define __PLATFORM_SOC_HWDMACHANNELS_S5L8947X_H
+
+#define DMA_MEMORY_TX		(1)
+#define DMA_MEMORY_RX		(2)
+#define DMA_FMI0DATA		(5)
+#define DMA_FMI0CHECK		(6)
+#define DMA_FMI1DATA		(7)
+#define DMA_FMI1CHECK		(8)
+
+#define DMA_CHANNEL_COUNT	(42)
+
+#define DMA_CHANNEL_CONFIG						\
+{									\
+	/*	low	high	AES OK	reqID	FIFO address */		\
+	{	3,	4,	false,	0x00,	0x30000010	},	\
+	{	3,	4,	false,	0x00,	0x30000020	},	\
+	{	3,	4,	false,	0x01,	0x301000A0	},	\
+	{	3,	4,	false,	0x01,	0x30200020	},	\
+	{	5,	8,	true,	0x00,	0x31200014	},	\
+	{	5,	8,	true,	0x01,	0x31200018	},	\
+ 	{	5,	8,	true,	0x02,	0x31300014	},	\
+	{	5,	8,	true,	0x03,	0x31300018	},	\
+}
+
+#endif /* ! __PLATFORM_SOC_HWDMACHANNELS_S5L8947X_H */

platform/s5l8940x/include/platform/soc/hwisr.h

@@ -0,0 +1,198 @@
+/*
+ * Copyright (C) 2009-2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWISR_H
+#define __PLATFORM_SOC_HWISR_H
+
+#define INT_SW0			0	// Software 0 Interrupt
+#define INT_SW1			1	// Software 1 Interrupt
+#define INT_SW2			2	// Software 2 Interrupt
+#define INT_SW3			3	// Software 3 Interrupt
+#define INT_WDT			4	// Watchdog Timer Interrupt
+#define INT_SWI			5	// SWI Interrupt
+#define INT_DWI			6	// DWI Interrupt
+#define INT_ISP0		7	// ISP 0 Interrupt
+#define INT_ISP1       		8	// ISP 1 Interrupt
+#define INT_SCALER0		9	// Scaler Interrupt
+#define INT_SCALER1		10	// Scaler Interrupt
+#define INT_USB_OTG		11	// USB OTG Interrupt
+#define INT_USB_EHCI		12	// USB EHCI Interrupt
+#define INT_USB_OHCI0		13	// USB OHCI 0 Interrupt
+#define INT_USB_OHCI1		14	// USB OHCI 1 Interrupt
+#define INT_USB_RES		15	// USB PHY Interrupt
+#define INT_PWM			16	// PWM Interrupt
+#define INT_PKE			17	// PKE Interrupt
+#define INT_IIC0		18	// I2C 0 Interrupt
+#define INT_IIC1		19	// I2C 1 Interrupt
+#define INT_IIC2		20	// I2C 2 Interrupt
+#define INT_UART0		21	// UART 0 Interrupt
+#define INT_UART1		22	// UART 1 Interrupt
+#define INT_UART2		23	// UART 2 Interrupt
+#define INT_UART3		24	// UART 3 Interrupt
+#define INT_UART4 		25	// UART 4 Interrupt
+#define INT_UART5 		26	// UART 5 Interrupt
+#if SUB_PLATFORM_S5L8947X
+#define INT_ETH			27	// Ethernet Interrupt
+#else
+#define INT_UART6		27	// UART 6 Interrupt
+#endif
+#define INT_SPI0 		28	// SPI 0 Interrupt
+#define INT_SPI1		29	// SPI 1 Interrupt
+#define INT_SPI2		30	// SPI 2 Interrupt
+#define INT_SPI3		31	// SPI 3 Interrupt
+#if SUB_PLATFORM_S5L8947X
+#define INT_USB_DEV_RES		32	// USB PHY1 Interrupt
+#else
+#define INT_SPI4		32	// SPI 4 Interrupt
+#endif
+#define INT_FMI0		33	// FMI 0 Interrupt
+#define INT_FMI1		34	// FMI 1 Interrupt
+#if SUB_PLATFORM_S5L8947X
+#define INT_USB_DEV_OTG		35	// USB OTG1 Interrupt
+#define INT_USB_DEV_EHCI	36	// USB EHCI1 Interrupt
+#else
+#define INT_FMI2		35	// FMI 2 Interrupt
+#define INT_FMI3		36	// FMI 3 Interrupt
+#endif
+#define INT_SHA1		37	// SHA-1 Interrupt
+#define INT_SHA2		38	// SHA-1 Interrupt
+#define INT_WIFI		39	// WiFi Interrupt
+#define INT_TVOUT		40	// TV Out Interrupt
+#define INT_MIPI_DSI		41	// MIPI DSI Interrupt	 	
+#define INT_CLCD		42	// CLCD Interrupt
+#define INT_DISP0		43	// Display Pipe 0 Interrupt	
+#define INT_DISP1		44	// Display Pipe 1 Interrupt
+#define INT_RGBOUT		45	// RGB Out Interrupt
+#if SUB_PLATFORM_S5L8947X
+#define INT_HDMI_LINK		46	// HDMI link Interrupt
+#define INT_HDMI_CEC		47	// HDMI cec Interrupt
+#else
+#define INT_DPORT0		46	// DisplayPort 0 Interrupt
+#define INT_DPORT1		47	// DisplayPort 1 Interrupt
+#endif
+#define INT_VENC		48	// Video Encoder Interrupt
+#define INT_SGX			49	// SGX Interrupt
+#define INT_VDEC		50	// Video Decoder Interrupt
+#define INT_CDMA_DMAC1		51	// CDMA DMA Channel 1 Interrupt
+#define INT_CDMA_DMAC2		52	// CDMA DMA Channel 2 Interrupt
+#define INT_CDMA_DMAC3		53	// CDMA DMA Channel 3 Interrupt
+#define INT_CDMA_DMAC4		54	// CDMA DMA Channel 4 Interrupt
+#define INT_CDMA_DMAC5		55	// CDMA DMA Channel 5 Interrupt
+#define INT_CDMA_DMAC6		56	// CDMA DMA Channel 6 Interrupt
+#define INT_CDMA_DMAC7		57	// CDMA DMA Channel 7 Interrupt
+#define INT_CDMA_DMAC8		58	// CDMA DMA Channel 8 Interrupt
+#define INT_CDMA_DMAC9		59	// CDMA DMA Channel 9 Interrupt
+#define INT_CDMA_DMAC10		60	// CDMA DMA Channel 10 Interrupt
+#define INT_CDMA_DMAC11		61	// CDMA DMA Channel 11 Interrupt
+#define INT_CDMA_DMAC12		62	// CDMA DMA Channel 12 Interrupt
+#define INT_CDMA_DMAC13		63	// CDMA DMA Channel 13 Interrupt
+#define INT_CDMA_DMAC14		64	// CDMA DMA Channel 14 Interrupt
+#define INT_CDMA_DMAC15		65	// CDMA DMA Channel 15 Interrupt
+#define INT_CDMA_DMAC16		66	// CDMA DMA Channel 16 Interrupt
+#define INT_CDMA_DMAC17		67	// CDMA DMA Channel 17 Interrupt
+#define INT_CDMA_DMAC18		68	// CDMA DMA Channel 18 Interrupt
+#define INT_CDMA_DMAC19		69	// CDMA DMA Channel 19 Interrupt
+#define INT_CDMA_DMAC20		70	// CDMA DMA Channel 20 Interrupt
+#define INT_CDMA_DMAC21		71	// CDMA DMA Channel 21 Interrupt
+#define INT_CDMA_DMAC22		72	// CDMA DMA Channel 22 Interrupt
+#define INT_CDMA_DMAC23		73	// CDMA DMA Channel 23 Interrupt
+#define INT_CDMA_DMAC24		74	// CDMA DMA Channel 24 Interrupt
+#define INT_CDMA_DMAC25		75	// CDMA DMA Channel 25 Interrupt
+#define INT_CDMA_DMAC26		76	// CDMA DMA Channel 26 Interrupt
+#define INT_CDMA_DMAC27		77	// CDMA DMA Channel 27 Interrupt
+#define INT_CDMA_DMAC28		78	// CDMA DMA Channel 28 Interrupt
+#define INT_CDMA_DMAC29		79	// CDMA DMA Channel 29 Interrupt
+#define INT_CDMA_DMAC30		80	// CDMA DMA Channel 30 Interrupt
+#define INT_CDMA_DMAC31		81	// CDMA DMA Channel 31 Interrupt
+#define INT_CDMA_DMAC32		82	// CDMA DMA Channel 32 Interrupt
+#define INT_CDMA_DMAC33		83	// CDMA DMA Channel 33 Interrupt
+#define INT_CDMA_DMAC34		84	// CDMA DMA Channel 34 Interrupt
+#define INT_CDMA_DMAC35		85	// CDMA DMA Channel 35 Interrupt
+#define INT_CDMA_DMAC36		86	// CDMA DMA Channel 36 Interrupt
+#define INT_CDMA_DMAC37		87	// CDMA DMA Channel 37 Interrupt
+#define INT_CDMA_DMAC38		88	// CDMA DMA Channel 38 Interrupt
+#define INT_CDMA_DMAC39		89	// CDMA DMA Channel 39 Interrupt
+#define INT_CDMA_DMAC40		90	// CDMA DMA Channel 40 Interrupt
+#define INT_CDMA_DMAC41		91	// CDMA DMA Channel 41 Interrupt
+#define INT_CDMA_DMAC42		92	// CDMA DMA Channel 42 Interrupt
+#define INT_CDMA_DMAC43		93	// CDMA DMA Channel 43 Interrupt
+#define INT_CDMA_DMAC44		94	// CDMA DMA Channel 44 Interrupt
+
+// Reserved 95 - 96
+
+// Audio and Highland Park Interrupts 97 - 115
+
+#define INT_AUDIO_CPU_IRQ0	97	// 
+#define INT_AUDIO_CPU_IRQ1	98	// 
+
+#define INT_HPERFNRT_DART	116	// HPerf-NRT DART Interrupt
+#define INT_HPERFRT_DART	117	// HPerf-RT DART Interrupt
+#define INT_JPG			118	// JPEG Interrupt
+#define INT_GPIO0		119	// GPIO 0 Interrupt
+#define INT_GPIO1		120	// GPIO 1 Interrupt
+#define INT_MCU			121	// MCU 0 Interrupt
+#define INT_MCU0		122	// MCU 0 Interrupt
+#define INT_MCU1		123	// MCU 1 Interrupt
+#define INT_PIO0		124	// PIO 0 Interrupt
+#define INT_PIO1		125	// PIO 1 Interrupt
+
+// Reserved 126
+
+#define INT_IOP_COMMRX		127	// IOP CommRx Interrupt
+#define INT_IOP_COMMTX		128	// IOP CommTx Interrupt
+#define INT_IOP_PMI		129	// IOP PerfMon Interrupt
+#define INT_IOP_CTIIRQ		130	// IOP CTIIRQ Interrupt
+#define INT_ISP_COMMRX		131	// IOP CommRx Interrupt
+#define INT_ISP_COMMTX		132	// IOP CommTx Interrupt
+#define INT_ISP_PMI		133	// IOP PerfMon Interrupt
+#define INT_ISP_CTIIRQ		134	// IOP CTIIRQ Interrupt
+
+#define INT_CPU0_PMI		135	// IOP Perfmon Interrupt
+#define INT_CPU0_CTIIRQ		136	// IOP CTI Interrupt
+#define INT_CPU0_COMMRX		137	// IOP CommRx Interrupt
+#define INT_CPU0_COMMTX		138	// IOP CommTx Interrupt
+#define INT_CPU1_PMI		139	// IOP PMI Interrupt
+#define INT_CPU1_CTIIRQ		140	// IOP CTI Interrupt
+#define INT_CPU1_COMMRX		141	// IOP CommRx Interrupt
+#define INT_CPU1_COMMTX		142	// IOP CommTx Interrupt
+
+#define INT_L2C			143	// PL310 Interrupt
+
+// Reserved 144 - 151
+
+#define INT_PMGR_PMI		152	// PMGR PerfMon Interrupt
+#define INT_HPERFNTR_PMI	153	// HPerf-NRT PerfMon Interrupt
+#define INT_HPERFRT_PMI		154	// HPerf-RT PerfMon Interrupt
+#define INT_DPIPE0_PMI		155	// Display Pipe 0 PerfMon Interrupt
+#define INT_DPIPE1_PMI		156	// Display Pipe 1 PerfMon Interrupt
+
+// Reserved 157 - 159
+
+#define INT_ETB_FULL		160	// ETB Full Interrupt
+
+#if PLATFORM_VARIANT_IOP
+
+#include <drivers/aic/aic.h>
+
+#define INT_HOST		INT_SW2			// Host processor doorbell
+#define INT_IOP			INT_SW3			// I/O coprocessor doorbell
+#define INT_IOP_NMI		kAIC_VEC_SW_TMR		// I/O coprocessor NMI
+
+#elif PLATFORM_VARIANT_AUDIO
+
+#include <drivers/audio/audio.h>
+
+#define INT_HOST		AE2_INT_SW0		// Host processor doorbell
+#define INT_IOP			AE2_INT_SW0		// I/O coprocessor doorbell
+#define INT_IOP_NMI		AE2_INT_SW1		// I/O coprocessor NMI
+
+#endif
+
+#endif /* ! __PLATFORM_SOC_HWISR_H */

platform/s5l8940x/include/platform/soc/hwregbase.h

@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2009-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWREGBASE_H
+#define __PLATFORM_SOC_HWREGBASE_H
+
+/* S5L8940X/S5L8942X/S5L8947X Reg Base Defs */
+
+#define AIC_VERSION 			0
+#define AIC_INT_COUNT			(192)
+#define PMGR_WDG_VERSION		0
+
+#if !SUB_PLATFORM_S5L8947X
+#define SDIO_BASE_ADDR			(0x30000000)
+
+#define SHA1_BASE_ADDR			(0x30100000)
+#endif
+
+#define SHA2_BASE_ADDR			(0x30200000)
+
+#define FMI0_BASE_ADDR			(0x31200000)
+#define FMI1_BASE_ADDR			(0x31300000)
+#define FMI2_BASE_ADDR			(0x31400000)
+#define FMI3_BASE_ADDR			(0x31500000)
+#define FMI_VERSION			(3)
+#if !SUB_PLATFORM_S5L8940X
+#define FMI_VERSION_MINOR		(1)
+#endif // SUB_PLATFORM_S5L8942X
+
+#if !SUB_PLATFORM_S5L8947X
+#define SPI0_BASE_ADDR			(0x32000000)
+#define SPI1_BASE_ADDR			(0x32100000)
+#define SPI2_BASE_ADDR			(0x32200000)
+#define SPI3_BASE_ADDR			(0x32300000)
+#define SPI4_BASE_ADDR			(0x32400000)
+#define SPI_VERSION			(1)
+#define SPIS_COUNT			(5)
+#else
+#define SPI0_BASE_ADDR			(0x32000000)
+#define SPI_VERSION			(1)
+#define SPIS_COUNT			(1)
+
+#define ADC_BASE_ADDR			(0x32100000)
+#endif
+
+#define UART_VERSION			(1)
+#define UART0_BASE_ADDR			(0x32500000)
+#define UART1_BASE_ADDR			(0x32600000)
+#define UART2_BASE_ADDR			(0x32700000)
+#define UART3_BASE_ADDR			(0x32800000)
+#define UART4_BASE_ADDR			(0x32900000)
+#if SUB_PLATFORM_S5L8947X
+#define UARTS_COUNT			(5)
+#elif SUB_PLATFORM_S5L8942X
+#define UART5_BASE_ADDR			(0x32A00000)
+#define UARTS_COUNT			(6)
+#elif SUB_PLATFORM_S5L8940X
+#define UART5_BASE_ADDR			(0x32A00000)
+#define UART6_BASE_ADDR			(0x32B00000)
+#define UARTS_COUNT			(7)
+#endif
+
+#define PKE_BASE_ADDR			(0x33100000)
+
+#define IIC_BASE_ADDR			(0x33200000)
+#define IIC_SPACING			(0x00100000)
+#define IICS_COUNT			(3)
+
+#define AUDIO_BASE_ADDR			(0x34000000)
+
+#define USBPHY_BASE_ADDR		(0x36000000)
+#if SUB_PLATFORM_S5L8940X
+#define USBPHY_VERSION			(3)
+#else
+#define USBPHY_VERSION			(4)
+#endif
+
+#define USBOTG_BASE_ADDR		(0x36100000)
+#define UPERF_WIDGETS_BASE_ADDR		(0x36E00000)
+#define UPERF_PL301_BASE_ADDR		(0x36F00000)
+
+#define CDMA_BASE_ADDR			(0x37000000)
+#define CDMA_VERSION			3
+
+#if !SUB_PLATFORM_S5L8947X
+#define VENC_BASE_ADDR			(0x38000000)
+#endif
+
+#define VDEC_BASE_ADDR			(0x38100000)
+
+#define JPEG_BASE_ADDR			(0x38200000)
+
+#define SCALER_BASE_ADDR		(0x38300000)
+#define SCALER_SPACING			(0x00100000)
+
+#define NRT_DART_BASE_ADDR		(0x38B00000)
+#define NRT_DART_WIDGETS_BASE_ADDR	(0x38C00000)
+#define NRT_DART_PL301_BASE_ADDR	(0x38D00000)
+#define NRT_TOP_WIDGETS_BASE_ADDR	(0x38E00000)
+#define NRT_TOP_PL301_BASE_ADDR		(0x38F00000)
+
+#define CLCD_BASE_ADDR			(0x39200000)
+#define CLCD_VERSION			(0)
+#define CLCD_DITHER_BASE_ADDR		(0x39300000)
+#define DITHER_VERSION			(1)
+
+#define TVOUT_BASE_ADDR			(0x39400000)
+
+#if !SUB_PLATFORM_S5L8947X
+#define DSIM_BASE_ADDR			(0x39500000)
+#define DSIM_LANE_COUNT			(4)
+#define DSIM_VERSION			(1)
+#endif
+
+#define RGBOUT_BASE_ADDR		(0x39600000)
+
+#if !SUB_PLATFORM_S5L8947X
+#define DP_BASE_ADDR			(0x39700000)
+#define DISPLAYPORT_VERSION		(1)
+#else
+#define HDMI_BASE_ADDR			(0x39700000)
+#define DPBDITHER_BASE_ADDR		(0x39800000)
+#endif
+
+#if !SUB_PLATFORM_S5L8947X
+#define ISP_BASE_ADDR			(0x3A000000)
+
+#define DISP0_BASE_ADDR			(0x3A100000)
+#define CLCD_DISPLAYPIPE_BASE_ADDR	(DISP0_BASE_ADDR)
+#endif
+#define DISP1_BASE_ADDR			(0x3A200000)
+#define RGBOUT_DISPLAYPIPE_BASE_ADDR	(DISP1_BASE_ADDR)
+#define DISP_VERSION			(3)
+
+#if !SUB_PLATFORM_S5L8947X
+#define RT_DART_BASE_ADDR		(0x3A400000)
+#endif
+#define RT_TOP_WIDGETS_BASE_ADDR	(0x3A500000)
+#define RT_TOP_PL301_BASE_ADDR		(0x3A600000)
+
+#if SUB_PLATFORM_S5L8947X
+#define ETHERNET_BASE_ADDR		(0x3B000000)
+#else
+#define HP_BASE_ADDR			(0x3B000000)
+#endif
+
+#if SUB_PLATFORM_S5L8947X
+#define AMP_BASE_ADDR			(0x3D000000)
+#define AMP_SPACING			(0x00100000)
+#else
+#define AMG_BASE_ADDR			(0x3D000000)
+#define AMG_SPACING			(0x00100000)
+#endif
+
+#define PL310_BASE_ADDR			(0x3E000000)
+#define SCU_BASE_ADDR			(0x3E100000)
+
+#define PMGR_BASE_ADDR			(0x3F100000)
+#define AIC_BASE_ADDR			(0x3F200000)
+
+#define IOP_BASE_ADDR			(0x3F300000)
+
+#define ROSC_BASE_ADDR			(0x3F400000)
+#define ROSC_MASK			(0x57FF)
+#define ROSC_WITH_CLOCK			(0)
+
+#define CHIPID_BASE_ADDR		(0x3F500000)
+
+#define SWI_BASE_ADDR			(0x3F600000)
+#if !SUB_PLATFORM_S5L8947X
+#define DWI_BASE_ADDR			(0x3F700000)
+#endif
+
+#define AMC_BASE_ADDR			(0x3F800000)
+
+#define GPIO_BASE_ADDR			(0x3FA00000)
+#define GPIO_VERSION			(1)
+#if SUB_PLATFORM_S5L8940X
+#define GPIO_GROUP_COUNT		(29)
+#elif SUB_PLATFORM_S5L8942X
+#define GPIO_GROUP_COUNT		(26)
+#elif SUB_PLATFORM_S5L8947X
+#define GPIO_GROUP_COUNT		(18)
+#endif
+#define GPIO_PAD_SPI			(GPIO_GROUP_COUNT)
+
+#define PIO_BASE_ADDR			(0x3FB00000)
+#define PIO_SPACING			(0x00100000)
+
+#define CIF_BASE_ADDR			(0x3FD00000)
+
+#define CDIO_WIDGETS_BASE_ADDR		(0x3FE00000)
+#define CDIO_PL301_BASE_ADDR		(0x3FF00000)
+
+#endif /* ! __PLATFORM_SOC_HWREGBASE_H */

platform/s5l8940x/include/platform/soc/miu.h

@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2009-2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_MIU_H
+#define __PLATFORM_SOC_MIU_H
+
+#include <lib/devicetree.h>
+#include <platform/soc/hwregbase.h>
+
+#define	rREMAP_CTL			(*(volatile u_int32_t *)(PIO_BASE_ADDR + 0x0000))
+
+#define rPL310_CONTROL			(*(volatile u_int32_t *)(PL310_BASE_ADDR + 0x0100))
+#define rPL310_INVAL_WAY		(*(volatile u_int32_t *)(PL310_BASE_ADDR + 0x077C))
+#define rPL310_FILTER_START		(*(volatile u_int32_t *)(PL310_BASE_ADDR + 0x0C00))
+#define rPL310_FILTER_END		(*(volatile u_int32_t *)(PL310_BASE_ADDR + 0x0C04))
+
+#define rSCU_CONTROL			(*(volatile u_int32_t *)(SCU_BASE_ADDR + 0x0000))
+#define rSCU_POWER_STATUS		(*(volatile u_int32_t *)(SCU_BASE_ADDR + 0x0008))
+#define rSCU_TAG_INVAL			(*(volatile u_int32_t *)(SCU_BASE_ADDR + 0x000C))
+
+#define rCIF_CONTROL			(*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0000))
+#define rCIF_CLKGATE			(*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0004))
+#define rCIF_RTLIMIT			(*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0008))
+#define rCIF_WTLIMIT			(*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x000C))
+#define rCIF_IDLETMR			(*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0010))
+#define rCIF_RDREMAP			(*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0040))
+#define rCIF_WRREMAP			(*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0044))
+
+#define  CDIO_IOP_RTLIMIT		(0x0008)
+#define rCDIO_IOP_RTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_RTLIMIT))
+#define  CDIO_IOP_WTLIMIT		(0x000C)
+#define rCDIO_IOP_WTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_WTLIMIT))
+#define  CDIO_IOP_WREQSP		(0x001C)
+#define rCDIO_IOP_WREQSP		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_WREQSP))
+#define  CDIO_CDMA_RTLIMIT		(0x0028)
+#define rCDIO_CDMA_RTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_CDMA_RTLIMIT))
+#define  CDIO_CDMA_WTLIMIT		(0x002C)
+#define rCDIO_CDMA_WTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_CDMA_WTLIMIT))
+#define  CDIO_CDMA_WGATHER		(0x0030)
+#define rCDIO_CDMA_WGATHER		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_CDMA_WGATHER))
+#define  CDIO_UPERF_RTLIMIT		(0x0048)
+#define rCDIO_UPERF_RTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPERF_RTLIMIT))
+#define  CDIO_UPERF_WTLIMIT		(0x004C)
+#define rCDIO_UPERF_WTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPERF_WTLIMIT))
+#define  CDIO_UPERF_WGATHER		(0x0050)
+#define rCDIO_UPERF_WGATHER		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPERF_WGATHER))
+#define  CDIO_AUDIO_RTLIMIT		(0x0068)
+#define rCDIO_AUDIO_RTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_AUDIO_RTLIMIT))
+#define  CDIO_AUDIO_WTLIMIT		(0x006C)
+#define rCDIO_AUDIO_WTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_AUDIO_WTLIMIT))
+#define  CDIO_AUDIO_WGATHER		(0x0070)
+#define rCDIO_AUDIO_WGATHER		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_AUDIO_WGATHER))
+#define  CDIO_PIO_RTLIMIT		(0x00A8)
+#define rCDIO_PIO_RTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_PIO_RTLIMIT))
+#define  CDIO_PIO_WTLIMIT		(0x00AC)
+#define rCDIO_PIO_WTLIMIT		(*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_PIO_WTLIMIT))
+
+#define  CDIO_AR_CHAN_ARB_MI0		(0x0408)
+#define rCDIO_AR_CHAN_ARB_MI0		(*(volatile u_int32_t *)(CDIO_PL301_BASE_ADDR + CDIO_AR_CHAN_ARB_MI0))
+#define  CDIO_AW_CHAN_ARB_MI0		(0x040C)
+#define rCDIO_AW_CHAN_ARB_MI0		(*(volatile u_int32_t *)(CDIO_PL301_BASE_ADDR + CDIO_AW_CHAN_ARB_MI0))
+#define  CDIO_AR_CHAN_ARB_MI1		(0x0428)
+#define rCDIO_AR_CHAN_ARB_MI1		(*(volatile u_int32_t *)(CDIO_PL301_BASE_ADDR + CDIO_AR_CHAN_ARB_MI1))
+#define  CDIO_AW_CHAN_ARB_MI1		(0x042C)
+#define rCDIO_AW_CHAN_ARB_MI1		(*(volatile u_int32_t *)(CDIO_PL301_BASE_ADDR + CDIO_AW_CHAN_ARB_MI1))
+
+#define  UPERF_OTG_QOS			(0x0014)
+#define rUPERF_OTG_QOS			(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OTG_QOS))
+#define  UPERF_OTG_CACHE		(0x0018)
+#define rUPERF_OTG_CACHE		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OTG_CACHE))
+#define  UPERF_EHCI_QOS			(0x0034)
+#define rUPERF_EHCI_QOS			(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_EHCI_QOS))
+#define  UPERF_EHCI_CACHE		(0x0038)
+#define rUPERF_EHCI_CACHE		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_EHCI_CACHE))
+#define  UPERF_OHCI0_QOS		(0x0054)
+#define rUPERF_OHCI0_QOS		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OHCI0_QOS))
+#define  UPERF_OHCI0_CACHE		(0x0058)
+#define rUPERF_OHCI0_CACHE		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OHCI0_CACHE))
+#define  UPERF_OHCI1_QOS		(0x0074)
+#define rUPERF_OHCI1_QOS		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OHCI1_QOS))
+#define  UPERF_OHCI1_CACHE		(0x0078)
+#define rUPERF_OHCI1_CACHE		(*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OHCI1_CACHE))
+
+#define  HPERF_NRT_DART_DART_RTLIMIT	(0x0004)
+#define rHPERF_NRT_DART_DART_RTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_DART_RTLIMIT))
+#define  HPERF_NRT_DART_DART_WTLIMIT	(0x0008)
+#define rHPERF_NRT_DART_DART_WTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_DART_WTLIMIT))
+#define  HPERF_NRT_DART_JPEG0_QOS	(0x000C)
+#define rHPERF_NRT_DART_JPEG0_QOS	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_JPEG0_QOS))
+#define  HPERF_NRT_DART_JPEG1_QOS	(0x0010)
+#define rHPERF_NRT_DART_JPEG1_QOS	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_JPEG1_QOS))
+#define  HPERF_NRT_DART_SCALER0_RTLIMIT	(0x001C)
+#define rHPERF_NRT_DART_SCALER0_RTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_SCALER0_RTLIMIT))
+#define  HPERF_NRT_DART_SCALER0_WTLIMIT	(0x0020)
+#define rHPERF_NRT_DART_SCALER0_WTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_SCALER0_WTLIMIT))
+#define  HPERF_NRT_DART_SCALER1_RTLIMIT	(0x0030)
+#define rHPERF_NRT_DART_SCALER1_RTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_SCALER1_RTLIMIT))
+#define  HPERF_NRT_DART_SCALER1_WTLIMIT	(0x0034)
+#define rHPERF_NRT_DART_SCALER1_WTLIMIT	(*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_SCALER1_WTLIMIT))
+
+#define  HPERF_NRT_DART_AR_CHAN_ARB_MI	(0x0408)
+#define rHPERF_NRT_DART_AR_CHAN_ARB_MI	(*(volatile u_int32_t *)(NRT_DART_PL301_BASE_ADDR + HPERF_NRT_DART_AR_CHAN_ARB_MI0))
+#define  HPERF_NRT_DART_AW_CHAN_ARB_MI	(0x040C)
+#define rHPERF_NRT_DART_AW_CHAN_ARB_MI	(*(volatile u_int32_t *)(NRT_DART_PL301_BASE_ADDR + HPERF_NRT_DART_AW_CHAN_ARB_MI0))
+
+#define  HPERF_NRT_TOP_TOP_RTLIMIT	(0x0000)
+#define rHPERF_NRT_TOP_TOP_RTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_TOP_RTLIMIT))
+#define  HPERF_NRT_TOP_TOP_WTLIMIT	(0x0004)
+#define rHPERF_NRT_TOP_TOP_WTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_TOP_WTLIMIT))
+#define  HPERF_NRT_TOP_VENC_RTLIMIT	(0x0010)
+#define rHPERF_NRT_TOP_VENC_RTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VENC_RTLIMIT))
+#define  HPERF_NRT_TOP_VENC_WTLIMIT	(0x0014)
+#define rHPERF_NRT_TOP_VENC_WTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VENC_WTLIMIT))
+#define  HPERF_NRT_TOP_VENC_WREQSP	(0x0018)
+#define rHPERF_NRT_TOP_VENC_WREQSP	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VENC_WREQSP))
+#define  HPERF_NRT_TOP_VDEC_RTLIMIT	(0x0028)
+#define rHPERF_NRT_TOP_VDEC_RTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VDEC_RTLIMIT))
+#define  HPERF_NRT_TOP_VDEC_WTLIMIT	(0x002C)
+#define rHPERF_NRT_TOP_VDEC_WTLIMIT	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VDEC_WTLIMIT))
+#define  HPERF_NRT_TOP_VDEC_WREQSP	(0x0030)
+#define rHPERF_NRT_TOP_VDEC_WREQSP	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VDEC_WREQSP))
+#define  HPERF_NRT_TOP_DART_WGATHER	(0x0048)
+#define rHPERF_NRT_TOP_DART_WGATHER	(*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_DART_WGATHER))
+
+#define  HPERF_NRT_TOP_AR_CHAN_ARB_MI	(0x0408)
+#define rHPERF_NRT_TOP_AR_CHAN_ARB_MI	(*(volatile u_int32_t *)(NRT_TOP_PL301_BASE_ADDR + HPERF_NRT_TOP_AR_CHAN_ARB_MI0))
+#define  HPERF_NRT_TOP_AW_CHAN_ARB_MI	(0x040C)
+#define rHPERF_NRT_TOP_AW_CHAN_ARB_MI	(*(volatile u_int32_t *)(NRT_TOP_PL301_BASE_ADDR + HPERF_NRT_TOP_AW_CHAN_ARB_MI0))
+
+#define  HPERF_RT_TOP_DISP0_RTLIMIT	(0x0004)
+#define rHPERF_RT_TOP_DISP0_RTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_DISP0_RTLIMIT))
+#define  HPERF_RT_TOP_DISP1_RTLIMIT	(0x000C)
+#define rHPERF_RT_TOP_DISP1_RTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_DISP1_RTLIMIT))
+#define  HPERF_RT_TOP_ISP_RTLIMIT	(0x0018)
+#define rHPERF_RT_TOP_ISP_RTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_ISP_WTLIMIT))
+#define  HPERF_RT_TOP_ISP_WTLIMIT	(0x001C)
+#define rHPERF_RT_TOP_ISP_WTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_ISP_RTLIMIT))
+#define  HPERF_RT_TOP_TOP_RTLIMIT	(0x0020)
+#define rHPERF_RT_TOP_TOP_RTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_TOP_WTLIMIT))
+#define  HPERF_RT_TOP_TOP_WTLIMIT	(0x0024)
+#define rHPERF_RT_TOP_TOP_WTLIMIT	(*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_TOP_RTLIMIT))
+
+#define  HPERF_RT_TOP_AR_CHAN_ARB_MI	(0x0408)
+#define rHPERF_RT_TOP_AR_CHAN_ARB_MI	(*(volatile u_int32_t *)(RT_TOP_PL301_BASE_ADDR + HPERF_RT_TOP_AR_CHAN_ARB_MI0))
+#define  HPERF_RT_TOP_AW_CHAN_ARB_MI	(0x040C)
+#define rHPERF_RT_TOP_AW_CHAN_ARB_MI	(*(volatile u_int32_t *)(RT_TOP_PL301_BASE_ADDR + HPERF_RT_TOP_AW_CHAN_ARB_MI0))
+
+
+enum remap_select {
+  REMAP_SRAM = 0,
+  REMAP_SDRAM
+};
+
+extern void miu_select_remap(enum remap_select sel);
+extern void miu_bypass_prep(void);
+extern void miu_update_device_tree(DTNode *pmgr_node);
+
+#endif /* ! __PLATFORM_SOC_MIU_H */

platform/s5l8940x/include/platform/soc/pmgr.h

@@ -0,0 +1,465 @@
+/*
+ * Copyright (C) 2009-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_PMGR_H
+#define __PLATFORM_SOC_PMGR_H
+
+#include <lib/devicetree.h>
+#include <platform/soc/hwregbase.h>
+
+#define	rPMGR_PLL0_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0000))
+#define	rPMGR_PLL0_PARAM		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0004))
+#define	rPMGR_PLL1_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0008))
+#define	rPMGR_PLL1_PARAM		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x000C))
+#define	rPMGR_PLL2_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0010))
+#define	rPMGR_PLL2_PARAM		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0014))
+#define	rPMGR_PLL3_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0018))
+#define	rPMGR_PLL3_PARAM		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x001C))
+#define	rPMGR_PLL4_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0020))
+#define	rPMGR_PLL4_PARAM		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0024))
+#define	rPMGR_PLLUSB_CTL		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0028))
+#define	rPMGR_PLLUSB_PARAM		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x002C))
+
+#define	rPMGR_PLL_ENABLE			(1 << 31)
+#define	rPMGR_PLL_EXT_BYPASS			(1 << 30)
+#define	rPMGR_PLL_REAL_LOCK			(1 << 29)
+#define	rPMGR_PLL_LOAD				(1 << 27)
+#define	rPMGR_PLL_BYPASS			(1 << 23)
+#define	rPMGR_PLL_P(_p)				(((_p) & 0x03f) << 14)
+#if (SUB_PLATFORM_S5L8942X || SUB_PLATFORM_S5L8947X)
+#define rPMGR_PLL_VSEL(_p)			(((_p) & 1) << 13)
+#endif
+#define	rPMGR_PLL_M(_m)				(((_m) & 0x3ff) <<  3)
+#define	rPMGR_PLL_S(_s)				(((_s) & 0x007) <<  0)
+
+#define rPMGR_PARAM_EXT_AFC(_n)			((_n) << 17)
+#define rPMGR_PARAM_AFC_EN			(1 << 16)
+#define rPMGR_PARAM_LOCK_TIME(_n)		((_n) << 0)
+
+#define	rPMGR_PLL_GATES			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0030))
+
+#define	rPMGR_DOUBLER_CTL		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0034))
+
+#define	rPMGR_DOUBLER_ENABLE			(1 << 31)
+#define	rPMGR_DOUBLER_EXT_BYPASS		(1 << 30)
+
+#define	rPMGR_CPU_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0038))
+#define	rPMGR_MCU_FIXED_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x003C))
+#define	rPMGR_MCU_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0040))
+#define	rPMGR_PCLK1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0044))
+
+#define	rPMGR_PREDIV0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0048))
+#define	rPMGR_PREDIV1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x004C))
+#define	rPMGR_PREDIV2_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0050))
+#define	rPMGR_PREDIV3_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0054))
+#define	rPMGR_PREDIV4_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0058))
+#define	rPMGR_PREDIV5_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x005C))
+#define	rPMGR_PREDIV6_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0060))
+
+#define	rPMGR_MANAGED0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0064))
+#define	rPMGR_MANAGED1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0068))
+#define	rPMGR_MANAGED2_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x006C))
+#define	rPMGR_MANAGED3_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0070))
+#define	rPMGR_MANAGED4_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0074))
+
+#define	rPMGR_VID1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0078))
+#define	rPMGR_MEDIUM0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x007C))
+#define	rPMGR_VID0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0080))
+#define	rPMGR_I2C_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0084))
+#define	rPMGR_SDIO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0088))
+#define	rPMGR_MIPI_DSI_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x008C))
+#define	rPMGR_AUDIO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0090))
+#define	rPMGR_HPARK_PCLK0_CLK_CFG	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0094))
+#define	rPMGR_HPARK_TCLK_CLK_CFG	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0098))
+#define	rPMGR_UPERF_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x009C))
+#define	rPMGR_DEBUG_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00A0))
+
+#define	rPMGR_HPERFRT_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00A4))
+#define	rPMGR_GFX_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00A8))
+#define	rPMGR_GFX_SLC_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00AC))
+
+#define	rPMGR_HPERFNRT_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00B0))
+#define	rPMGR_ISP_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00B4))
+#define	rPMGR_IOP_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00B8))
+#define	rPMGR_CDIO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00BC))
+
+#define	rPMGR_LPERFS_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00C0))
+#define	rPMGR_PCLK0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00C4))
+#define	rPMGR_PCLK2_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00C8))
+#define	rPMGR_PCLK3_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00CC))
+
+#define	rPMGR_MEDIUM1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00D0))
+#define	rPMGR_SPI0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00D4))
+#define	rPMGR_SPI1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00D8))
+#define	rPMGR_SPI2_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00DC))
+#define	rPMGR_SPI3_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00E0))
+#define	rPMGR_SPI4_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00E4))
+#define	rPMGR_SLEEP_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00E8))
+#define	rPMGR_USBPHY_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00EC))
+#define	rPMGR_USBOHCI_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00F0))
+#define	rPMGR_USB12_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00F4))
+#define	rPMGR_NCO_REF0_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00F8))
+#define	rPMGR_NCO_REF1_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00FC))
+#define	rPMGR_VENC_MTX_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0100))
+#define	rPMGR_VENC_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0104))
+
+#define	PMGR_FIRST_CLK_CFG		(&rPMGR_CPU_CLK_CFG)
+#define	PMGR_LAST_CLK_CFG		(&rPMGR_VENC_CLK_CFG)
+#define	PMGR_CLK_CFG_COUNT		(((((u_int32_t)(PMGR_LAST_CLK_CFG)) - ((u_int32_t)(PMGR_FIRST_CLK_CFG))) / 4) + 1)
+#define	PMGR_CLK_NUM(_r)		(((u_int32_t)&(rPMGR_ ## _r ## _CLK_CFG) - ((u_int32_t)(PMGR_FIRST_CLK_CFG))) / 4)
+
+#define	rPMGR_I2S0_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0110))
+#define	rPMGR_I2S0_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0114))
+#define	rPMGR_I2S0_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0118))
+
+#define	rPMGR_I2S1_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0120))
+#define	rPMGR_I2S1_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0124))
+#define	rPMGR_I2S1_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0128))
+
+#define	rPMGR_I2S2_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0130))
+#define	rPMGR_I2S2_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0134))
+#define	rPMGR_I2S2_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0138))
+
+#define	rPMGR_I2S3_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0140))
+#define	rPMGR_I2S3_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0144))
+#define	rPMGR_I2S3_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0148))
+
+#define	rPMGR_SPDIF_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0150))
+#define	rPMGR_SPDIF_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0154))
+#define	rPMGR_SPDIF_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0158))
+
+#define	rPMGR_DP_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0160))
+#define	rPMGR_DP_NCO_N1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0164))
+#define	rPMGR_DP_NCO_N2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0168))
+
+#define	rPMGR_MCA0_NCO_CLK_CFG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0170))
+#define	rPMGR_MCA0_NCO_N1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0174))
+#define	rPMGR_MCA0_NCO_N2		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0178))
+
+#define	rPMGR_CLK_CFG_ENABLE			(1 << 31)
+#define	rPMGR_CLK_CFG_PENDING			(1 << 30)
+#define	rPMGR_CLK_CFG_SRC_SEL(_s)		(((_s) & 0x3) << 28)
+#define	rPMGR_CLK_CFG_SRC_SEL_MASK		rPMGR_CLK_CFG_SRC_SEL(3)
+#define	rPMGR_CLK_CFG_DIVIDER(_d)		(((_d) & 0x1f) << 0)
+#define	rPMGR_CLK_CFG_DIV_MASK			rPMGR_CLK_CFG_DIVIDER(0x1f)
+
+#define	PMGR_PERF_STATE_COUNT		(16)
+#define	rPMGR_PERF_STATE_A(_s)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0200 + ((_s) * 0x10)))
+#define	rPMGR_PERF_STATE_B(_s)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0204 + ((_s) * 0x10)))
+#define	rPMGR_PERF_STATE_C(_s)		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0208 + ((_s) * 0x10)))
+#define	rPMGR_PERF_STATE_CTL		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0300))
+
+#define	PMGR_PERF_STATE_SEL(_s)			(((_s) & 0xF) << 0)
+#define	PMGR_PERF_STATE_PENDING			(0xFF << 16)
+
+#define	kPERF_STATE_BYPASS			(0)
+#define	kPERF_STATE_SECUREROM			(1)
+#define	kPERF_STATE_IBOOT			(2)
+#define	kPERF_STATE_IBOOT_CNT			(5)
+
+#define	rPMGR_MCU_CLK_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0400))
+
+#define	rPMGR_CPU0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1008))
+#define	rPMGR_CPU1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x100C))
+#define	rPMGR_SCU_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1010))
+#define	rPMGR_L2RAM0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1014))
+#define	rPMGR_L2RAM1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1018))
+#define	rPMGR_CPU_REGS_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x101C))
+#define	rPMGR_MCU_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1020))
+#define	rPMGR_GFX_SYS_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1024))
+#define	rPMGR_GFX_CORES_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1028))
+#define	rPMGR_HPERFNRT_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x102C))
+#define	rPMGR_VDEC_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1030))
+#define	rPMGR_SCALER0_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1034))
+#define	rPMGR_SCALER1_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1038))
+#define	rPMGR_JPG_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x103C))
+#define	rPMGR_VENCD_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1040))
+#define	rPMGR_HPERFRT_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1044))
+#define	rPMGR_ISP_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1048))
+#define	rPMGR_DISP0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1054))
+#define	rPMGR_DISP1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1058))
+#define	rPMGR_DISPOUT_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x105C))
+#define	rPMGR_MIPI_DSI_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1060))
+#define	rPMGR_CLCD_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1064))
+#define	rPMGR_TVOUT_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1068))
+#define	rPMGR_RGBOUT_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x106C))
+#define	rPMGR_DPLINK_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1070))
+#define	rPMGR_CDIO_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1074))
+#define	rPMGR_CDMA_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1078))
+#define	rPMGR_IOP_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x107C))
+#define	rPMGR_UPERF_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1080))
+#define	rPMGR_USBOTG0_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1084))
+#define	rPMGR_USB20_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1088))
+#define	rPMGR_USB11_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x108C))
+#define	rPMGR_USBOHCI0_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1090))
+#define	rPMGR_USBOHCI1_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1094))
+#define	rPMGR_USBREG_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1098))
+#define	rPMGR_AUDIO_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x109C))
+#define	rPMGR_I2S0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10A0))
+#define	rPMGR_I2S1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10A4))
+#define	rPMGR_I2S2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10A8))
+#define	rPMGR_I2S3_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10AC))
+#define	rPMGR_SPDIF_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10B0))
+#define	rPMGR_HPARK_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10B4))
+#define	rPMGR_SDIO_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10B8))
+#define	rPMGR_SHA1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10BC))
+#define	rPMGR_SHA2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10C0))
+#define	rPMGR_FMI0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10C4))
+#define	rPMGR_FMI0BCH_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10C8))
+#define	rPMGR_FMI1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10CC))
+#define	rPMGR_FMI1BCH_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10D0))
+#define	rPMGR_FMI2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10D4))
+#define	rPMGR_FMI2BCH_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10D8))
+#define	rPMGR_FMI3_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10DC))
+#define	rPMGR_FMI3BCH_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10E0))
+#define	rPMGR_SPI0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10E4))
+#define	rPMGR_SPI1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10E8))
+#define	rPMGR_SPI2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10EC))
+#define	rPMGR_SPI3_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10F0))
+#define	rPMGR_SPI4_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10F4))
+#define	rPMGR_UART0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10F8))
+#define	rPMGR_UART1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10FC))
+#define	rPMGR_UART2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1100))
+#define	rPMGR_UART3_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1104))
+#define	rPMGR_UART4_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1108))
+#define	rPMGR_UART5_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x110C))
+#define	rPMGR_UART6_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1110))
+#define	rPMGR_PKE_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1114))
+#define	rPMGR_I2C0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1118))
+#define	rPMGR_I2C1_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x111C))
+#define	rPMGR_I2C2_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1120))
+#define	rPMGR_PWM_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1124))
+#define	rPMGR_SCRT_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1128))
+#define	rPMGR_GPIO_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x112C))
+#define	rPMGR_SWI_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1130))
+#define	rPMGR_DWI_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1134))
+#define	rPMGR_DEBUG_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1138))
+#define	rPMGR_AIC_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x113C))
+#define	rPMGR_MCA0_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1140))
+#ifdef SUB_PLATFORM_S5L8947X
+#define	rPMGR_ETH_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1144))
+#define	rPMGR_HDMI_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1148))
+#define	rPMGR_ADC_PS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x114C))
+#define	rPMGR_USBOTG1_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1150))
+#define	rPMGR_USB20_1_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1154))
+#define	rPMGR_USBOHCI0_1_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1158))
+#define	rPMGR_USBREG1_PS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x115C))
+#endif
+#define rPMGR_PS_RESET				(1 << 31)
+
+#define	PMGR_FIRST_PS			(&rPMGR_CPU0_PS)
+#if SUB_PLATFORM_S5L8942X
+#define	PMGR_LAST_PS			(&rPMGR_MCA0_PS)
+#elif SUB_PLATFORM_S5L8947X
+#define	PMGR_LAST_PS			(&rPMGR_USBREG1_PS)
+#else
+#define	PMGR_LAST_PS			(&rPMGR_AIC_PS)
+#endif
+#define	PMGR_DEV_PS_COUNT		(((((u_int32_t)(PMGR_LAST_PS)) - ((u_int32_t)(PMGR_FIRST_PS))) / 4) + 1)
+#define	PMGR_PS_NUM(_r)			(((u_int32_t)&(rPMGR_ ## _r ## _PS) - ((u_int32_t)(PMGR_FIRST_PS))) / 4)
+
+#define	rPMGR_CPU_CFG			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1180))
+
+#define	rPMGR_PWR_GATE_CTL_SET		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1200))
+#define	rPMGR_PWR_GATE_CTL_CLR		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1204))
+#define	rPMGR_PWR_GATE_IOP			(1 << 6)
+#define	rPMGR_PWR_GATE_GFX_MODE		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1208))
+
+#define	rPMGR_CORE_OFFLINE_SET		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1210))
+#define	rPMGR_CORE_OFFLINE_CLR		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1214))
+#define	rPMGR_WAKE_CORES		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1220))
+
+#define	PMGR_PWR_GATE_TIME_COUNT	(15)
+#define	rPMGR_PWR_GATE_TIME_A(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1238 + ((_n) * 8)))
+#define	rPMGR_PWR_GATE_TIME_B(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x123C + ((_n) * 8)))
+#define	rPMGR_PWR_GATE_DBG0		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x12E0))
+#define	rPMGR_PWR_GATE_DBG1		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x12E4))
+
+#define	rPMGR_TEST_CLK			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2000))
+#define	rPMGR_PLL0_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2010))
+#define	rPMGR_PLL1_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2014))
+#define	rPMGR_PLL2_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2018))
+#define	rPMGR_PLL3_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x201C))
+#define	rPMGR_PLL4_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2020))
+#define	rPMGR_PLLUSB_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2024))
+#define	rPMGR_DOUBLER_DEBUG		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2028))
+
+#define	rPMGR_PLL0_TUNE			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2080))
+#define	rPMGR_PLL1_TUNE			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2084))
+#define	rPMGR_PLL2_TUNE			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2088))
+#define	rPMGR_PLL3_TUNE			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x208C))
+#define	rPMGR_PLL4_TUNE			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2090))
+#define	rPMGR_PLLUSB_TUNE		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2094))
+
+#define rPMGR_PLL_DEBUG_ENABLED			(1 << 31)
+#define rPMGR_PLL_DEBUG_BYP_ENABLED		(1 << 30)
+#define rPMGR_PLL_DEBUG_DBG_STPCLK_EN		(1 << 24)
+#define rPMGR_PLL_DEBUG_LOST_LOCK		(1 << 16)
+#define rPMGR_PLL_DEBUG_STATE(_r)		(((_r) >> 0) & 0xff)
+
+#define rPMGR_EMA_CTL_CPU		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2100))
+#define rPMGR_EMA_CTL_CPU_SPIN			(0x01 << 16)
+#define rPMGR_EMA_CTL_SOC		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2104))
+#define rPMGR_EMA_CTL_SOC_SEL			(0x1f << 0)
+#define rPMGR_EMA_CTL_SOC_SPIN			(0x01 << 16)
+
+#define	rPMGR_SRAM_EMA_B0_Pn_LO(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2120 + ((_n) * 8)))
+#define	rPMGR_SRAM_EMA_B0_Pn_HI(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2124 + ((_n) * 8)))
+#define	rPMGR_SRAM_EMA_B1_Pn_LO(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x21C0 + ((_n) * 8)))
+#define	rPMGR_SRAM_EMA_B1_Pn_HI(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x21C4 + ((_n) * 8)))
+#if (SUB_PLATFORM_S5L8942X || SUB_PLATFORM_S5L8947X)
+#define	rPMGR_SRAM_EMA_B2_Pn_LO(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2200 + ((_n) * 8)))
+#define	rPMGR_SRAM_EMA_B2_Pn_HI(_n)	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2204 + ((_n) * 8)))
+#endif
+
+enum {
+  EMA_CPU = 0,
+  EMA_MCU = 1,
+  EMA_GFX_PIPES_SYS = 2,
+  EMA_GFX_HYDRA = 3,
+  EMA_VDEC = 4,
+  EMA_VENC = 5,
+  EMA_ISP = 6,
+  EMA_DISP = 7,
+  EMA_NRT = 8,
+  EMA_CIF = 9,
+  EMA_IOP = 10,
+  EMA_SAUDIO = 11,
+  EMA_CDMA = 12,
+  EMA_FMI = 13,
+  EMA_HPARK = 14,
+};
+
+#define	rPMGR_WDOG_TMR			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3020))
+#define	rPMGR_WDOG_RST			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3024))
+#define	rPMGR_WDOG_INT			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3028))
+#define	rPMGR_WDOG_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x302C))
+
+#define	rPMGR_EVENT_TMR			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3100))
+#define	rPMGR_EVENT_PERIOD		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3104))
+#define	rPMGR_EVENT_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3108))
+
+#define	rPMGR_PERF_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4000))
+#define	rPMGR_PERF_STATUS		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4004))
+#define	rPMGR_PERF_CTR0_LO		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4020))
+#define	rPMGR_PERF_CTR0_HI		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4024))
+#define	rPMGR_PERF_CFG0_LO		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4028))
+#define	rPMGR_PERF_CFG0_MID		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x402C))
+#define	rPMGR_PERF_CFG0_HI		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4030))
+#define	rPMGR_PERF_CTR1_LO		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4040))
+#define	rPMGR_PERF_CTR1_HI		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4044))
+#define	rPMGR_PERF_CFG1_LO		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4048))
+#define	rPMGR_PERF_CFG1_MID		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x404C))
+#define	rPMGR_PERF_CFG1_HI		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4050))
+
+#define	rPMGR_SCRATCH0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6000))
+#define	rPMGR_SCRATCH1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6004))
+#define	rPMGR_SCRATCH2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6008))
+#define	rPMGR_SCRATCH3			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x600C))
+#define	rPMGR_SCRATCH4			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6010))
+#define	rPMGR_SCRATCH5			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6014))
+#define	rPMGR_SCRATCH6			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6018))
+#define	rPMGR_SCRATCH7			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x601C))
+#define	rPMGR_SCRATCH8			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6020))
+#define	rPMGR_SCRATCH9			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6024))
+#define	rPMGR_SCRATCH10			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6028))
+#define	rPMGR_SCRATCH11			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x602C))
+#define	rPMGR_SCRATCH12			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6030))
+#define	rPMGR_SCRATCH13			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6034))
+#define	rPMGR_SCRATCH14			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6038))
+#define	rPMGR_SCRATCH15			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x603C))
+
+#define	rPMGR_DAC_FS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x7000))
+
+#define	rPMGR_USB_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x8000))
+
+#define	rPMGR_SHA_SEL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x9000))
+
+#define	rPMGR_SECURITY			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xA000))
+
+#define	rPMGR_GFX_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xB000))
+
+#define PGMR_GET_PERF_STATE_INDEX(_n, _x)	(((_x) >> ((_n) * 4)) & 0xF)
+#define PGMR_SET_PERF_STATE_INDEX(_n, _i)	(((_i) & 0xF) << ((_n) * 4))
+#define PMGR_PERF_STATE_V(_n)			(_n)
+#define PMGR_PERF_STATE_P			(3)
+#define PMGR_PERF_STATE_M(_n)			(4 + (_n))
+
+enum {
+	PMGR_CLK_OSC = 0,
+	PMGR_CLK_PLL0,
+	PMGR_CLK_PLL1,
+	PMGR_CLK_PLL2,
+	PMGR_CLK_PLL3,
+	PMGR_CLK_PLL4,
+	PMGR_CLK_PLLUSB,
+	PMGR_CLK_DOUBLER,
+	PMGR_CLK_CPU,
+	PMGR_CLK_MEM,
+	PMGR_CLK_PIO,
+	PMGR_CLK_ACP,
+	PMGR_CLK_MCU_FIXED,
+	PMGR_CLK_MCU,
+	PMGR_CLK_PREDIV0,
+	PMGR_CLK_PREDIV1,
+	PMGR_CLK_PREDIV2,
+	PMGR_CLK_PREDIV3,
+	PMGR_CLK_PREDIV4,
+	PMGR_CLK_PREDIV5,
+	PMGR_CLK_PREDIV6,
+	PMGR_CLK_MANAGED0,
+	PMGR_CLK_MANAGED1,
+	PMGR_CLK_MANAGED2,
+	PMGR_CLK_MANAGED3,
+	PMGR_CLK_MANAGED4,
+	PMGR_CLK_MEDIUM0,
+	PMGR_CLK_MEDIUM1,
+	PMGR_CLK_VID0,
+	PMGR_CLK_VID1,
+	PMGR_CLK_I2C,
+	PMGR_CLK_SDIO,
+	PMGR_CLK_MIPI_DSI,
+	PMGR_CLK_AUDIO,
+	PMGR_CLK_HPARK_PCLK,
+	PMGR_CLK_HPARK_TCLK,
+	PMGR_CLK_UPERF,
+	PMGR_CLK_DEBUG,
+	PMGR_CLK_HPERFRT,
+	PMGR_CLK_GFX,
+	PMGR_CLK_GFX_SLC,
+	PMGR_CLK_HPERFNRT,
+	PMGR_CLK_ISP,
+	PMGR_CLK_IOP,
+	PMGR_CLK_CDIO,
+	PMGR_CLK_LPERFS,
+	PMGR_CLK_PCLK0,
+	PMGR_CLK_PCLK1,
+	PMGR_CLK_PCLK2,
+	PMGR_CLK_PCLK3,
+	PMGR_CLK_SPI0,
+	PMGR_CLK_SPI1,
+	PMGR_CLK_SPI2,
+	PMGR_CLK_SPI3,
+	PMGR_CLK_SPI4,
+	PMGR_CLK_SLOW,
+	PMGR_CLK_SLEEP,
+	PMGR_CLK_USBPHY,
+	PMGR_CLK_USBOHCI,
+	PMGR_CLK_USB12,
+	PMGR_CLK_NCO_REF0,
+	PMGR_CLK_NCO_REF1,
+	PMGR_CLK_VENC_MTX,
+	PMGR_CLK_VENC,
+	PMGR_CLK_COUNT
+};
+
+extern void pmgr_update_device_tree(DTNode *pmgr_node);
+
+#endif /* ! __PLATFORM_SOC_PMGR_H */

platform/s5l8940x/include/platform/trampoline.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_TRAMPOLINE_H
+#define __PLATFORM_TRAMPOLINE_H
+
+#include <platform/memmap.h>
+#include <platform/soc/hwregbase.h>
+
+#define SECURITY_REG		(PMGR_BASE_ADDR + 0xA000)
+#define ROM_READ_DISABLE	(1 << 0)
+
+#endif /* ! __PLATFORM_TRAMPOLINE_H */

platform/s5l8940x/include/platform/usbconfig.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2008-2009 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_USBCONFIG_H
+#define __PLATFORM_USBCONFIG_H
+
+#define USBPHY_CLK_TYPE		(3) /* Use CLKCORE */
+
+#if SUB_PLATFORM_S5L8940X
+#define USBPHY_UOTGTUNE1        (0x349)
+#define USBPHY_UOTGTUNE2        (0xF13)
+#elif SUB_PLATFORM_S5L8942X | SUB_PLATFORM_S5L8947X
+#define USBPHY_UOTGTUNE1        (0x349)
+#define USBPHY_UOTGTUNE2        (0x6FF3)
+#endif
+
+#define USBOTG_AHB_DMA_BURST	(DWCUSB_GAHBCFG_HBST_INCR8)
+
+#ifdef WITH_TARGET_USB_CONFIG
+#include <target/usbconfig.h>
+#endif /* WITH_TARGET_USB_CONFIG */
+
+#endif /* ! __PLATFORM_USBCONFIG_H */

platform/s5l8940x/iop_init.c

@@ -0,0 +1,208 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <arch.h>
+#include <arch/arm/arm.h>
+#include <debug.h>
+#include <drivers/a5iop/a5iop.h>
+#include <platform.h>
+#include <platform/clocks.h>
+#include <platform/int.h>
+#include <platform/memmap.h>
+#include <platform/timer.h>
+#include <platform/soc/hwisr.h>
+#include <platform/soc/pmgr.h>
+#include <sys.h>
+#include <sys/boot.h>
+#include <sys/callout.h>
+
+/*
+ * Platform memory layout.
+ *
+ * The IOP sees SDRAM at its physical location uncached, and has an cached aperture
+ * visible elsewhere.  SDRAM size of up to 1GB is currently supported.
+ * SRAM is not visible/legally usable.
+ *
+ * For some platforms/targets, SDRAM_LEN is not constant and so we 
+ * have to compute a maximum via other means.
+ *
+ * Note that the AE2 Sparrow shares this code.
+ */
+#define MEM_CACHED_BASE		(SDRAM_BASE | 0xc0000000)
+#define SDRAM_MAX_LEN		(SDRAM_BANK_LEN * SDRAM_BANK_COUNT)
+struct mem_static_map_entry mem_static_map_entries[] = {
+        {
+                MEM_CACHED_BASE,                        /* cached */
+                SDRAM_BASE,                             /* uncached */
+                SDRAM_BASE,                             /* physical */
+                SDRAM_MAX_LEN                           /* length */
+        },
+        {MAP_NO_ENTRY, MAP_NO_ENTRY, MAP_NO_ENTRY, 0}
+};
+
+void platform_mmu_setup(bool resume)
+{
+	if (false == resume) {
+		/* Remap text base to zero, outer uncacheable, shared */
+		arm_mmu_map_section(0, TEXT_BASE, kARMMMUInnerNormalOuterNoncached, true);
+#ifdef MAP_SRAM_CACHED
+		/* Map the SRAM as cacheable, shared */
+		arm_mmu_map_section(SRAM_BASE, SRAM_BASE, kARMMMUNormal, true);
+#endif // MAP_SRAM_CACHED
+		/* Remap all of SDRAM through the cacheable aperture, outer uncacheable, shared */
+		arm_mmu_map_section_range(MEM_CACHED_BASE, SDRAM_BASE, ROUNDUP(SDRAM_BANK_LEN * SDRAM_BANK_COUNT, MB)/MB,
+					  kARMMMUInnerNormalOuterNoncached, true, false);
+		/* Remap all of SDRAM through the uncacheable aperture (existing mappings should be there, but be sure) */
+		arm_mmu_map_section_range(SDRAM_BASE, SDRAM_BASE, ROUNDUP(SDRAM_BANK_LEN * SDRAM_BANK_COUNT, MB)/MB,
+					  kARMMMUStronglyOrdered, false, false);
+	}
+}
+
+bool platform_get_production_mode(void)
+{
+	return(true);
+}
+
+bool platform_get_secure_mode(void)
+{
+	return(true);
+}
+
+void platform_reset(bool panic)
+{
+	for (;;)
+		;
+}
+
+/*
+ * Early init is done every time the IOP starts.
+ */
+int
+platform_early_init()
+{
+#if PLATFORM_VARIANT_IOP
+	/* In general we want power-gating to be disabled. */
+	rPMGR_PWR_GATE_CTL_CLR = rPMGR_PWR_GATE_IOP;
+	while (rPMGR_PWR_GATE_CTL_CLR & rPMGR_PWR_GATE_IOP) ;
+#endif
+
+	interrupt_init();
+
+	timer_init(0);
+	
+	return(0);
+}
+
+/*
+ * Halt waiting for an interrupt.
+ */
+void
+platform_halt(void)
+{
+	arch_halt();
+}
+
+#if SUPPORT_SLEEP
+
+#if WITH_IOP_POWER_GATING
+
+/*
+ * Deep idle sleep with power gating
+ */
+void
+platform_deep_idle(void)
+{
+	rPMGR_PWR_GATE_CTL_SET = rPMGR_PWR_GATE_IOP;
+	while (!(rPMGR_PWR_GATE_CTL_SET & rPMGR_PWR_GATE_IOP)) ;
+	a5iop_sleep(1);
+	rPMGR_PWR_GATE_CTL_CLR = rPMGR_PWR_GATE_IOP;
+	while (rPMGR_PWR_GATE_CTL_CLR & rPMGR_PWR_GATE_IOP) ;
+}
+
+#endif
+
+void
+platform_sleep(void)
+{
+	/* We assume power-gating is disabled, which it need to be so
+	 * the IOP wrapper registers don't disappear. */
+	a5iop_sleep(0);
+}
+
+#endif
+
+/*
+ * Cache control
+ */
+void
+platform_cache_operation(int operation, void *address, u_int32_t length)
+{
+	a5iop_cache_operation(operation, address, length);
+}
+
+/*
+ * Host doorbell uses a SWI in the AIC.
+ */
+static void	(* _doorbell_handler)(void *arg);
+static void
+platform_doorbell_handler(void *arg)
+{
+	/* clear the doorbell before passing up */
+	interrupt_clear_ipc(INT_IOP);
+	_doorbell_handler(arg);
+}
+
+void
+platform_init_iop_doorbell(void (* handler)(void *arg), void *arg)
+{
+	_doorbell_handler = handler;
+	install_int_handler(INT_IOP, platform_doorbell_handler, arg);
+	set_int_type(INT_IOP, INT_TYPE_IRQ | INT_TYPE_LEVEL);
+	unmask_int(INT_IOP);
+}
+
+void
+platform_mask_doorbell(void)
+{
+	mask_int(INT_IOP);
+}
+
+void
+platform_unmask_doorbell(void)
+{
+	unmask_int(INT_IOP);
+}
+
+void
+platform_ring_host_doorbell(void)
+{
+	interrupt_generate_ipc(INT_HOST);
+}
+
+int
+platform_init_nmi(void (*handler)(void *arg), void *arg)
+{
+#ifdef INT_IOP_NMI
+	install_int_handler(INT_IOP_NMI, handler, arg);
+	set_int_type(INT_IOP_NMI, INT_TYPE_FIQ | INT_TYPE_LEVEL);
+	unmask_int(INT_IOP_NMI);
+#endif
+
+	return(0);
+}
+
+/*
+ * Clock management.
+ *
+ * Currently the IOP does none for this platform.
+ */
+void clock_gate(int device, bool enable)
+{
+}

platform/s5l8940x/miu/miu.c

@@ -0,0 +1,319 @@
+/*
+ * Copyright (C) 2007-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <debug.h>
+#include <drivers/miu.h>
+#include <platform.h>
+#include <platform/memmap.h>
+#include <platform/miu.h>
+#include <platform/soc/miu.h>
+#include <platform/soc/pmgr.h>
+#include <platform/clocks.h>
+#include <platform/soc/hwclocks.h>
+
+static void miu_configure_bridge(const u_int32_t *bridge_settings);
+
+#define BRIDGE_SHIFT		(16)
+#define BRIDGE_MASK		(0xFFFF)
+#define NRT_DART_WIDGETS	(0 << BRIDGE_SHIFT)
+#define NRT_DART_BRIDGE		(1 << BRIDGE_SHIFT)
+#define NRT_TOP_WIDGETS		(2 << BRIDGE_SHIFT)
+#define NRT_TOP_BRIDGE		(3 << BRIDGE_SHIFT)
+#define RT_TOP_WIDGETS		(4 << BRIDGE_SHIFT)
+#define RT_TOP_BRIDGE		(5 << BRIDGE_SHIFT)
+#define UPERF_WIDGETS		(6 << BRIDGE_SHIFT)
+#define UPERF_BRIDGE		(7 << BRIDGE_SHIFT)
+#define CDIO_WIDGETS		(8 << BRIDGE_SHIFT)
+#define CDIO_BRIDGE		(9 << BRIDGE_SHIFT)
+
+static const u_int32_t bridge_registers[] = {
+	NRT_DART_WIDGETS_BASE_ADDR,	NRT_DART_PL301_BASE_ADDR,
+	NRT_TOP_WIDGETS_BASE_ADDR,	NRT_TOP_PL301_BASE_ADDR,
+	RT_TOP_WIDGETS_BASE_ADDR,	RT_TOP_PL301_BASE_ADDR,
+	UPERF_WIDGETS_BASE_ADDR,	UPERF_PL301_BASE_ADDR,
+	CDIO_WIDGETS_BASE_ADDR,		CDIO_PL301_BASE_ADDR,
+};
+
+#if APPLICATION_SECUREROM || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
+// The following settings are based on H4P Tunables Revision 0.12
+
+static const u_int32_t bridge_settings_static[] = {
+	// Configure recommended transaction limits in CDIO
+	CDIO_WIDGETS | CDIO_IOP_RTLIMIT,	0x00000808,
+	CDIO_WIDGETS | CDIO_IOP_WTLIMIT,	0x00000808,
+	CDIO_WIDGETS | CDIO_CDMA_RTLIMIT,	0x00000808,
+	CDIO_WIDGETS | CDIO_CDMA_WTLIMIT,	0x00000808,
+	CDIO_WIDGETS | CDIO_UPERF_RTLIMIT,	0x00000404,
+	CDIO_WIDGETS | CDIO_UPERF_WTLIMIT,	0x00000404,
+	CDIO_WIDGETS | CDIO_AUDIO_RTLIMIT,	0x00000808,
+	CDIO_WIDGETS | CDIO_AUDIO_WTLIMIT,	0x00000808,
+	CDIO_WIDGETS | CDIO_PIO_RTLIMIT,	0x00000808,
+	CDIO_WIDGETS | CDIO_PIO_WTLIMIT,	0x00000404,
+
+	// Configure recommended bridge settings in CDIO
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0,	0x00000000,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0,	0x01000001,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0,	0x02000002,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0,	0x03000003,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0,	0x04000004,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0,	0x00000000,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0,	0x01000001,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0,	0x02000002,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0,	0x03000003,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0,	0x04000004,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1,	0x00000000,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1,	0x01000001,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1,	0x02000002,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1,	0x03000003,
+	CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1,	0x04000004,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1,	0x00000000,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1,	0x01000001,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1,	0x02000002,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1,	0x03000003,
+	CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1,	0x04000004,
+
+	// Configure recommended features in CDIO
+	CDIO_WIDGETS | CDIO_IOP_WREQSP,		0x00000003,
+	CDIO_WIDGETS | CDIO_CDMA_WGATHER,	0x00000100,
+	CDIO_WIDGETS | CDIO_UPERF_WGATHER,	0x00000100,
+	CDIO_WIDGETS | CDIO_AUDIO_WGATHER,	0x00000100,
+
+	// Configure recommended traffic attributes in UPERF
+	//	AxCACHE = Cacheable
+	//	AxUSER = enable Shared bit
+	UPERF_WIDGETS | UPERF_OTG_QOS,		0x01010101,
+	UPERF_WIDGETS | UPERF_OTG_CACHE,	0x01020102,
+	UPERF_WIDGETS | UPERF_EHCI_QOS,		0x01010101,
+	UPERF_WIDGETS | UPERF_EHCI_CACHE,	0x01020102,
+	UPERF_WIDGETS | UPERF_OHCI0_QOS,	0x01010101,
+	UPERF_WIDGETS | UPERF_OHCI0_CACHE,	0x01020102,
+	UPERF_WIDGETS | UPERF_OHCI1_QOS,	0x01010101,
+	UPERF_WIDGETS | UPERF_OHCI1_CACHE,	0x01020102,
+
+	0, 0,
+	0, 0
+};
+#endif	// APPLICATION_SECUREROM || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
+
+#if WITH_DEVICETREE || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
+static const u_int32_t bridge_settings_dynamic[] = {
+	// Configure recommended transaction limits in HPerf-NRT DART
+	NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER0_RTLIMIT,	0x00000707,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER0_WTLIMIT,	0x00000404,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER1_RTLIMIT,	0x00000707,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER1_WTLIMIT,	0x00000404,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_DART_RTLIMIT,		0x00000808,
+	NRT_DART_WIDGETS | HPERF_NRT_DART_DART_WTLIMIT,		0x00000808,
+
+	// Configure recommended bridge settings in HPerf-NRT DART
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI,	0x00000000,	// JPEG0 High Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI,	0x01000001,	// JPEG1 High Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI,	0x02000102,	// Scaler0 Reduced Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI,	0x03000103,	// Sclaer1 Reduced Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI,	0x00000000,	// JPEG0 High Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI,	0x01000001,	// JPEG1 High Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI,	0x02000102,	// Scaler0 Reduced Priority
+	NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI,	0x03000103,	// Sclaer1 Reduced Priority
+
+	// Configure recommended bridge settings in HPerf-NRT DART
+	NRT_DART_WIDGETS | HPERF_NRT_DART_JPEG0_QOS,		0x01010101,	// JPEG0 LLT Traffic for R&W
+	NRT_DART_WIDGETS | HPERF_NRT_DART_JPEG1_QOS,		0x01010101,	// JPEG0 LLT Traffic for R&W
+	0, 0,
+
+	// Configure recommended transaction limits in HPerf-NRT Top
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_VENC_RTLIMIT,		0x00001010,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_VENC_WTLIMIT,		0x00000808,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_VDEC_RTLIMIT,		0x00001010,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_VDEC_WTLIMIT,		0x00000808,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_TOP_RTLIMIT,		0x00003F3F,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_TOP_WTLIMIT,		0x00000F0F,
+
+	// Configure recommended bridge settings in HPerf-NRT Top
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI,		0x00000000,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI,		0x01000001,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI,		0x02000002,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI,		0x03000003,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI,		0x00000000,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI,		0x01000001,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI,		0x02000002,
+	NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI,		0x03000003,
+
+	// Configure recommended features in HPerf-NRT Top
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_DART_WGATHER,		0x00000000,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_VENC_WREQSP,		0x00000003,
+	NRT_TOP_WIDGETS | HPERF_NRT_TOP_VDEC_WREQSP,		0x00000003,
+	0, 0,
+
+	// Configure recommended transaction limits in HPerf-RT Top
+	RT_TOP_WIDGETS | HPERF_RT_TOP_TOP_RTLIMIT,		0x00003F3F,
+	RT_TOP_WIDGETS | HPERF_RT_TOP_TOP_WTLIMIT,		0x00000F0F,
+	RT_TOP_WIDGETS | HPERF_RT_TOP_DISP0_RTLIMIT,		0x00000C0C,
+	RT_TOP_WIDGETS | HPERF_RT_TOP_DISP1_RTLIMIT,		0x00001010,
+	RT_TOP_WIDGETS | HPERF_RT_TOP_ISP_RTLIMIT,		0x00000C0C,
+	RT_TOP_WIDGETS | HPERF_RT_TOP_ISP_WTLIMIT,		0x00001010,
+
+	// Configure recommended bridge settings in HPerf-RT Top
+	RT_TOP_BRIDGE | HPERF_RT_TOP_AR_CHAN_ARB_MI,		0x00000000,
+	RT_TOP_BRIDGE | HPERF_RT_TOP_AR_CHAN_ARB_MI,		0x01000001,
+	RT_TOP_BRIDGE | HPERF_RT_TOP_AR_CHAN_ARB_MI,		0x02000002,
+	0, 0,
+
+	0, 0
+};
+#endif	// WITH_DEVICETREE || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
+
+int miu_initialize_internal_ram(void)
+{
+#if APPLICATION_SECUREROM
+	// Ensure that rPMGR_SCRATCH0-3 get cleared
+	rPMGR_SCRATCH0 = 0;
+	rPMGR_SCRATCH1 = 0;
+	rPMGR_SCRATCH2 = 0;
+	rPMGR_SCRATCH3 = 0;
+#endif /* APPLICATION_SECUREROM */
+
+	// Save the Security Epoch in the top byte of PMGR_SCRATCH0
+	rPMGR_SCRATCH0 &= ~0xFF000000;
+	rPMGR_SCRATCH0 |= (platform_get_security_epoch()) << 24;
+
+	return 0;
+}
+
+int miu_init(void)
+{
+#if APPLICATION_IBOOT && !PRODUCT_IBEC
+	// Verify that the Security Epoch in PMGR_SCRATCH0 matches
+	if ((rPMGR_SCRATCH0 >> 24) != platform_get_security_epoch()) {
+		panic("miu_init: Epoch Mismatch\n");
+	}
+#endif
+
+#if APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC
+	// Configure recommended transaction limits in CIF
+	rCIF_RTLIMIT = 0x00000808;
+	rCIF_WTLIMIT = 0x00000808;
+
+	// Tunables recommendation, for SCU clock-gating
+	// (will change to 0x80 for <rdar://problem/8267114>)
+	rCIF_IDLETMR = 0x00000010;
+#endif
+
+#if APPLICATION_SECUREROM || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
+	// Configure bridges that are statically powered
+	clock_gate(CLK_UPERF, true);
+	miu_configure_bridge(bridge_settings_static);
+	clock_gate(CLK_UPERF, false);
+#endif
+
+#if APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC
+	// Configure bridges that are dynamically powered
+	clock_gate(CLK_HPERFNRT, true);
+	clock_gate(CLK_HPERFRT, true);
+	miu_configure_bridge(bridge_settings_dynamic);
+	clock_gate(CLK_HPERFNRT, false);
+	clock_gate(CLK_HPERFRT, false);
+	
+	/* Enable the SCU.  Note that we explicitly do NOT touch the
+	 * "power status" register, since the default is supposed to
+	 * be correct, and the real control is in the CPU's "SMP"
+	 * bit. */
+	rSCU_TAG_INVAL = 0xff;	/* invalidate SCU tags for all CPUs */
+
+	/* Enable SCU, standby, speculative linefills, and parity */
+	rSCU_CONTROL = (1 << 5) | (1 << 3) | (1 << 2) | (1 << 0);
+#endif
+
+	/* remap whatever bank of ram we're in to zero */
+	if (TEXT_BASE == SRAM_BASE)
+		miu_select_remap(REMAP_SRAM);
+	else if ((TEXT_BASE >= SDRAM_BASE) && (TEXT_BASE < SDRAM_END))
+		miu_select_remap(REMAP_SDRAM);
+
+	return 0;
+}
+
+static void miu_configure_bridge(const u_int32_t *bridge_settings)
+{
+	volatile u_int32_t *reg;
+	u_int32_t cnt = 0, bridge, offset, data;
+
+	while ((bridge_settings[cnt] != 0) || (bridge_settings[cnt + 1] != 0)) {
+		while ((bridge_settings[cnt] != 0) || (bridge_settings[cnt + 1] != 0)) {
+			bridge = bridge_settings[cnt] >> BRIDGE_SHIFT;
+			offset = bridge_settings[cnt] & BRIDGE_MASK;
+			data = bridge_settings[cnt + 1];
+			reg = (volatile u_int32_t *)(bridge_registers[bridge] + offset);
+			*reg = data;
+			cnt += 2;
+		}
+		cnt += 2;
+	}
+}
+
+void miu_suspend(void)
+{
+	/* XXX ? */
+}
+
+int miu_initialize_dram(bool resume)
+{
+#if APPLICATION_IBOOT
+	mcu_initialize_dram(resume);
+#endif
+	return 0;
+}
+
+void miu_select_remap(enum remap_select sel)
+{
+	switch (sel) {
+		case REMAP_SRAM:
+			rREMAP_CTL = (rREMAP_CTL & ~3) | (1 << 0); // remap_sel = 1
+			rPL310_FILTER_START = 0x1;
+			break;
+		case REMAP_SDRAM:
+			rREMAP_CTL = (rREMAP_CTL & ~3) | (2 << 0); // remap_sel = 2
+			// Leave low megabyte heading to DRAM for wake-from-sleep,
+			// Otherwise send everything below DRAM to the PIO block.
+			// Currently this is for testing only; it is not POR.
+			rPL310_FILTER_END   = 0x80000000;
+			rPL310_FILTER_START = 0x00100001;
+			break;
+	}
+
+	/* read remap register to ensure it has been updated */
+	rREMAP_CTL;
+}
+
+void miu_bypass_prep(void)
+{
+#if APPLICATION_IBOOT
+	extern void mcu_bypass_prep(void);
+	mcu_bypass_prep();
+#endif
+}
+
+#if WITH_DEVICETREE
+
+void miu_update_device_tree(DTNode *pmgr_node)
+{
+	u_int32_t propSize;
+	char *propName;
+	void *propData;
+
+	// Fill in the bridge-settings property
+	propName = "bridge-settings";
+	if (FindProperty(pmgr_node, &propName, &propData, &propSize)) {
+		if (propSize >= sizeof(bridge_settings_dynamic)) {
+			memcpy(propData, bridge_settings_dynamic, sizeof(bridge_settings_dynamic));
+		}
+	}
+}
+
+#endif

platform/s5l8940x/miu/rules.mk

@@ -0,0 +1,15 @@
+# Copyright (C) 2007 Apple Inc. All rights reserved.
+#
+# This document is the property of Apple Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple Inc.
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+OPTIONS += \
+	WITH_HW_MIU=1
+
+ALL_OBJS += $(LOCAL_DIR)/miu.o

platform/s5l8940x/pinconfig_s5l8940x.c

@@ -0,0 +1,317 @@
+/*
+ * Copyright (C) 2009-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <drivers/apple/gpio.h>
+#include <platform.h>
+#include <platform/soc/hwregbase.h>
+#include <target.h>
+
+/* Default S5L8940X SoC Pin Configuration */
+
+#define FMI_DRIVE_STR	DRIVE_X3
+
+#if !WITH_TARGET_CONFIG
+static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
+/* Port  0 */
+	CFG_IN,								// GPIO0		-> MENU_KEY
+	CFG_IN,								// GPIO1		-> HOLD_KEY
+	CFG_DISABLED,							// GPIO2		->
+	CFG_DISABLED,							// GPIO3		->
+	CFG_DISABLED,							// GPIO4		->
+	CFG_DISABLED | PULL_DOWN,					// GPIO5		->
+	CFG_DISABLED,							// GPIO6		->
+	CFG_DISABLED | PULL_DOWN,					// GPIO7		->
+
+/* Port  1 */
+	CFG_DISABLED,							// GPIO8		->
+	CFG_DISABLED,							// GPIO9		->
+	CFG_DISABLED,							// GPIO10		->
+	CFG_DISABLED,							// GPIO11		->
+	CFG_DISABLED,							// GPIO12		->
+	CFG_DISABLED,							// GPIO13		->
+	CFG_DISABLED,							// GPIO14		->
+	CFG_DISABLED,							// GPIO15		->
+
+/* Port  2 */
+	CFG_DISABLED,							// GPIO16		-> BOARD_ID[3]
+	CFG_DISABLED,							// GPIO17		->
+	CFG_DISABLED,							// GPIO18		-> BOOT_CONFIG[0]
+	CFG_DISABLED | PULL_DOWN,					// GPIO19		->
+	CFG_DISABLED,							// GPIO20		->
+	CFG_DISABLED,							// GPIO21		->
+	CFG_DISABLED | PULL_DOWN,					// GPIO22		->
+	CFG_DISABLED,							// GPIO23		->
+
+/* Port  3 */
+	CFG_DISABLED | PULL_DOWN,					// GPIO24		->
+	CFG_DISABLED,							// GPIO25		-> BOOT_CONFIG[1]
+	CFG_IN | PULL_DOWN,						// GPIO26		-> FORCE_DFU
+	CFG_DISABLED | PULL_DOWN,					// GPIO27		-> DFU_STATUS
+	CFG_DISABLED,							// GPIO28		-> BOOT_CONFIG[2]
+	CFG_DISABLED,							// GPIO29		-> BOOT_CONFIG[3]
+	CFG_DISABLED,							// GPIO30		->
+	CFG_DISABLED,							// GPIO31		->
+
+/* Port  4 */
+	CFG_DISABLED,							// GPIO32		->
+	CFG_DISABLED,							// GPIO33		->
+	CFG_DISABLED,							// GPIO34		->
+	CFG_DISABLED,							// GPIO35		->
+	CFG_DISABLED,							// GPIO36		->
+	CFG_DISABLED,							// GPIO37		->
+	CFG_DISABLED,							// GPIO38		->
+	CFG_DISABLED,							// GPIO39		->
+
+/* Port  5 */
+	CFG_DISABLED,							// EHCI_PORT_PWR[0]	->
+	CFG_DISABLED,							// EHCI_PORT_PWR[1]	->
+	CFG_DISABLED,							// EHCI_PORT_PWR[2]	->
+	CFG_DISABLED,							// UART1_TXD		->
+	CFG_DISABLED,							// UART1_RXD		->
+	CFG_DISABLED,							// UART1_RTSN		->
+	CFG_DISABLED,							// UART1_CTSN		->
+	CFG_DISABLED,							// UART2_TXD		->
+
+/* Port  6 */
+	CFG_DISABLED,							// UART2_RXD		->
+	CFG_DISABLED,							// UART2_RTSN		->
+	CFG_DISABLED,							// UART2_CTSN		->
+	CFG_DISABLED,							// UART3_TXD		->
+	CFG_DISABLED,							// UART3_RXD		->
+	CFG_DISABLED,							// UART3_RTSN		->
+	CFG_DISABLED,							// UART3_CTSN		->
+	CFG_DISABLED,							// UART5_RTXD		->
+
+/* Port  7 */
+	CFG_DISABLED,							// UART6_TXD		->
+	CFG_DISABLED,							// UART6_RXD		->
+	CFG_DISABLED,							// UART6_RTSN		->
+	CFG_DISABLED,							// UART6_CTSN		->
+	CFG_DISABLED,							// UART4_TXD/SPI4_MOSI	->
+	CFG_DISABLED,							// UART4_RXD/SPI4_MISO	->
+	CFG_DISABLED,							// UART4_RTSN/SPI4_SCLK	->
+	CFG_DISABLED,							// UART4_CTSN/SPI4_SSIN	->
+
+/* Port  8 */
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN3		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN2		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN1		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_WEN		->
+
+/* Port  9 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO5		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO4		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO2		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO1		->
+
+/* Port 10 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO0		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN3		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN2		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN1		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_REN		->
+
+/* Port 11 */
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO5		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO4		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO2		->
+
+/* Port 12 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO1		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO0		->
+	CFG_DISABLED,							// FMI2_CEN3		->
+	CFG_DISABLED,							// FMI2_CEN2		->
+	CFG_DISABLED,							// FMI2_CEN1		->
+	CFG_DISABLED,							// FMI2_CEN0		->
+	CFG_DISABLED,							// FMI2_CLE		->
+	CFG_DISABLED,							// FMI2_ALE		->
+
+/* Port 13 */
+	CFG_DISABLED,							// FMI2_REN		->
+	CFG_DISABLED,							// FMI2_WEN		->
+	CFG_DISABLED,							// FMI2_IO7		->
+	CFG_DISABLED,							// FMI2_IO6		->
+	CFG_DISABLED,							// FMI2_IO5		->
+	CFG_DISABLED,							// FMI2_IO4		->
+	CFG_DISABLED,							// FMI2_DQS		->
+	CFG_DISABLED,							// FMI2_IO3		->
+
+/* Port 14 */
+	CFG_DISABLED,							// FMI2_IO2		->
+	CFG_DISABLED,							// FMI2_IO1		->
+	CFG_DISABLED,							// FMI2_IO0		->
+	CFG_DISABLED,							// FMI0_CEN7		->
+	CFG_DISABLED,							// FMI0_CEN6		->
+	CFG_DISABLED,							// FMI0_CEN5		->
+	CFG_DISABLED,							// FMI0_CEN4		->
+	CFG_DISABLED,							// FMI1_CEN7		->
+
+/* Port 15 */
+	CFG_DISABLED,							// FMI1_CEN6		->
+	CFG_DISABLED,							// FMI1_CEN5		->
+	CFG_DISABLED,							// FMI1_CEN4		->
+	CFG_DISABLED,							// FMI3_CEN3		->
+	CFG_DISABLED,							// FMI3_CEN2		->
+	CFG_DISABLED,							// FMI3_CEN1		->
+	CFG_DISABLED,							// FMI3_CEN0		->
+	CFG_DISABLED,							// FMI3_CLE		->
+
+/* Port 16 */
+	CFG_DISABLED,							// FMI3_ALE		->
+	CFG_DISABLED,							// FMI3_REN		->
+	CFG_DISABLED,							// FMI3_WEN		->
+	CFG_DISABLED,							// FMI3_IO7		->
+	CFG_DISABLED,							// FMI3_IO6		->
+	CFG_DISABLED,							// FMI3_IO5		->
+	CFG_DISABLED,							// FMI3_IO4		->
+	CFG_DISABLED,							// FMI3_DQS		->
+
+/* Port 17 */
+	CFG_DISABLED,							// FMI3_IO3		->
+	CFG_DISABLED,							// FMI3_IO2		->
+	CFG_DISABLED,							// FMI3_IO1		->
+	CFG_DISABLED,							// FMI3_IO0		->
+	CFG_DISABLED,							// FMI2_CEN7		->
+	CFG_DISABLED,							// FMI2_CEN6		->
+	CFG_DISABLED,							// FMI2_CEN5		->
+	CFG_DISABLED,							// FMI2_CEN4		->
+
+/* Port 18 */
+	CFG_DISABLED,							// FMI3_CEN7		->
+	CFG_DISABLED,							// FMI3_CEN6		->
+	CFG_DISABLED,							// FMI3_CEN5		->
+	CFG_DISABLED,							// FMI3_CEN4		->
+	CFG_DISABLED,							// SPI3_MOSI		-> 
+	CFG_DISABLED,							// SPI3_MISO		-> 
+	CFG_DISABLED,							// SPI3_SCLK		-> 
+	CFG_DISABLED,							// SPI3_SSIN		-> 
+
+/* Port 19 */
+	CFG_DISABLED,							// ISP0_PRE_FLASH	->
+	CFG_DISABLED,							// ISP0_FLASH		->
+	CFG_DISABLED,							// ISP1_PRE_FLASH	->
+	CFG_DISABLED,							// ISP1_FLASH		->
+	CFG_DISABLED,							// SPI1_SCLK		->
+	CFG_DISABLED,							// SPI1_MOSI		->
+	CFG_DISABLED,							// SPI1_MISO		->
+	CFG_DISABLED,							// SPI1_SSIN		->
+
+/* Port 20 */
+	CFG_DISABLED,							// I2C2_SDA		->
+	CFG_DISABLED,							// I2C2_SCL		->
+	CFG_DISABLED,							// SPI0_SCLK		-> SPI0_SCLK/BOARD_ID[0]
+	CFG_DISABLED,							// SPI0_MOSI		-> SPI0_MOSI/BOARD_ID[1]
+	CFG_DISABLED,							// SPI0_MISO		-> SPI0_MISO/BOARD_ID[2]
+	CFG_DISABLED | PULL_UP,						// SPI0_SSIN		-> SPI0_SSIN
+	CFG_DISABLED,							// SPI2_SCLK		->
+	CFG_DISABLED,							// SPI2_MOSI		->
+
+/* Port 21 */
+	CFG_DISABLED,							// SPI2_MISO		->
+	CFG_DISABLED,							// SPI2_SSIN		->
+	CFG_DISABLED,							// I2C0_SDA		->
+	CFG_DISABLED,							// I2C0_SCL		->
+	CFG_DISABLED,							// I2C1_SDA		->
+	CFG_DISABLED,							// I2C1_SCL		->
+	CFG_DISABLED,							// ISP0_SDA		->
+	CFG_DISABLED,							// ISP0_SCL		->
+
+/* Port 22 */
+	CFG_DISABLED,							// ISP1_SDA		->
+	CFG_DISABLED,							// ISP1_SCL		->
+	CFG_DISABLED,							// SDIO_CLK		->
+	CFG_DISABLED,							// SDIO_CMD		->
+	CFG_DISABLED,							// SDIO_DATA0		->
+	CFG_DISABLED,							// SDIO_DATA1		->
+	CFG_DISABLED,							// SDIO_DATA2		->
+	CFG_DISABLED,							// SDIO_DATA3		->
+
+/* Port 23 */
+	CFG_DISABLED,							// MIPI_VSYNC		->
+	CFG_DISABLED,							// TMR32_PWM0		->
+	CFG_DISABLED,							// TMR32_PWM1		->
+	CFG_DISABLED,							// TMR32_PWM2		->
+	CFG_DISABLED,							// SWI_DATA		->
+	CFG_DISABLED,							// DWI_DI		->
+	CFG_DISABLED,							// DWI_DO		->
+	CFG_DISABLED,							// DWI_CLK		->
+
+/* Port 24 */
+	CFG_DISABLED,							// SENSOR0_RST		->
+	CFG_DISABLED,							// SENSOR0_CLK		->
+	CFG_DISABLED,							// SENSOR1_RST		->
+	CFG_DISABLED,							// SENSOR1_CLK		->
+	CFG_DISABLED,							// I2S0_MCK		->
+	CFG_DISABLED,							// I2S0_LRCK		->
+	CFG_DISABLED,							// I2S0_BCLK		->
+	CFG_DISABLED,							// I2S0_DOUT		->
+
+/* Port 25 */
+	CFG_DISABLED,							// I2S0_DIN		->
+	CFG_DISABLED,							// I2S1_MCK		->
+	CFG_DISABLED,							// I2S1_LRCK		->
+	CFG_DISABLED,							// I2S1_BCLK		->
+	CFG_DISABLED,							// I2S1_DOUT		->
+	CFG_DISABLED,							// I2S1_DIN		->
+	CFG_DISABLED,							// I2S2_MCK		->
+	CFG_DISABLED,							// I2S2_LRCK		->
+
+/* Port 26 */
+	CFG_DISABLED,							// I2S2_BCLK		->
+	CFG_DISABLED,							// I2S2_DOUT		->
+	CFG_DISABLED,							// I2S2_DIN		->
+	CFG_DISABLED,							// I2S3_MCK		->
+	CFG_DISABLED,							// I2S3_LRCK		->
+	CFG_DISABLED,							// I2S3_BCLK		->
+	CFG_DISABLED,							// I2S3_DOUT		->
+	CFG_DISABLED,							// I2S3_DIN		->
+
+/* Port 27 */
+	CFG_DISABLED,							// SPDIF		->
+	CFG_DISABLED | PULL_DOWN,					// GPIO217		->
+	CFG_DISABLED,							// GPIO218		->
+	CFG_DISABLED,							// DP_HPD		->
+	CFG_DISABLED,							// UART0_TXD		->
+	CFG_DISABLED,							// UART0_RXD		->
+	CFG_DISABLED,							// TST_CLKOUT		->
+	CFG_DISABLED,							// TST_STPCLK		->
+
+/* Port 28 */
+	CFG_DISABLED,							// WDOG			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+};
+
+const uint32_t *platform_get_default_gpio_cfg(uint32_t gpioc)
+{
+	return gpio_default_cfg;
+}
+#endif

platform/s5l8940x/pinconfig_s5l8942x.c

@@ -0,0 +1,288 @@
+/*
+ * Copyright (C) 2009-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#include <drivers/apple/gpio.h>
+#include <platform.h>
+#include <platform/soc/hwregbase.h>
+#include <target.h>
+
+/* Default S5L8942X SoC Pin Configuration */
+
+#define FMI_DRIVE_STR	DRIVE_X2
+#define FMI_SLEW_RATE	SLEW_RATE_SLOW
+
+#if !WITH_TARGET_CONFIG
+static const u_int32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
+/* Port  0 */
+	CFG_IN,								// GPIO0		-> MENU_KEY
+	CFG_IN,								// GPIO1		-> HOLD_KEY
+	CFG_DISABLED,							// GPIO2		->
+	CFG_DISABLED,							// GPIO3		->
+	CFG_DISABLED,							// GPIO4		->
+	CFG_DISABLED,							// GPIO5		->
+	CFG_DISABLED,							// GPIO6		->
+	CFG_DISABLED,							// GPIO7		->
+
+/* Port  1 */
+	CFG_DISABLED,							// GPIO8		->
+	CFG_DISABLED,							// GPIO9		->
+	CFG_DISABLED,							// GPIO10		->
+	CFG_DISABLED,							// GPIO11		->
+	CFG_DISABLED,							// GPIO12		->
+	CFG_DISABLED,							// GPIO13		->
+	CFG_DISABLED,							// GPIO14		->
+	CFG_DISABLED,							// GPIO15		->
+
+/* Port  2 */
+	CFG_DISABLED,							// GPIO16		-> BOARD_ID[3]
+	CFG_DISABLED,							// GPIO17		->
+	CFG_DISABLED,							// GPIO18		-> BOOT_CONFIG[0]
+	CFG_DISABLED,							// GPIO19		-> KEEPACT
+	CFG_DISABLED,							// GPIO20		->
+	CFG_DISABLED,							// GPIO21		->
+	CFG_DISABLED,							// GPIO22		->
+	CFG_DISABLED,							// GPIO23		->
+
+/* Port  3 */
+	CFG_DISABLED,							// GPIO24		->
+	CFG_DISABLED,							// GPIO25		-> BOOT_CONFIG[1]
+	CFG_IN | PULL_DOWN,						// GPIO26		-> FORCE_DFU
+	CFG_DISABLED | PULL_DOWN,					// GPIO27		-> DFU_STATUS
+	CFG_DISABLED,							// GPIO28		-> BOOT_CONFIG[2]
+	CFG_DISABLED,							// GPIO29		-> BOOT_CONFIG[3]
+	CFG_DISABLED,							// GPIO30		->
+	CFG_DISABLED,							// GPIO31		->
+
+/* Port  4 */
+	CFG_DISABLED,							// GPIO32		->
+	CFG_DISABLED,							// GPIO33		->
+	CFG_DISABLED,							// GPIO34		->
+	CFG_DISABLED,							// GPIO35		->
+	CFG_DISABLED,							// GPIO36		->
+	CFG_DISABLED,							// EHCI_PORT_PWR[0]	-> BOARD_REV[0]
+	CFG_DISABLED,							// EHCI_PORT_PWR[1]	-> BOARD_REV[1]
+	CFG_DISABLED,							// EHCI_PORT_PWR[2]	-> BOARD_REV[2]
+
+/* Port  5 */
+	CFG_DISABLED,							// UART1_TXD		->
+	CFG_DISABLED,							// UART1_RXD		->
+	CFG_DISABLED,							// UART1_RTSN		->
+	CFG_DISABLED,							// UART1_CTSN		->
+	CFG_DISABLED,							// UART2_TXD		->
+	CFG_DISABLED,							// UART2_RXD		->
+	CFG_DISABLED,							// UART2_RTSN		->
+	CFG_DISABLED,							// UART2_CTSN		->
+
+/* Port  6 */
+	CFG_DISABLED,							// UART3_TXD		->
+	CFG_DISABLED,							// UART3_RXD		->
+	CFG_DISABLED,							// UART3_RTSN		->
+	CFG_DISABLED,							// UART3_CTSN		->
+	CFG_DISABLED,							// I2C0_SDA		->
+	CFG_DISABLED,							// I2C0_SCL		->
+	CFG_DISABLED,							// I2C1_SDA		->
+	CFG_DISABLED,							// I2C1_SCL		->
+
+/* Port  7 */
+	CFG_DISABLED,							// ISP0_SDA		->
+	CFG_DISABLED,							// ISP0_SCL		->
+	CFG_DISABLED,							// ISP1_SDA		->
+	CFG_DISABLED,							// ISP1_SCL		->
+	CFG_DISABLED,							// UART5_TXD/MIPI_VSYNC	->
+	CFG_DISABLED,							// TMR32_PWM0
+	CFG_DISABLED,							// TMR32_PWM1
+	CFG_DISABLED,							// TMR32_PWM2
+
+/* Port  8 */
+	CFG_DISABLED,							// SWI_DATA		->
+	CFG_DISABLED,							// DWI_DI		->
+	CFG_DISABLED,							// DWI_DO		->
+	CFG_DISABLED,							// DWI_CLK		->
+	CFG_DISABLED,							// SENSOR0_RST		->
+	CFG_DISABLED,							// SENSOR0_CLK		->
+	CFG_DISABLED,							// SENSOR1_RST		->
+	CFG_DISABLED,							// SENSOR1_CLK		->
+
+/* Port  9 */
+	CFG_DISABLED,							// ISP0_PRE_FLASH	->
+	CFG_DISABLED,							// ISP0_FLASH		->
+	CFG_DISABLED,							// ISP1_PRE_FLASH	->
+	CFG_DISABLED,							// ISP1_FLASH		->
+	CFG_DISABLED,							// I2S0_MCK		->
+	CFG_DISABLED,							// I2S0_LRCK		->
+	CFG_DISABLED,							// I2S0_SCLK		->
+	CFG_DISABLED,							// I2S0_DOUT		->
+
+/* Port 10 */
+	CFG_DISABLED,							// I2S0_DIN		->
+	CFG_DISABLED,							// I2S1_MCK		->
+	CFG_DISABLED,							// I2S1_LRCK		->
+	CFG_DISABLED,							// I2S1_SCLK		->
+	CFG_DISABLED,							// I2S1_DOUT		->
+	CFG_DISABLED,							// I2S1_DIN		->
+	CFG_DISABLED,							// I2S2_MCK		->
+	CFG_DISABLED,							// I2S2_LRCK		->
+
+/* Port 11 */
+	CFG_DISABLED,							// I2S2_BCLK		->
+	CFG_DISABLED,							// I2S2_DOUT		->
+	CFG_DISABLED,							// I2S2_DIN		->
+	CFG_DISABLED,							// I2S2_MCK		->
+	CFG_DISABLED,							// I2S3_LRCK		->
+	CFG_DISABLED,							// I2S3_BCLK		->
+	CFG_DISABLED,							// I2S3_DOUT		->
+	CFG_DISABLED,							// I2S3_DIN		->
+
+/* Port 12 */
+	CFG_DISABLED,							// SPI0_SCLK		-> BOARD_ID[0]
+	CFG_DISABLED,							// SPI0_MOSI		-> BOARD_ID[1]
+	CFG_DISABLED,							// SPI0_MISO		-> BOARD_ID[2]
+	CFG_DISABLED | PULL_UP,						// SPI0_SSIN		->
+	CFG_DISABLED,							// SPI1_SCLK		->
+	CFG_DISABLED,							// SPI1_MOSI		->
+	CFG_DISABLED,							// SPI1_MISO		->
+	CFG_DISABLED,							// SPI1_SSIN		->
+
+/* Port 13 */
+	CFG_DISABLED,							// SPI2_SCLK		->
+	CFG_DISABLED,							// SPI2_MOSI		->
+	CFG_DISABLED,							// SPI2_MISO		->
+	CFG_DISABLED,							// SPI2_SSIN		->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 14 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 15 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 16 */
+	CFG_DISABLED,							// UART4_TXD		-> SPI3_SCLK/FMI0_CEN7
+	CFG_DISABLED,							// UART4_RXD		-> SPI3_MOSI/FMI0_CEN6
+	CFG_DISABLED,							// UART4_RTSN		-> SPI3_MISO/FMI0_CEN5
+	CFG_DISABLED,							// UART4_CTSN		-> SPI3_SSIN/FMI0_CEN4
+	CFG_DISABLED,							// SDIO0_DATA3		-> FMI1_CEN7
+	CFG_DISABLED,							// SDIO0_DATA2		-> FMI1_CEN6
+	CFG_DISABLED,							// SDIO0_DATA1		-> FMI1_CEN5
+	CFG_DISABLED,							// SDIO0_DATA0		-> FMI1_CEN4
+
+/* Port 17 */
+	CFG_DISABLED,							// SDIO0_CMD		->
+	CFG_DISABLED,							// SDIO0_CLK		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN3		-> FMI0_RBN0
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN2		-> FMI0_RBN1
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN1		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_ALE		->
+
+/* Port 18 */
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI0_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO5		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO4		->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 19 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 20 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO2		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO1		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI0_IO0		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN3		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN2		->
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN1		->
+
+/* Port 21 */
+	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN0		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_CLE		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_ALE		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_REN		->
+	CFG_DISABLED | PULL_UP | FMI_DRIVE_STR,				// FMI1_WEN		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO7		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO6		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO5		->
+
+/* Port 22 */
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO4		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_DQS		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO3		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO2		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO1		->
+	CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR,			// FMI1_IO0		->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 23 */
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+
+/* Port 24 */
+	CFG_DISABLED,							// I2C2_SDA		->
+	CFG_DISABLED,							// I2C2_SCL		->
+	CFG_DISABLED,							// UART0_TXD		->
+	CFG_DISABLED,							// UART0_RXD		->
+	CFG_DISABLED,							// UART5_RTXD		-> UART5_RXD
+	CFG_DISABLED,							// DP_HPD		->
+	CFG_DISABLED,							// TST_CLKOUT		->
+	CFG_DISABLED,							// TST_STPCLK		->
+
+/* Port 25 */
+	CFG_DISABLED,							// WDOG			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+	CFG_DISABLED,							// 			->
+};
+
+const uint32_t *platform_get_default_gpio_cfg(uint32_t gpioc)
+{
+	return gpio_default_cfg;
+}
+#endif