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/*
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* Copyright (C) 2010-2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <drivers/amc/amc.h>
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#include <drivers/amc/amc_phy.h>
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#include <drivers/amc/amc_regs.h>
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#include <drivers/dram.h>
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#include <drivers/miu.h>
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#include <sys.h>
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int mcu_initialize_dram (bool resume)
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{
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return amc_init(resume);
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}
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void mcu_bypass_prep (int step)
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{
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amc_phy_bypass_prep(step);
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}
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uint64_t mcu_get_memory_size (void)
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{
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return amc_get_memory_size();
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}
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void amc_configure_address_decoding_and_mapping (void)
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{
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amc_configure_default_address_decoding_and_mapping();
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}
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void amc_enable_slow_boot (bool enable)
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{
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int slow_freqsel;
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if (enable) {
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if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
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rAMC_FREQSEL = amc_params.freqsel;
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return;
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}
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slow_freqsel = 3;
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rAMC_BOOTCLK = (amc_params.bootclkdivsr << 8) | 1;
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spin(5);
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rAMC_FREQSEL = slow_freqsel;
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amc_phy_scale_dll(slow_freqsel, amc_params.bootclkdivsr);
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} else {
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if ((amc_params.flags & FLAG_AMC_PARAM_SLOW_BOOT) == false) {
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return;
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}
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rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_small;
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spin(2);
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rAMC_BOOTCLK &= ~1;
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spin(5);
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rAMC_FREQSEL = amc_params.freqsel;
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amc_phy_scale_dll(amc_params.freqsel, 1);
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rAMC_PWRMNGTPARAM = amc_params.pwrmngtparam_guided;
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}
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}
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void amc_finalize (bool resume)
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{
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uint8_t odts;
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#if SUPPORT_FPGA
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rAMC_PWRMNGTEN |= 0x00000001; // Sharing clocks between channels so do not enable clock stopping for PD or SR
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#else
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rAMC_PWRMNGTEN |= 0x00011011;
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#endif
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rAMC_AREFPARAM |= (0x00001000); // Turn on freq change waiting for refresh and self-refresh exit
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amc_mrcmd(MR_READ, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x4, (uintptr_t)&odts);
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rAMC_ODTS = 0x00010080; // [16] => TempDrtEn, [9:0] RdIntrvl XXX based on tREFI
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if (!resume) {
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amc_enable_autorefresh();
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}
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#if !SUPPORT_FPGA
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// Turn of Fast Critical Word Forwarding feature and AIU CWF feature
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// Disabled for NRT <rdar://problem/9416881>
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rAMC_AIUPRT_RD_CWF = 0x00363600;
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rAMC_QBRPARAM = 0x00810000;
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rAMC_QBREN = 0x00111001;
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#endif
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}
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void amc_dram_workarounds (bool resume)
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{
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const struct amc_memory_device_info *dev_info;
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dev_info = amc_get_memory_device_info();
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switch (dev_info->vendor_id) {
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case JEDEC_MANUF_ID_SAMSUNG:
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// <rdar://problem/9454992> H4P Samsung 35nm LPDDR2 Transition for N94
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// TMRS for Samsung 46nm part only
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if ((!resume) && (dev_info->rev_id == 0)) {
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// Test MRS Entry
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xff);
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// Apply Samsung workaround <rdar://problem/9032765>
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// Column Select Line pull in (230ps) TMRS(1)
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x80);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x04);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x08);
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// Latch command
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
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// Column Select Line pull in (230ps) TMRS(2)
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x40);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x01);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x20);
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// Latch command
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
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}
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break;
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case JEDEC_MANUF_ID_HYNIX:
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if (dev_info->rev_id == 0) {
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if (!resume && (dev_info->rev_id2 == 0)) {
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// Test MRS Exit "just in case" <rdar://problem/8769095>
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x00);
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// Test MRS Entry
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xb0);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xe0);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x90);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xa2);
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}
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// <rdar://problem/9585266> H4G UM Update: Modified setting for tMRR timing parameter
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// override tMRR to 3 cycles
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if (dev_info->density == JEDEC_DENSITY_2Gb)
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rAMC_MODE_FREQ(0) = amc_params.freq[0].modereg | 0x3;
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}
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break;
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default:
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break;
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}
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}
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void amc_dram_shift_dq_offset (int8_t *dq_offset, uint8_t num_bytes) {
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// Do nothing for H4G
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}
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@@ -0,0 +1,16 @@
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# Copyright (C) 2010-2011 Apple Inc. All rights reserved.
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#
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# This document is the property of Apple Inc.
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# It is considered confidential and proprietary.
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#
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# This document may not be reproduced or transmitted in any form,
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# in whole or in part, without the express written permission of
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# Apple Inc.
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#
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LOCAL_DIR := $(GET_LOCAL_DIR)
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OPTIONS += \
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WITH_HW_AMC=1
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ALL_OBJS += \
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$(LOCAL_DIR)/amc.o
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@@ -0,0 +1,231 @@
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/*
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* Copyright (C) 2009-2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <lib/env.h>
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#include <platform.h>
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#include <platform/soc/chipid.h>
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#include <platform/soc/hwclocks.h>
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#if SUPPORT_FPGA
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#define _rCFG_FUSE0 (*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x00))
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#undef rCFG_FUSE0
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// XXX ECID (1 << 7)?
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// XXX double-check memory values
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#define rCFG_FUSE0 ((0 << 31) | (3 << 28) | (0xE << 24) | (2 << 22) | \
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(0 << 9) | (1 << 8) | (3 << 4) | (kPlatformSecurityDomainDarwin << 2) | (0 << 1) | (0 << 0) | \
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_rCFG_FUSE0)
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#endif
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#if SUB_PLATFORM_S5L8945X
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#define DEFAULT_SOC_VOLTAGE_LOW 1000
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#define DEFAULT_SOC_VOLTAGE_MED 1100
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#define DEFAULT_SOC_VOLTAGE_HIGH 1200
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#define DEFAULT_CPU_VOLTAGE_LOW 1000
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#define DEFAULT_CPU_VOLTAGE_MED 1150
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#define DEFAULT_CPU_VOLTAGE_HIGH 1250
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#define BASE_SOC_VOLTAGE_LOW 875
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#define BASE_SOC_VOLTAGE_MED 975
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#define BASE_SOC_VOLTAGE_HIGH 1075
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#define BASE_CPU_VOLTAGE_LOW 875
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#define BASE_CPU_VOLTAGE_MED 975
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#define BASE_CPU_VOLTAGE_HIGH 1075
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#endif
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bool chipid_get_production_mode(void)
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{
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return ((rCFG_FUSE0 >> 0) & 1) != 0;
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}
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void chipid_clear_production_mode(void)
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{
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#if SUPPORT_FPGA
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_rCFG_FUSE0 &= ~1;
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#else
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rCFG_FUSE0 &= ~1;
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#endif
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}
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bool chipid_get_secure_mode(void)
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{
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return ((rCFG_FUSE0 >> 1) & 1) != 0;
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}
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u_int32_t chipid_get_security_domain(void)
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{
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return (rCFG_FUSE0 >> 2) & 3;
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}
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u_int32_t chipid_get_board_id(void)
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{
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return (rCFG_FUSE0 >> 4) & 3;
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}
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bool chipid_get_ecid_image_personalization_required(void)
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{
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return ((rCFG_FUSE0 >> 7) & 1) != 0;
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}
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u_int32_t chipid_get_minimum_epoch(void)
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{
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return (rCFG_FUSE0 >> 9) & 0x7F;
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}
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u_int32_t chipid_get_chip_id(void)
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{
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#if SUB_PLATFORM_S5L8945X
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return 0x8945;
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#endif
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}
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u_int32_t chipid_get_chip_revision(void)
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{
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return (((rECIDHI >> 13) & 0x7) << 4) | (((rECIDHI >> 10) & 0x7) << 0);
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}
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u_int32_t chipid_get_osc_frequency(void)
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{
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return OSC_FREQ;
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}
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u_int64_t chipid_get_ecid_id(void)
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{
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u_int64_t ecid = 0;
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#if SUPPORT_FPGA
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ecid = 0x000012345678ABCDULL;
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#else
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ecid |= ((rECIDLO >> 0)) & ((1ULL << (21 - 0)) - 1); // LOT_ID
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ecid <<= (26 - 21);
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ecid |= ((rECIDLO >> 21)) & ((1ULL << (26 - 21)) - 1); // WAFER_NUM
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ecid <<= (10 - 2);
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ecid |= ((rECIDHI >> 2)) & ((1ULL << (10 - 2)) - 1); // Y_POS
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ecid <<= (32 - 26);
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ecid |= ((rECIDLO >> 26)) & ((1ULL << (32 - 26)) - 1); // X_POS_H
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ecid <<= ( 2 - 0);
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ecid |= ((rECIDHI >> 0)) & ((1ULL << ( 2 - 0)) - 1); // X_POS_L
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#endif
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return ecid;
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}
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u_int64_t chipid_get_die_id(void)
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{
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return ((u_int64_t)rECIDHI << 32) | rECIDLO;
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}
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u_int32_t chipid_get_fused_thermal_70C(void)
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{
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return (rCFG_FUSE6 >> 8) & 0xff;
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}
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u_int32_t chipid_get_fused_thermal_25C(void)
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{
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return rCFG_FUSE6 & 0xff;
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}
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u_int32_t chipid_get_fuse_revision(void)
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{
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return (rCFG_FUSE1 >> 25) & 0xf;
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}
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u_int32_t chipid_get_soc_voltage(u_int32_t index)
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{
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u_int32_t soc_voltage = 0;
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u_int32_t soc_bin_offset_data = 0, soc_bin_data = (rCFG_FUSE1 >> 5) & 0x1FF;
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int32_t soc_bin_offset;
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#if DEBUG_BUILD && WITH_ENV
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soc_bin_offset_data = env_get_uint("soc-bin-offset", 0);
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switch (index) {
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case CHIPID_SOC_VOLTAGE_LOW : soc_bin_offset_data = (soc_bin_offset_data >> 0) & 0xff; break;
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case CHIPID_SOC_VOLTAGE_MED : soc_bin_offset_data = (soc_bin_offset_data >> 8) & 0xff; break;
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case CHIPID_SOC_VOLTAGE_HIGH : soc_bin_offset_data = (soc_bin_offset_data >> 16) & 0xff; break;
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default : break;
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}
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#endif
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// if bin data is all zeros, bin data is not valid
|
||||
if (soc_bin_data == 0) {
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switch (index) {
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||||
case CHIPID_SOC_VOLTAGE_LOW : soc_voltage = DEFAULT_SOC_VOLTAGE_LOW; break;
|
||||
case CHIPID_SOC_VOLTAGE_MED : soc_voltage = DEFAULT_SOC_VOLTAGE_MED; break;
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||||
case CHIPID_SOC_VOLTAGE_HIGH : soc_voltage = DEFAULT_SOC_VOLTAGE_HIGH; break;
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default : break;
|
||||
}
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} else {
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switch (index) {
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case CHIPID_SOC_VOLTAGE_LOW : soc_voltage = BASE_SOC_VOLTAGE_LOW + 25 * ((soc_bin_data>>6)&7); break;
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||||
case CHIPID_SOC_VOLTAGE_MED : soc_voltage = BASE_SOC_VOLTAGE_MED + 25 * ((soc_bin_data>>3)&7); break;
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||||
case CHIPID_SOC_VOLTAGE_HIGH : soc_voltage = BASE_SOC_VOLTAGE_HIGH + 25 * ((soc_bin_data>>0)&7); break;
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||||
default : break;
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||||
}
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||||
}
|
||||
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||||
soc_bin_offset = soc_bin_offset_data | (((soc_bin_offset_data & 0x80) == 0) ? 0 : 0xffffff00);
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||||
soc_bin_offset *= 25;
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||||
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||||
return soc_voltage + soc_bin_offset;
|
||||
}
|
||||
|
||||
u_int32_t chipid_get_cpu_voltage(u_int32_t index)
|
||||
{
|
||||
u_int32_t cpu_voltage = 0;
|
||||
u_int32_t cpu_bin_offset_data = 0, cpu_bin_data = ((((u_int64_t)rCFG_FUSE1 << 32) | rCFG_FUSE0) >> 28) & 0x1FF;
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||||
int32_t cpu_bin_offset;
|
||||
|
||||
#if DEBUG_BUILD && WITH_ENV
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||||
cpu_bin_offset_data = env_get_uint("core-bin-offset", 0);
|
||||
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||||
switch (index) {
|
||||
case CHIPID_CPU_VOLTAGE_LOW : cpu_bin_offset_data = (cpu_bin_offset_data >> 0) & 0xff; break;
|
||||
case CHIPID_CPU_VOLTAGE_MED : cpu_bin_offset_data = (cpu_bin_offset_data >> 8) & 0xff; break;
|
||||
case CHIPID_CPU_VOLTAGE_HIGH : cpu_bin_offset_data = (cpu_bin_offset_data >> 16) & 0xff; break;
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||||
default : break;
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||||
}
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||||
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||||
#endif
|
||||
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||||
// if bin data is all zeros, bin data is not valid
|
||||
if (cpu_bin_data == 0) {
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||||
switch (index) {
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||||
case CHIPID_CPU_VOLTAGE_LOW : cpu_voltage = DEFAULT_CPU_VOLTAGE_LOW; break;
|
||||
case CHIPID_CPU_VOLTAGE_MED : cpu_voltage = DEFAULT_CPU_VOLTAGE_MED; break;
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||||
case CHIPID_CPU_VOLTAGE_HIGH : cpu_voltage = DEFAULT_CPU_VOLTAGE_HIGH; break;
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||||
default : break;
|
||||
}
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||||
} else {
|
||||
switch (index) {
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||||
case CHIPID_CPU_VOLTAGE_LOW : cpu_voltage = BASE_CPU_VOLTAGE_LOW + 25 * ((cpu_bin_data>>6)&7); break;
|
||||
case CHIPID_CPU_VOLTAGE_MED : cpu_voltage = BASE_CPU_VOLTAGE_MED + 25 * ((cpu_bin_data>>3)&7); break;
|
||||
case CHIPID_CPU_VOLTAGE_HIGH : cpu_voltage = BASE_CPU_VOLTAGE_HIGH + 25 * ((cpu_bin_data>>0)&7); break;
|
||||
default : break;
|
||||
}
|
||||
}
|
||||
|
||||
cpu_bin_offset = cpu_bin_offset_data | (((cpu_bin_offset_data & 0x80) == 0) ? 0 : 0xffffff00);
|
||||
cpu_bin_offset *= 25;
|
||||
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||||
return cpu_voltage + cpu_bin_offset;
|
||||
}
|
||||
|
||||
bool chipid_get_fuse_lock(void)
|
||||
{
|
||||
return (rCFG_FUSE1 & (1 << 31)) != 0;
|
||||
}
|
||||
|
||||
void chipid_set_fuse_lock(bool locked)
|
||||
{
|
||||
if (locked) rCFG_FUSE1 |= 1 << 31;
|
||||
}
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (C) 2009 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_PLATFORM_CHIPID=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/chipid.o
|
||||
@@ -0,0 +1,155 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#if WITH_TARGET_AMC_PARAMS
|
||||
#include <target/amcconfig.h>
|
||||
#else
|
||||
static const struct amc_param amc_params = {
|
||||
.flags = (FLAG_AMC_PARAM_BUSTAT23 | FLAG_AMC_PARAM_RECONFIG | FLAG_AMC_PARAM_SLOW_BOOT | FLAG_AMC_PARAM_ENABLE_AIU),
|
||||
|
||||
.freqsel = 0,
|
||||
.tREFi = 0x5d,
|
||||
.longsrcnt = 0x2008,
|
||||
.srextrarefcnt = 0x00010000,
|
||||
.tREFi_1Gb = 0xbb,
|
||||
.longsrcnt_1Gb = 0x1004,
|
||||
.rdlat = 6,
|
||||
.wrlat = 3,
|
||||
.phyrdlat = 8, // rdlat + 2
|
||||
.phywrlat = 3,
|
||||
.pdn = 0x33000303,
|
||||
.read = 0x00000103,
|
||||
.bustat = 0x00222212,
|
||||
.bustat2 = 0x00222212,
|
||||
.derate = 0x28831258,
|
||||
.mcphyupdate = 0x05010009,
|
||||
.pwrmngtparam_small = 0x00013000,
|
||||
.pwrmngtparam_guided = 0x00fa3000,
|
||||
.chnldec = 0x00040000,
|
||||
.chnldec2 = 0x00555555,
|
||||
.chnldec4 = 0x00aaaaaa,
|
||||
.autoref_params = 0x00000022,
|
||||
.bootclkdivsr = 8,
|
||||
.arefparam = 0x0600a000,
|
||||
.aref_freq0 = 0x00100100,
|
||||
.aref_freq1 = 0x00100000,
|
||||
.readleveling = 0x01000301,
|
||||
|
||||
.freq = {
|
||||
{ // 400MHz
|
||||
.cas = 0x00000308,
|
||||
.pch = 0x00030611,
|
||||
.act = 0x14040908,
|
||||
.autoref = 0x1834a000,
|
||||
.selfref = 0x00038060,
|
||||
.modereg = 0x00240502,
|
||||
.mifcassch = 0x001f0111,
|
||||
.mifqmaxctrl = 0x00000000,
|
||||
},
|
||||
{ // 200MHz
|
||||
.cas = 0x00000004,
|
||||
.pch = 0x00000009,
|
||||
.act = 0x0a020504,
|
||||
.autoref = 0x0c1a0000,
|
||||
.selfref = 0x0001c000,
|
||||
.modereg = 0x00120000,
|
||||
.mifcassch = 0x00000000,
|
||||
.mifqmaxctrl = 0x00000000,
|
||||
},
|
||||
{ // 100MHz
|
||||
.cas = 0x00000003,
|
||||
.pch = 0x00000005,
|
||||
.act = 0x08020303,
|
||||
.autoref = 0x060d0000,
|
||||
.selfref = 0x0000e000,
|
||||
.modereg = 0x00090000,
|
||||
.mifcassch = 0x00000000,
|
||||
.mifqmaxctrl = 0x00000000,
|
||||
},
|
||||
{ // 50 & 24MHz
|
||||
.cas = 0x00000003,
|
||||
.pch = 0x00000003,
|
||||
.act = 0x08020303,
|
||||
.autoref = 0x03070000,
|
||||
.selfref = 0x00007000,
|
||||
.modereg = 0x00060000,
|
||||
.mifcassch = 0x00000010,
|
||||
.mifqmaxctrl = 0x00000001,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static const struct amc_tunable amc_tunables[] = {
|
||||
// These settings are common across all H4x and H5P. Channel decode and hashing
|
||||
// is done in mainline init code. Any tunables that match hardware defaults are
|
||||
// omitted here.
|
||||
|
||||
{ &rAMC_AIUPRT_CFG, 0x00070000 }, // address error enable
|
||||
{ &rAMC_AIUPRT_RD_GEN, 0x00000018 }, // fence read detect on GFX
|
||||
{ &rAMC_AIUPRT_WR, 0x00000001 }, // out-of-order write, ignore B-bit
|
||||
|
||||
{ &rAMC_AIU_RDBRSTLEN, 0x01010101 }, // burst len is 64B
|
||||
{ &rAMC_AIU_RDMINCRD, 0x7B7B7C7B }, // RT:NRT:CPU:GFX = 40:40:5:10
|
||||
{ &rAMC_AIU_WRBRSTLEN, 0x01010101 }, // burst len is 64B
|
||||
{ &rAMC_AIU_WRMINCRD, 0x7B7B7C7B }, // RT:NRT:CPU:GFX = 40:40:5:10
|
||||
|
||||
{ &rAMC_AIU_CPUSPCREQ, 0x00000019 }, // CPU ageout timer
|
||||
{ &rAMC_AIU_GFXSPCREQ, 0x00000032 }, // GFX ageout timer
|
||||
{ &rAMC_AIU_NRTSPCREQ, 0x00000032 }, // Hperf-NRT ageout timer
|
||||
{ &rAMC_AIU_RTSPCREQ, 0x00000019 }, // Hperf-RT ageout timer
|
||||
{ &rAMC_AIU_WPQSCH, 0x10001000 }, // only supported for Hperf-RT
|
||||
{ &rAMC_AIU_THOTLCPUPARAM, 0x0A4640C4 },
|
||||
{ &rAMC_AIU_THOTLRTPARAM, 0x0A4640C4 },
|
||||
{ &rAMC_AIU_THOTLNRTPARAM, 0x00000000 },
|
||||
{ &rAMC_AIU_THOTLGFXPARAM, 0x00000000 },
|
||||
{ &rAMC_AIU_PUSHEN, 0x00001100 }, // only supported for Hperf-RT
|
||||
|
||||
{ &rAMC_OPIDLETMR, 0x00200000 },
|
||||
{ &rAMC_OPTMRADJEN, 0x00000001 },
|
||||
{ &rAMC_OPTMRADJPARAM, 0x20400064 },
|
||||
|
||||
{ &rAMC_MIFACTSCH, 0x00000001 },
|
||||
|
||||
{ &rAMC_PSQRQTIMER0, 0x00000040 }, // RTG bypass up to 64 transactions
|
||||
{ &rAMC_PSQRQTIMER1, 0x00000018 }, // RTY bypass up to 24 transactions
|
||||
{ &rAMC_PSQRQTIMER2, 0x00000020 }, // RTG bypass up to 32 transactions
|
||||
{ &rAMC_PSQRQBRST, 0x040c040c }, // RTR transactions don't affect read burst size
|
||||
{ &rAMC_PSQRQSCHCRD, 0x002028f5 }, // read credits = 2 * write credits
|
||||
{ &rAMC_PSQWQBRST, 0x0208040c }, // RTR reads cause reduced write burst size
|
||||
{ &rAMC_PSQWQSCHCRD, 0x001014f5 }, // write credits = 1/2 * read credits
|
||||
{ &rAMC_MCUQOS, 0x00010f04 }, // RTG=4, RTY=15, enable pick-oldest-RTY
|
||||
|
||||
// Platform specific
|
||||
|
||||
{ &rAMC_AIU_RDMAXCRD, 0x1928047F }, // RT:NRT:CPU:GFX = 40:40:5:10
|
||||
{ &rAMC_AIU_RDREFL, 0x1421037F }, // 5/6 of AIURDMAXCRD fields
|
||||
{ &rAMC_AIU_WRMAXCRD, 0x1928047F }, // RT:NRT:CPU:GFX = 40:40:5:10
|
||||
{ &rAMC_AIU_WRREFL, 0x1421037F }, // 5/6 of AIUWRMAXCRD fields
|
||||
{ &rAMC_AIU_THOTLEN, 0x00000000 }, // enable throttling
|
||||
{ &rAMC_PSQRQCTL1, 0x0000112A }, // ages write out faster than default (1/2 SelfRef)
|
||||
{ &rAMC_PSQWQCTL1, 0x00000180 }, // ages write out faster than default (1/2 SelfRef)
|
||||
{ &rAMC_MCUQOSLLT, 0x00010108 },
|
||||
{ &rAMC_PWRMNGTPARAM, 0x03001000 }, // SelfRef timer = 384 cycles
|
||||
|
||||
// There is a bug around write merge, which we believe is avoided
|
||||
// in current drivers: <rdar://problem/9076703>
|
||||
// Power and performance measurements of disabling write merging were
|
||||
// done: <rdar://problem/9092558> <rdar://problem/9087726>
|
||||
{ &rAMC_PSQWQCTL0, 0x00010100 }, // Write merge enable
|
||||
|
||||
{ &rAMC_AIU_ADDRBANKHASH0, 0x00006db6 }, // Enable bank hashing, bank[0] derived from bits 0,3,6,..
|
||||
{ &rAMC_AIU_ADDRBANKHASH1, 0x00005b6d }, // Enable bank hashing, bank[1] derived from bits 1,4,7,..
|
||||
{ &rAMC_AIU_ADDRBANKHASH2, 0x000036db }, // Enable bank hashing, bank[2] derived from bits 2,5,8,..
|
||||
{ &rAMC_AIU_CHNLCRD, 0x00180018 },
|
||||
{ &rAMC_AIU_CHNLTM, 0x00006101 },
|
||||
{ &rAMC_AIU_LLTSCHCTL, 0x00000001 }, // Ensure LLT traffic from all ports is treated as medium priority request in the AIU arbitration
|
||||
};
|
||||
#endif
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The amg_param struct is defined in drivers/apple/amg/amg.h, and this
|
||||
* file should only by included from amg.c.
|
||||
*/
|
||||
|
||||
#if WITH_TARGET_AMG_PARAMS
|
||||
#include <target/amgconfig.h>
|
||||
#else
|
||||
static const struct amg_params amc_phy_params = {
|
||||
.flags = 0,
|
||||
.core_config = 0x00001053,
|
||||
.read_latency = 0x0000669b,
|
||||
.gate_offset = 0x08080808,
|
||||
};
|
||||
#endif
|
||||
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_GPIODEF_H
|
||||
#define __PLATFORM_GPIODEF_H
|
||||
|
||||
/* S5L8945X specific gpio -> pin mappings */
|
||||
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#if WITH_TARGET_CONFIG
|
||||
# include <target/gpiodef.h>
|
||||
#endif
|
||||
|
||||
/* define platform-specific gpios in a generic fashion here. */
|
||||
#define GPIO_IIC0_SCL GPIO(12, 4)
|
||||
#define GPIO_IIC0_SDA GPIO(12, 3)
|
||||
#define GPIO_IIC1_SCL GPIO(12, 6)
|
||||
#define GPIO_IIC1_SDA GPIO(12, 5)
|
||||
#define GPIO_IIC2_SCL GPIO(10, 1)
|
||||
#define GPIO_IIC2_SDA GPIO(10, 0)
|
||||
|
||||
#define GPIO_BOARD_ID0 GPIO( 1, 0)
|
||||
#define GPIO_BOARD_ID1 GPIO( 1, 1)
|
||||
#define GPIO_BOARD_ID2 GPIO( 1, 2)
|
||||
#define GPIO_BOARD_ID3 GPIO( 6, 4)
|
||||
|
||||
#define GPIO_BOOT_CONFIG0 GPIO( 6, 6)
|
||||
#define GPIO_BOOT_CONFIG1 GPIO( 7, 5)
|
||||
#define GPIO_BOOT_CONFIG2 GPIO( 8, 0)
|
||||
#define GPIO_BOOT_CONFIG3 GPIO( 8, 1)
|
||||
|
||||
#define GPIO_REQUEST_DFU1 GPIO( 4, 5) // formerly known as HOLD_KEY
|
||||
#define GPIO_REQUEST_DFU2 GPIO( 4, 4) // formerly known as MENU_KEY
|
||||
#define GPIO_FORCE_DFU GPIO( 7, 6)
|
||||
#define GPIO_DFU_STATUS GPIO( 7, 7)
|
||||
|
||||
#define SPI_NOR0 (0)
|
||||
#define SPI_NOR3 (3)
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define GPIO_SPI0_CS GPIO(GPIO_PAD_SPI, 0)
|
||||
#define GPIO_SPI3_CS GPIO(GPIO_PAD_SPI, 3)
|
||||
#else
|
||||
#define GPIO_SPI0_CS GPIO( 1, 3)
|
||||
#define GPIO_SPI3_CS GPIO(19, 5)
|
||||
#endif
|
||||
|
||||
#define GPIO_UART1_TXD GPIO(10, 2)
|
||||
|
||||
#define GPIO_SYSTEM_RESET GPIO(17, 2)
|
||||
|
||||
#endif /* ! __PLATFORM_GPIODEF_H */
|
||||
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_IMAGE_DEVICES_H
|
||||
#define __PLATFORM_IMAGE_DEVICES_H
|
||||
|
||||
static const struct image_device platform_image_devices[] = {
|
||||
#if defined(WITH_NAND_BOOT)
|
||||
{ "nand_firmware", 0x00000 }
|
||||
#else
|
||||
{ "nor0", 0x00000 }
|
||||
#endif
|
||||
};
|
||||
|
||||
#if WITH_SYSCFG
|
||||
static const struct image_device platform_syscfg_devices[] = {
|
||||
#if defined(WITH_NAND_BOOT)
|
||||
{ "nand_syscfg", 0x00000 }
|
||||
#else
|
||||
{ "nor0", 0x00000 }
|
||||
#endif
|
||||
};
|
||||
#endif /* WITH_SYSCFG */
|
||||
|
||||
#endif /* ! __PLATFORM_IMAGE_DEVICES_H */
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_MEMCONFIG_H
|
||||
#define __PLATFORM_MEMCONFIG_H
|
||||
|
||||
/* S5L8945X SoC Mem Pin Configuration */
|
||||
|
||||
static const gpio_t memory_interface_gpios[] = {
|
||||
/* Not needed */
|
||||
};
|
||||
#endif /* ! __PLATFORM_MEMCONFIG_H */
|
||||
@@ -0,0 +1,125 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_MEMMAP_H
|
||||
#define __PLATFORM_MEMMAP_H
|
||||
|
||||
#include <platform/memmap_defaults.h>
|
||||
|
||||
/* S5L8945X specific memory map */
|
||||
#define SDRAM_BASE (0x80000000ULL)
|
||||
#define SDRAM_BANK_LEN (0x20000000ULL)
|
||||
#define SDRAM_BANK_COUNT (2)
|
||||
#define SDRAM_END (SDRAM_BASE + (SDRAM_BANK_LEN * SDRAM_BANK_COUNT))
|
||||
#define VROM_BASE (0x3F000000ULL)
|
||||
#define VROM_BANK_LEN (0x00100000ULL)
|
||||
#define VROM_LEN (0x00010000ULL)
|
||||
#define SRAM_BASE (0x34000000ULL)
|
||||
#define SRAM_BANK_LEN (0x00100000ULL)
|
||||
#define SRAM_LEN (0x00040000ULL)
|
||||
|
||||
/* Sleep token is stored at first physical page in kernel memory */
|
||||
#define SLEEP_TOKEN_BUFFER_BASE (SDRAM_BASE)
|
||||
|
||||
/* reserved area for panic info */
|
||||
#define PANIC_SIZE (0x00004000ULL)
|
||||
#define PANIC_BASE (SDRAM_END - PANIC_SIZE)
|
||||
|
||||
/* reserved area for iBoot */
|
||||
#define IBOOT_SIZE (0x00100000 - PANIC_SIZE)
|
||||
#define IBOOT_BASE (PANIC_BASE - IBOOT_SIZE)
|
||||
#define PROTECTED_REGION_SIZE IBOOT_SIZE
|
||||
|
||||
/* reserved area for display */
|
||||
#define DISPLAY_SIZE (0x03F00000ULL)
|
||||
#define DISPLAY_BASE (IBOOT_BASE - DISPLAY_SIZE)
|
||||
|
||||
/* where to stick the mmu tt, default heap and insecure memory*/
|
||||
#if APPLICATION_SECUREROM
|
||||
#define MMU_TT_SIZE (0x4000ULL)
|
||||
#define MMU_TT_BASE (SRAM_BASE + SRAM_LEN - MMU_TT_SIZE)
|
||||
#define MMU_NONCACHE0_SIZE (SRAM_BANK_LEN)
|
||||
#define MMU_NONCACHE0_PBASE (SRAM_BASE)
|
||||
#define MMU_NONCACHE0_VBASE (SRAM_BASE + SRAM_BANK_LEN * 3)
|
||||
|
||||
#define STACK_SIZE (0x3000ULL)
|
||||
#define STACK_BASE (MMU_TT_BASE - STACK_SIZE)
|
||||
|
||||
#define HEAP_END (STACK_BASE)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define INSECURE_MEMORY_BASE (SRAM_BASE)
|
||||
#define INSECURE_MEMORY_SIZE ((uintptr_t)__segment_start(__DATA) - INSECURE_MEMORY_BASE)
|
||||
|
||||
#endif /* ! __ASSEMBLY__ */
|
||||
|
||||
#endif /* APPLICATION_SECUREROM */
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
#define MMU_TT_SIZE (0x4000ULL)
|
||||
#define MMU_TT_BASE (TEXT_BASE + TEXT_FOOTPRINT - MMU_TT_SIZE)
|
||||
#define MMU_NONCACHE0_SIZE (SRAM_BANK_LEN)
|
||||
#define MMU_NONCACHE0_PBASE (SRAM_BASE)
|
||||
#define MMU_NONCACHE0_VBASE (SRAM_BASE + SRAM_BANK_LEN * 3)
|
||||
#define MMU_NONCACHE1_SIZE (0x40000000ULL)
|
||||
#define MMU_NONCACHE1_PBASE (0x80000000ULL)
|
||||
#define MMU_NONCACHE1_VBASE (0xC0000000ULL)
|
||||
|
||||
#if WITH_DFU_MODE
|
||||
#define STACK_SIZE (0x3000ULL)
|
||||
|
||||
#define INSECURE_MEMORY_SIZE (0x00200000ULL)
|
||||
#define INSECURE_MEMORY_BASE (SDRAM_BASE + SDRAM_BANK_LEN - INSECURE_MEMORY_SIZE)
|
||||
|
||||
#define HEAP_EXT_SIZE (0x00100000ULL)
|
||||
#define HEAP_EXT_BASE (INSECURE_MEMORY_BASE - HEAP_EXT_SIZE)
|
||||
|
||||
#else /* !WITH_DFU_MODE */
|
||||
#define STACK_SIZE (0x1000ULL)
|
||||
|
||||
#define INSECURE_MEMORY_BASE (SDRAM_BASE)
|
||||
#define INSECURE_MEMORY_SIZE (DEFAULT_KERNEL_ADDRESS - SDRAM_BASE)
|
||||
|
||||
#define SECURE_MEMORY_BASE (INSECURE_MEMORY_BASE + INSECURE_MEMORY_SIZE)
|
||||
/* If only 1 bank is populated, this only clears to the alias of
|
||||
* DISPLAY_BASE in the first bank. If 2 banks are populated, this
|
||||
* clears all the was to DISPLAY_BASE in the second bank. */
|
||||
#define SECURE_MEMORY_SIZE (DISPLAY_BASE - SECURE_MEMORY_BASE - SDRAM_BANK_LEN * 2 + platform_get_memory_size())
|
||||
|
||||
#define HEAP_EXT_BASE (DEFAULT_FREE_ADDRESS)
|
||||
#define HEAP_EXT_SIZE (DISPLAY_BASE - SDRAM_BANK_LEN - HEAP_EXT_BASE)
|
||||
#endif /* !WITH_DFU_MODE */
|
||||
|
||||
#define STACK_BASE (MMU_TT_BASE - STACK_SIZE)
|
||||
|
||||
#define HEAP_END (STACK_BASE)
|
||||
|
||||
#endif /* APPLICATION_IBOOT */
|
||||
|
||||
#define SCRATCH_BASE (0x33600000ULL)
|
||||
#define SCRATCH_LEN (2048)
|
||||
|
||||
#if APPLICATION_EMBEDDEDIOP
|
||||
# if ARCH_ARMv7
|
||||
# define MMU_TT_SIZE (0x4000ULL)
|
||||
# endif
|
||||
|
||||
#define AUDIO_SRAM_RESERVE (0x1000ULL)
|
||||
#define USB_SRAM_RESERVE (0x10000ULL)
|
||||
|
||||
#if TARGET_S5L8945XAE2
|
||||
#define HEAP_EXT_BASE (SRAM_BASE + AUDIO_SRAM_RESERVE)
|
||||
#define HEAP_EXT_SIZE (SRAM_LEN - AUDIO_SRAM_RESERVE - USB_SRAM_RESERVE)
|
||||
#endif /* TARGET_S5L8945XAE2 */
|
||||
|
||||
#endif /* !APPLICATION_EMBEDDEDIOP */
|
||||
|
||||
#endif /* ! __PLATFORM_MEMMAP_H */
|
||||
@@ -0,0 +1,330 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_PINCONFIG_H
|
||||
#define __PLATFORM_PINCONFIG_H
|
||||
|
||||
/* Default S5L8945X SoC Pin Configuration */
|
||||
|
||||
#define FMI_DRIVE_STR DRIVE_X3
|
||||
|
||||
static const u_int32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // UART2_TXD ->
|
||||
CFG_DISABLED, // UART2_RXD ->
|
||||
CFG_DISABLED, // UART2_RTSN ->
|
||||
CFG_DISABLED, // UART2_CTSN ->
|
||||
CFG_DISABLED, // UART6_TXD ->
|
||||
CFG_DISABLED, // UART6_RXD ->
|
||||
CFG_DISABLED, // UART6_RTSN ->
|
||||
CFG_DISABLED, // UART6_CTSN ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // SPI0_SCLK -> SPI0_SCLK/BOARD_ID[0]
|
||||
CFG_DISABLED, // SPI0_MOSI -> SPI0_MOSI/BOARD_ID[1]
|
||||
CFG_DISABLED, // SPI0_MISO -> SPI0_MISO/BOARD_ID[2]
|
||||
CFG_DISABLED | PULL_UP, // SPI0_SSIN -> SPI0_SSIN
|
||||
CFG_DISABLED, // UART4_TXD/SPI4_MOSI ->
|
||||
CFG_DISABLED, // UART4_RXD/SPI4_MISO ->
|
||||
CFG_DISABLED, // UART4_RTSN/SPI4_SCLK ->
|
||||
CFG_DISABLED, // UART4_CTSN/SPI4_SSIN ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED, // DP_HPD ->
|
||||
CFG_DISABLED, // EDP_HPD ->
|
||||
CFG_DISABLED, // UART0_TXD ->
|
||||
CFG_DISABLED, // UART0_RXD ->
|
||||
CFG_IN, // GPIO0 -> MENU_KEY (REQUEST_DFU2)
|
||||
CFG_IN, // GPIO1 -> HOLD_KEY (REQUEST_DFU1)
|
||||
CFG_DISABLED, // GPIO2 ->
|
||||
CFG_DISABLED, // GPIO3 ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // GPIO4 ->
|
||||
CFG_DISABLED | PULL_DOWN, // GPIO5 ->
|
||||
CFG_DISABLED, // GPIO6 ->
|
||||
CFG_DISABLED | PULL_DOWN, // GPIO7 ->
|
||||
CFG_DISABLED, // GPIO8 ->
|
||||
CFG_DISABLED, // GPIO9 ->
|
||||
CFG_DISABLED, // GPIO10 ->
|
||||
CFG_DISABLED, // GPIO11 ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED, // GPIO12 ->
|
||||
CFG_DISABLED, // GPIO13 ->
|
||||
CFG_DISABLED, // GPIO14 ->
|
||||
CFG_DISABLED, // GPIO15 ->
|
||||
CFG_DISABLED, // GPIO16 -> BOARD_ID[3]
|
||||
CFG_DISABLED, // GPIO17 ->
|
||||
CFG_DISABLED, // GPIO18 -> BOOT_CONFIG[0]
|
||||
CFG_DISABLED | PULL_DOWN, // GPIO19 ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED, // GPIO20 ->
|
||||
CFG_DISABLED, // GPIO21 ->
|
||||
CFG_DISABLED | PULL_DOWN, // GPIO22 ->
|
||||
CFG_DISABLED, // GPIO23 ->
|
||||
CFG_DISABLED | PULL_DOWN, // GPIO24 ->
|
||||
CFG_DISABLED, // GPIO25 -> BOOT_CONFIG[1]
|
||||
CFG_IN | PULL_DOWN, // GPIO26 -> FORCE_DFU
|
||||
CFG_DISABLED | PULL_DOWN, // GPIO27 -> DFU_STATUS
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // GPIO28 -> BOOT_CONFIG[2]
|
||||
CFG_DISABLED, // GPIO29 -> BOOT_CONFIG[3]
|
||||
CFG_DISABLED, // GPIO30 ->
|
||||
CFG_DISABLED, // GPIO31 ->
|
||||
CFG_DISABLED, // GPIO32 ->
|
||||
CFG_DISABLED, // GPIO33 ->
|
||||
CFG_DISABLED, // GPIO34 ->
|
||||
CFG_DISABLED, // GPIO35 ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // GPIO36 ->
|
||||
CFG_DISABLED, // GPIO37 ->
|
||||
CFG_DISABLED, // GPIO38 ->
|
||||
CFG_DISABLED, // GPIO39 ->
|
||||
CFG_DISABLED, // SPI1_SCLK ->
|
||||
CFG_DISABLED, // SPI1_MOSI ->
|
||||
CFG_DISABLED, // SPI1_MISO ->
|
||||
CFG_DISABLED, // SPI1_SSIN ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // I2C2_SDA ->
|
||||
CFG_DISABLED, // I2C2_SCL ->
|
||||
CFG_DISABLED, // UART1_TXD ->
|
||||
CFG_DISABLED, // UART1_RXD ->
|
||||
CFG_DISABLED, // UART1_RTSN ->
|
||||
CFG_DISABLED, // UART1_CTSN ->
|
||||
CFG_DISABLED, // UART3_TXD ->
|
||||
CFG_DISABLED, // UART3_RXD ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // UART3_RTSN ->
|
||||
CFG_DISABLED, // UART3_CTSN ->
|
||||
CFG_DISABLED, // UART5_RTXD ->
|
||||
CFG_DISABLED, // ISP0_SDA ->
|
||||
CFG_DISABLED, // ISP0_SCL ->
|
||||
CFG_DISABLED, // ISP1_SDA ->
|
||||
CFG_DISABLED, // ISP1_SCL ->
|
||||
CFG_DISABLED, // SPI2_SCLK ->
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // SPI2_MOSI ->
|
||||
CFG_DISABLED, // SPI2_MISO ->
|
||||
CFG_DISABLED, // SPI2_SSIN ->
|
||||
CFG_DISABLED, // I2C0_SDA ->
|
||||
CFG_DISABLED, // I2C0_SCL ->
|
||||
CFG_DISABLED, // I2C1_SDA ->
|
||||
CFG_DISABLED, // I2C1_SCL ->
|
||||
CFG_DISABLED, // MIPI_VSYNC ->
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // TMR32_PWM0 ->
|
||||
CFG_DISABLED, // TMR32_PWM1 ->
|
||||
CFG_DISABLED, // TMR32_PWM2 ->
|
||||
CFG_DISABLED, // SWI_DATA ->
|
||||
CFG_DISABLED, // DWI_DI ->
|
||||
CFG_DISABLED, // DWI_DO ->
|
||||
CFG_DISABLED, // DWI_CLK ->
|
||||
CFG_DISABLED, // SENSOR0_RST ->
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // SENSOR0_CLK ->
|
||||
CFG_DISABLED, // SENSOR1_RST ->
|
||||
CFG_DISABLED, // SENSOR1_CLK ->
|
||||
CFG_DISABLED, // I2S0_MCK ->
|
||||
CFG_DISABLED, // I2S0_LRCK ->
|
||||
CFG_DISABLED, // I2S0_BCLK ->
|
||||
CFG_DISABLED, // I2S0_DOUT ->
|
||||
CFG_DISABLED, // I2S0_DIN ->
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // I2S1_MCK ->
|
||||
CFG_DISABLED, // I2S1_LRCK ->
|
||||
CFG_DISABLED, // I2S1_BCLK ->
|
||||
CFG_DISABLED, // I2S1_DOUT ->
|
||||
CFG_DISABLED, // I2S1_DIN ->
|
||||
CFG_DISABLED, // I2S2_MCK ->
|
||||
CFG_DISABLED, // I2S2_LRCK ->
|
||||
CFG_DISABLED, // I2S2_BCLK ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED, // I2S2_DOUT ->
|
||||
CFG_DISABLED, // I2S2_DIN ->
|
||||
CFG_DISABLED, // I2S3_MCK ->
|
||||
CFG_DISABLED, // I2S3_LRCK ->
|
||||
CFG_DISABLED, // I2S3_BCLK ->
|
||||
CFG_DISABLED, // I2S3_DOUT ->
|
||||
CFG_DISABLED, // I2S3_DIN ->
|
||||
CFG_DISABLED, // SPDIF ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // TST_CLKOUT ->
|
||||
CFG_DISABLED, // TST_STPCLK ->
|
||||
CFG_DISABLED, // WDOG ->
|
||||
CFG_DISABLED, // EHCI_PORT_PWR[0] ->
|
||||
CFG_DISABLED, // EHCI_PORT_PWR[1] ->
|
||||
CFG_DISABLED, // EHCI_PORT_PWR[2] ->
|
||||
CFG_DISABLED, // SDIO_CLK ->
|
||||
CFG_DISABLED, // SDIO_CMD ->
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED, // SDIO_DATA0 ->
|
||||
CFG_DISABLED, // SDIO_DATA1 ->
|
||||
CFG_DISABLED, // SDIO_DATA2 ->
|
||||
CFG_DISABLED, // SDIO_DATA3 ->
|
||||
CFG_DISABLED, // GPIO_3V_0 ->
|
||||
CFG_DISABLED, // GPIO_3V_1 ->
|
||||
CFG_DISABLED, // ISP0_PRE_FLASH ->
|
||||
CFG_DISABLED, // ISP0_FLASH ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // ISP1_PRE_FLASH ->
|
||||
CFG_DISABLED, // ISP1_FLASH ->
|
||||
CFG_DISABLED, // SPI3_MOSI ->
|
||||
CFG_DISABLED, // SPI3_MISO ->
|
||||
CFG_DISABLED, // SPI3_SCLK ->
|
||||
CFG_DISABLED, // SPI3_SSIN ->
|
||||
CFG_DISABLED, // FMI0_CEN7 ->
|
||||
CFG_DISABLED, // FMI0_CEN6 ->
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // FMI0_CEN5 ->
|
||||
CFG_DISABLED, // FMI0_CEN4 ->
|
||||
CFG_DISABLED, // FMI1_CEN7 ->
|
||||
CFG_DISABLED, // FMI1_CEN6 ->
|
||||
CFG_DISABLED, // FMI1_CEN5 ->
|
||||
CFG_DISABLED, // FMI1_CEN4 ->
|
||||
CFG_DISABLED, // FMI2_CEN7 ->
|
||||
CFG_DISABLED, // FMI2_CEN6 ->
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // FMI2_CEN5 ->
|
||||
CFG_DISABLED, // FMI2_CEN4 ->
|
||||
CFG_DISABLED, // FMI3_CEN7 ->
|
||||
CFG_DISABLED, // FMI3_CEN6 ->
|
||||
CFG_DISABLED, // FMI3_CEN5 ->
|
||||
CFG_DISABLED, // FMI3_CEN4 ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI0_IO7 ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI0_IO6 ->
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI0_IO5 ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI0_IO4 ->
|
||||
CFG_DISABLED | PULL_UP | FMI_DRIVE_STR, // FMI0_DQS ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI0_IO3 ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI0_IO2 ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI0_IO1 ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI0_IO0 ->
|
||||
CFG_DISABLED | PULL_UP | FMI_DRIVE_STR, // FMI0_REN ->
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED | PULL_UP | FMI_DRIVE_STR, // FMI0_WEN ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI0_ALE ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI0_CLE ->
|
||||
CFG_DISABLED | FMI_DRIVE_STR, // FMI0_CEN3 ->
|
||||
CFG_DISABLED | FMI_DRIVE_STR, // FMI0_CEN2 ->
|
||||
CFG_DISABLED | FMI_DRIVE_STR, // FMI0_CEN1 ->
|
||||
CFG_DISABLED | FMI_DRIVE_STR, // FMI0_CEN0 ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI1_IO7 ->
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI1_IO6 ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI1_IO5 ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI1_IO4 ->
|
||||
CFG_DISABLED | PULL_UP | FMI_DRIVE_STR, // FMI1_DQS ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI1_IO3 ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI1_IO2 ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI1_IO1 ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI1_IO0 ->
|
||||
|
||||
/* Port 25 */
|
||||
CFG_DISABLED | PULL_UP | FMI_DRIVE_STR, // FMI1_REN ->
|
||||
CFG_DISABLED | PULL_UP | FMI_DRIVE_STR, // FMI1_WEN ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI1_ALE ->
|
||||
CFG_DISABLED | PULL_DOWN | FMI_DRIVE_STR, // FMI1_CLE ->
|
||||
CFG_DISABLED | FMI_DRIVE_STR, // FMI1_CEN3 ->
|
||||
CFG_DISABLED | FMI_DRIVE_STR, // FMI1_CEN2 ->
|
||||
CFG_DISABLED | FMI_DRIVE_STR, // FMI1_CEN1 ->
|
||||
CFG_DISABLED | FMI_DRIVE_STR, // FMI1_CEN0 ->
|
||||
|
||||
/* Port 26 */
|
||||
CFG_DISABLED, // FMI2_IO7 ->
|
||||
CFG_DISABLED, // FMI2_IO6 ->
|
||||
CFG_DISABLED, // FMI2_IO5 ->
|
||||
CFG_DISABLED, // FMI2_IO4 ->
|
||||
CFG_DISABLED, // FMI2_DQS ->
|
||||
CFG_DISABLED, // FMI2_IO3 ->
|
||||
CFG_DISABLED, // FMI2_IO2 ->
|
||||
CFG_DISABLED, // FMI2_IO1 ->
|
||||
|
||||
/* Port 27 */
|
||||
CFG_DISABLED, // FMI2_IO0 ->
|
||||
CFG_DISABLED, // FMI2_REN ->
|
||||
CFG_DISABLED, // FMI2_WEN ->
|
||||
CFG_DISABLED, // FMI2_ALE ->
|
||||
CFG_DISABLED, // FMI2_CLE ->
|
||||
CFG_DISABLED, // FMI2_CEN3 ->
|
||||
CFG_DISABLED, // FMI2_CEN2 ->
|
||||
CFG_DISABLED, // FMI2_CEN1 ->
|
||||
|
||||
/* Port 28 */
|
||||
CFG_DISABLED, // FMI2_CEN0 ->
|
||||
CFG_DISABLED, // FMI3_IO7 ->
|
||||
CFG_DISABLED, // FMI3_IO6 ->
|
||||
CFG_DISABLED, // FMI3_IO5 ->
|
||||
CFG_DISABLED, // FMI3_IO4 ->
|
||||
CFG_DISABLED, // FMI3_DQS ->
|
||||
CFG_DISABLED, // FMI3_IO3 ->
|
||||
CFG_DISABLED, // FMI3_IO2 ->
|
||||
|
||||
/* Port 29 */
|
||||
CFG_DISABLED, // FMI3_IO1 ->
|
||||
CFG_DISABLED, // FMI3_IO0 ->
|
||||
CFG_DISABLED, // FMI3_REN ->
|
||||
CFG_DISABLED, // FMI3_WEN ->
|
||||
CFG_DISABLED, // FMI3_ALE ->
|
||||
CFG_DISABLED, // FMI3_CLE ->
|
||||
CFG_DISABLED, // FMI3_CEN3 ->
|
||||
CFG_DISABLED, // FMI3_CEN2 ->
|
||||
|
||||
/* Port 30 */
|
||||
CFG_DISABLED, // FMI3_CEN1 ->
|
||||
CFG_DISABLED, // FMI3_CEN0 ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
CFG_DISABLED, // ->
|
||||
};
|
||||
|
||||
#endif /* ! __PLATFORM_PINCONFIG_H */
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_CHIPID_H
|
||||
#define __PLATFORM_SOC_CHIPID_H
|
||||
|
||||
#include <platform/chipid.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rCFG_FUSE0 (*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x00))
|
||||
#define rCFG_FUSE1 (*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x04))
|
||||
#define rCFG_FUSE2 (*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x08))
|
||||
#define rCFG_FUSE3 (*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x0C))
|
||||
#define rCFG_FUSE4 (*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x18))
|
||||
#define rCFG_FUSE5 (*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x1C))
|
||||
#define rCFG_FUSE6 (*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x20))
|
||||
#define rCFG_FUSE7 (*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x24))
|
||||
|
||||
#define rECIDLO (*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x10))
|
||||
#define rECIDHI (*(volatile u_int32_t *)(CHIPID_BASE_ADDR + 0x14))
|
||||
|
||||
extern bool chipid_get_ecid_image_personalization_required(void);
|
||||
|
||||
#define CHIPID_SOC_VOLTAGE_LOW (0)
|
||||
#define CHIPID_SOC_VOLTAGE_MED (1)
|
||||
#define CHIPID_SOC_VOLTAGE_HIGH (2)
|
||||
extern u_int32_t chipid_get_soc_voltage(u_int32_t index);
|
||||
|
||||
#define CHIPID_CPU_VOLTAGE_LOW (0)
|
||||
#define CHIPID_CPU_VOLTAGE_MED (1)
|
||||
#define CHIPID_CPU_VOLTAGE_HIGH (2)
|
||||
extern u_int32_t chipid_get_cpu_voltage(u_int32_t index);
|
||||
|
||||
extern u_int32_t chipid_get_fused_thermal_70C(void);
|
||||
extern u_int32_t chipid_get_fused_thermal_25C(void);
|
||||
extern u_int32_t chipid_get_fuse_revision(void);
|
||||
|
||||
#endif /* __PLATFORM_SOC_CHIPID_H */
|
||||
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_H
|
||||
#define __APPLE_DISPLAY_H
|
||||
|
||||
// Platform-specific displaypipe tunables
|
||||
static struct adfe_v1_tuneable adfe_tuneables[] =
|
||||
{
|
||||
{
|
||||
.name = "default",
|
||||
.disp_dpcclkcntl[0] = 0,
|
||||
.disp_dpbclklvl_clock_off_level[0] = DPBCLKLVL_OFFLVL(0x01f0),
|
||||
.disp_dpbclklvl_clock_on_level[0] = DPBCLKLVL_ONLVL(0x0180),
|
||||
.disp_dpusrcstrd[0] = DPUSRCSTRD_SRCBURST_4BLOCKS,
|
||||
.disp_dpcqoscnfg[0] = (DPCQOSCNFG_QOS_TIMER(0x0040) | \
|
||||
DPCQOSCNFG_QOS_ENABLE),
|
||||
.disp_dpbqoslvl_med_watermark[0] = DPBQOSLVL_MED_WATERMARK(0x0100),
|
||||
.disp_dpbqoslvl_high_watermark[0] = DPBQOSLVL_HIGH_WATERMARK(0x0000),
|
||||
.disp_dpureqcfg[0] = 0,
|
||||
|
||||
.disp_dpcclkcntl[1] = 0,
|
||||
.disp_dpbclklvl_clock_off_level[1] = DPBCLKLVL_OFFLVL(0x01f0),
|
||||
.disp_dpbclklvl_clock_on_level[1] = DPBCLKLVL_ONLVL(0x01c0),
|
||||
.disp_dpusrcstrd[1] = DPUSRCSTRD_SRCBURST_4BLOCKS,
|
||||
.disp_dpcqoscnfg[1] = (DPCQOSCNFG_QOS_TIMER(0x0040) | \
|
||||
DPCQOSCNFG_QOS_ENABLE),
|
||||
.disp_dpbqoslvl_med_watermark[1] = DPBQOSLVL_MED_WATERMARK(0x0100),
|
||||
.disp_dpbqoslvl_high_watermark[1] = DPBQOSLVL_HIGH_WATERMARK(0x0000),
|
||||
.disp_dpureqcfg[1] = 0,
|
||||
},
|
||||
};
|
||||
|
||||
#endif /* ! __APPLE_DISPLAY_H */
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_TIMINGS_H
|
||||
#define __APPLE_DISPLAY_TIMINGS_H
|
||||
|
||||
//Supported timings by this platform
|
||||
static struct display_timing timing_list[] =
|
||||
{
|
||||
#if DEBUG_BUILD || SUB_TARGET_J1 || SUB_TARGET_J2 || SUB_TARGET_J2A
|
||||
{
|
||||
.display_name = "ipad3",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 205200000,
|
||||
.dot_pitch = 264,
|
||||
.h_active = 2048,
|
||||
.h_back_porch = 80,
|
||||
.h_front_porch = 48,
|
||||
.h_pulse_width = 32,
|
||||
.v_active = 1536,
|
||||
.v_back_porch = 6,
|
||||
.v_front_porch = 3,
|
||||
.v_pulse_width = 4,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_EDP,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || WITH_HW_DISPLAY_HDMI
|
||||
{
|
||||
.display_name = "720p",
|
||||
.host_clock_id = CLK_VCLK1,
|
||||
.pixel_clock = 74250000,
|
||||
.dot_pitch = 243,
|
||||
.h_active = 1280,
|
||||
.h_pulse_width = 40,
|
||||
.h_back_porch = 110,
|
||||
.h_front_porch = 220,
|
||||
.v_active = 720,
|
||||
.v_pulse_width = 5,
|
||||
.v_back_porch = 5,
|
||||
.v_front_porch = 20,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_HDMI,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
#endif /* ! __APPLE_DISPLAY_TIMINGS_H */
|
||||
@@ -0,0 +1,123 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWCLOCKS_H
|
||||
#define __PLATFORM_SOC_HWCLOCKS_H
|
||||
|
||||
#include <platform/clocks.h>
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define OSC_FREQ (5000000UL)
|
||||
#else
|
||||
#define OSC_FREQ (24000000UL)
|
||||
#endif
|
||||
|
||||
#define CLK_FCLK (HWCLOCK_BASE+0)
|
||||
#define CLK_ACLK (HWCLOCK_BASE+1)
|
||||
#define CLK_HCLK (HWCLOCK_BASE+2)
|
||||
#define CLK_PCLK (HWCLOCK_BASE+3)
|
||||
#define CLK_VCLK0 (HWCLOCK_BASE+4)
|
||||
#define CLK_VCLK1 (HWCLOCK_BASE+5)
|
||||
#define CLK_MCLK (HWCLOCK_BASE+6)
|
||||
#define CLK_NCLK (HWCLOCK_BASE+7)
|
||||
#define CLK_USBPHYCLK (HWCLOCK_BASE+8)
|
||||
#define CLK_NCOREF (HWCLOCK_BASE+9)
|
||||
#define CLK_FMI (HWCLOCK_BASE+10)
|
||||
|
||||
/* S5L8945X clock gate devices */
|
||||
enum {
|
||||
CLK_CPU0 = 0,
|
||||
CLK_CPU1,
|
||||
CLK_SCU,
|
||||
CLK_L2RAM0,
|
||||
CLK_L2RAM1,
|
||||
CLK_CPU_REGS,
|
||||
CLK_MCU,
|
||||
CLK_GFX_SYS,
|
||||
CLK_GFX_CORES,
|
||||
CLK_HPERFNRT,
|
||||
CLK_VDEC,
|
||||
CLK_SCALER0,
|
||||
CLK_SCALER1,
|
||||
CLK_JPG0,
|
||||
CLK_JPG1,
|
||||
CLK_VENCD,
|
||||
CLK_HPERFRT,
|
||||
CLK_ISP,
|
||||
CLK_resv0,
|
||||
CLK_DISP0,
|
||||
CLK_DISP1,
|
||||
CLK_DISPOUT,
|
||||
CLK_EDPLINK,
|
||||
CLK_CLCD,
|
||||
CLK_TVDAC,
|
||||
CLK_RGBOUT,
|
||||
CLK_DPLINK,
|
||||
CLK_CDIO,
|
||||
CLK_CDMA,
|
||||
CLK_IOP,
|
||||
CLK_UPERF,
|
||||
CLK_UPERF1,
|
||||
CLK_USBOTG,
|
||||
CLK_USB20,
|
||||
CLK_USB11,
|
||||
CLK_USBOHCI0,
|
||||
CLK_USBOHCI1,
|
||||
CLK_USBPHY,
|
||||
CLK_USB1_OTG,
|
||||
CLK_USB1_20,
|
||||
CLK_USB1_11,
|
||||
CLK_USB1_OHCI0,
|
||||
CLK_USB1_OHCI1,
|
||||
CLK_USB1_PHY,
|
||||
CLK_AUDIO,
|
||||
CLK_I2S0,
|
||||
CLK_I2S1,
|
||||
CLK_I2S2,
|
||||
CLK_I2S3,
|
||||
CLK_SPDIF,
|
||||
CLK_HPARK,
|
||||
CLK_SDIO,
|
||||
CLK_SHA1,
|
||||
CLK_SHA2,
|
||||
CLK_FMI0,
|
||||
CLK_FMI0BCH,
|
||||
CLK_FMI1,
|
||||
CLK_FMI1BCH,
|
||||
CLK_FMI2,
|
||||
CLK_FMI2BCH,
|
||||
CLK_FMI3,
|
||||
CLK_FMI3BCH,
|
||||
CLK_SPI0,
|
||||
CLK_SPI1,
|
||||
CLK_SPI2,
|
||||
CLK_SPI3,
|
||||
CLK_SPI4,
|
||||
CLK_UART0,
|
||||
CLK_UART1,
|
||||
CLK_UART2,
|
||||
CLK_UART3,
|
||||
CLK_UART4,
|
||||
CLK_UART5,
|
||||
CLK_UART6,
|
||||
CLK_PKE,
|
||||
CLK_I2C0,
|
||||
CLK_I2C1,
|
||||
CLK_I2C2,
|
||||
CLK_PWM,
|
||||
CLK_SCRT,
|
||||
CLK_GPIO,
|
||||
CLK_SWI,
|
||||
CLK_DWI,
|
||||
CLK_DEBUG,
|
||||
CLK_AIC,
|
||||
};
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWCLOCKS_H */
|
||||
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWDMACHANNELS_H
|
||||
#define __PLATFORM_SOC_HWDMACHANNELS_H
|
||||
|
||||
#define DMA_MEMORY_TX (1)
|
||||
#define DMA_MEMORY_RX (2)
|
||||
#define DMA_SDIO (3)
|
||||
#define DMA_FMI0DATA (5)
|
||||
#define DMA_FMI0CHECK (6)
|
||||
#define DMA_FMI1DATA (7)
|
||||
#define DMA_FMI1CHECK (8)
|
||||
#define DMA_FMI2DATA (9)
|
||||
#define DMA_FMI2CHECK (10)
|
||||
#define DMA_FMI3DATA (11)
|
||||
#define DMA_FMI3CHECK (12)
|
||||
|
||||
#define DMA_CHANNEL_COUNT (44)
|
||||
|
||||
#define DMA_CHANNEL_CONFIG \
|
||||
{ \
|
||||
/* low high AES OK reqID FIFO address */ \
|
||||
{ 3, 4, false, 0x00, 0x30000020 }, \
|
||||
{ 3, 4, false, 0x01, 0x301000A0 }, \
|
||||
{ 3, 4, false, 0x01, 0x30200020 }, \
|
||||
{ 5, 12, true, 0x00, 0x31200014 }, \
|
||||
{ 5, 12, true, 0x01, 0x31200018 }, \
|
||||
{ 5, 12, true, 0x02, 0x31300014 }, \
|
||||
{ 5, 12, true, 0x03, 0x31300018 }, \
|
||||
{ 5, 12, true, 0x04, 0x31400014 }, \
|
||||
{ 5, 12, true, 0x05, 0x31400018 }, \
|
||||
{ 5, 12, true, 0x06, 0x31500014 }, \
|
||||
{ 5, 12, true, 0x07, 0x31500018 }, \
|
||||
}
|
||||
|
||||
|
||||
#define DMA_SDIO_TIMEOUT_US (10 * 1000)
|
||||
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWDMACHANNELS_H */
|
||||
@@ -0,0 +1,196 @@
|
||||
/*
|
||||
* Copyright (C) 22010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWISR_H
|
||||
#define __PLATFORM_SOC_HWISR_H
|
||||
|
||||
#define INT_SW0 0 // Software 0 Interrupt
|
||||
#define INT_SW1 1 // Software 1 Interrupt
|
||||
#define INT_SW2 2 // Software 2 Interrupt
|
||||
#define INT_SW3 3 // Software 3 Interrupt
|
||||
#define INT_WDT 4 // Watchdog Timer Interrupt
|
||||
#define INT_SWI 5 // SWI Interrupt
|
||||
#define INT_DWI 6 // DWI Interrupt
|
||||
#define INT_ISP0 7 // ISP 0 Interrupt
|
||||
#define INT_ISP1 8 // ISP 1 Interrupt
|
||||
#define INT_SCALER0 9 // Scaler Interrupt
|
||||
#define INT_SCALER1 10 // Scaler Interrupt
|
||||
#define INT_USB_OTG 11 // USB OTG Interrupt
|
||||
#define INT_USB_EHCI 12 // USB EHCI Interrupt
|
||||
#define INT_USB_OHCI0 13 // USB OHCI 0 Interrupt
|
||||
#define INT_USB_OHCI1 14 // USB OHCI 1 Interrupt
|
||||
#define INT_USB_RES 15 // USB PHY Interrupt
|
||||
#define INT_PWM 16 // PWM Interrupt
|
||||
#define INT_PKE 17 // PKE Interrupt
|
||||
#define INT_IIC0 18 // I2C 0 Interrupt
|
||||
#define INT_IIC1 19 // I2C 1 Interrupt
|
||||
#define INT_IIC2 20 // I2C 2 Interrupt
|
||||
#define INT_UART0 21 // UART 0 Interrupt
|
||||
#define INT_UART1 22 // UART 1 Interrupt
|
||||
#define INT_UART2 23 // UART 2 Interrupt
|
||||
#define INT_UART3 24 // UART 3 Interrupt
|
||||
#define INT_UART4 25 // UART 4 Interrupt
|
||||
#define INT_UART5 26 // UART 5 Interrupt
|
||||
#define INT_UART6 27 // UART 6 Interrupt
|
||||
#define INT_SPI0 28 // SPI 0 Interrupt
|
||||
#define INT_SPI1 29 // SPI 1 Interrupt
|
||||
#define INT_SPI2 30 // SPI 2 Interrupt
|
||||
#define INT_SPI3 31 // SPI 3 Interrupt
|
||||
#define INT_SPI4 32 // SPI 4 Interrupt
|
||||
#define INT_FMI0 33 // FMI 0 Interrupt
|
||||
#define INT_FMI1 34 // FMI 1 Interrupt
|
||||
#define INT_FMI2 35 // FMI 2 Interrupt
|
||||
#define INT_FMI3 36 // FMI 3 Interrupt
|
||||
#define INT_SHA1 37 // SHA-1 Interrupt
|
||||
#define INT_SHA2 38 // SHA-1 Interrupt
|
||||
#define INT_WIFI 39 // WiFi Interrupt
|
||||
#define INT_TVOUT 40 // TV Out Interrupt
|
||||
// Reserved 41
|
||||
#define INT_CLCD 42 // CLCD Interrupt
|
||||
#define INT_DISP0 43 // Display Pipe 0 Interrupt
|
||||
#define INT_DISP1 44 // Display Pipe 1 Interrupt
|
||||
#define INT_RGBOUT 45 // RGB Out Interrupt
|
||||
#define INT_DPORT0 46 // DisplayPort 0 Interrupt
|
||||
#define INT_DPORT1 47 // DisplayPort 1 Interrupt
|
||||
#define INT_VENC 48 // Video Encoder Interrupt
|
||||
#define INT_SGX 49 // SGX Interrupt
|
||||
#define INT_VDEC 50 // Video Decoder Interrupt
|
||||
#define INT_CDMA_DMAC1 51 // CDMA DMA Channel 1 Interrupt
|
||||
#define INT_CDMA_DMAC2 52 // CDMA DMA Channel 2 Interrupt
|
||||
#define INT_CDMA_DMAC3 53 // CDMA DMA Channel 3 Interrupt
|
||||
#define INT_CDMA_DMAC4 54 // CDMA DMA Channel 4 Interrupt
|
||||
#define INT_CDMA_DMAC5 55 // CDMA DMA Channel 5 Interrupt
|
||||
#define INT_CDMA_DMAC6 56 // CDMA DMA Channel 6 Interrupt
|
||||
#define INT_CDMA_DMAC7 57 // CDMA DMA Channel 7 Interrupt
|
||||
#define INT_CDMA_DMAC8 58 // CDMA DMA Channel 8 Interrupt
|
||||
#define INT_CDMA_DMAC9 59 // CDMA DMA Channel 9 Interrupt
|
||||
#define INT_CDMA_DMAC10 60 // CDMA DMA Channel 10 Interrupt
|
||||
#define INT_CDMA_DMAC11 61 // CDMA DMA Channel 11 Interrupt
|
||||
#define INT_CDMA_DMAC12 62 // CDMA DMA Channel 12 Interrupt
|
||||
#define INT_CDMA_DMAC13 63 // CDMA DMA Channel 13 Interrupt
|
||||
#define INT_CDMA_DMAC14 64 // CDMA DMA Channel 14 Interrupt
|
||||
#define INT_CDMA_DMAC15 65 // CDMA DMA Channel 15 Interrupt
|
||||
#define INT_CDMA_DMAC16 66 // CDMA DMA Channel 16 Interrupt
|
||||
#define INT_CDMA_DMAC17 67 // CDMA DMA Channel 17 Interrupt
|
||||
#define INT_CDMA_DMAC18 68 // CDMA DMA Channel 18 Interrupt
|
||||
#define INT_CDMA_DMAC19 69 // CDMA DMA Channel 19 Interrupt
|
||||
#define INT_CDMA_DMAC20 70 // CDMA DMA Channel 20 Interrupt
|
||||
#define INT_CDMA_DMAC21 71 // CDMA DMA Channel 21 Interrupt
|
||||
#define INT_CDMA_DMAC22 72 // CDMA DMA Channel 22 Interrupt
|
||||
#define INT_CDMA_DMAC23 73 // CDMA DMA Channel 23 Interrupt
|
||||
#define INT_CDMA_DMAC24 74 // CDMA DMA Channel 24 Interrupt
|
||||
#define INT_CDMA_DMAC25 75 // CDMA DMA Channel 25 Interrupt
|
||||
#define INT_CDMA_DMAC26 76 // CDMA DMA Channel 26 Interrupt
|
||||
#define INT_CDMA_DMAC27 77 // CDMA DMA Channel 27 Interrupt
|
||||
#define INT_CDMA_DMAC28 78 // CDMA DMA Channel 28 Interrupt
|
||||
#define INT_CDMA_DMAC29 79 // CDMA DMA Channel 29 Interrupt
|
||||
#define INT_CDMA_DMAC30 80 // CDMA DMA Channel 30 Interrupt
|
||||
#define INT_CDMA_DMAC31 81 // CDMA DMA Channel 31 Interrupt
|
||||
#define INT_CDMA_DMAC32 82 // CDMA DMA Channel 32 Interrupt
|
||||
#define INT_CDMA_DMAC33 83 // CDMA DMA Channel 33 Interrupt
|
||||
#define INT_CDMA_DMAC34 84 // CDMA DMA Channel 34 Interrupt
|
||||
#define INT_CDMA_DMAC35 85 // CDMA DMA Channel 35 Interrupt
|
||||
#define INT_CDMA_DMAC36 86 // CDMA DMA Channel 36 Interrupt
|
||||
#define INT_CDMA_DMAC37 87 // CDMA DMA Channel 37 Interrupt
|
||||
#define INT_CDMA_DMAC38 88 // CDMA DMA Channel 38 Interrupt
|
||||
#define INT_CDMA_DMAC39 89 // CDMA DMA Channel 39 Interrupt
|
||||
#define INT_CDMA_DMAC40 90 // CDMA DMA Channel 40 Interrupt
|
||||
#define INT_CDMA_DMAC41 91 // CDMA DMA Channel 41 Interrupt
|
||||
#define INT_CDMA_DMAC42 92 // CDMA DMA Channel 42 Interrupt
|
||||
#define INT_CDMA_DMAC43 93 // CDMA DMA Channel 43 Interrupt
|
||||
#define INT_CDMA_DMAC44 94 // CDMA DMA Channel 44 Interrupt
|
||||
|
||||
// Reserved 95 - 96
|
||||
|
||||
// Audio and Highland Park Interrupts 97 - 115
|
||||
|
||||
#define INT_AUDIO_CPU_IRQ0 97 //
|
||||
#define INT_AUDIO_CPU_IRQ1 98 //
|
||||
|
||||
#define INT_HPERFNRT_DART 116 // HPerf-NRT DART Interrupt
|
||||
#define INT_HPERFRT_DART 117 // HPerf-RT DART Interrupt
|
||||
#define INT_JPG 118 // JPEG Interrupt
|
||||
#define INT_GPIO0 119 // GPIO 0 Interrupt
|
||||
#define INT_GPIO1 120 // GPIO 1 Interrupt
|
||||
#define INT_MCU 121 // MCU 0 Interrupt
|
||||
#define INT_MCU0 122 // MCU 0 Interrupt
|
||||
#define INT_MCU1 123 // MCU 1 Interrupt
|
||||
#define INT_PIO0 124 // PIO 0 Interrupt
|
||||
#define INT_PIO1 125 // PIO 1 Interrupt
|
||||
|
||||
// Reserved 126
|
||||
|
||||
#define INT_IOP_COMMRX 127 // IOP CommRx Interrupt
|
||||
#define INT_IOP_COMMTX 128 // IOP CommTx Interrupt
|
||||
#define INT_IOP_PMI 129 // IOP PerfMon Interrupt
|
||||
#define INT_IOP_CTIIRQ 130 // IOP CTIIRQ Interrupt
|
||||
#define INT_ISP_COMMRX 131 // IOP CommRx Interrupt
|
||||
#define INT_ISP_COMMTX 132 // IOP CommTx Interrupt
|
||||
#define INT_ISP_PMI 133 // IOP PerfMon Interrupt
|
||||
#define INT_ISP_CTIIRQ 134 // IOP CTIIRQ Interrupt
|
||||
|
||||
#define INT_CPU0_PMI 135 // IOP Perfmon Interrupt
|
||||
#define INT_CPU0_CTIIRQ 136 // IOP CTI Interrupt
|
||||
#define INT_CPU0_COMMRX 137 // IOP CommRx Interrupt
|
||||
#define INT_CPU0_COMMTX 138 // IOP CommTx Interrupt
|
||||
#define INT_CPU1_PMI 139 // IOP PMI Interrupt
|
||||
#define INT_CPU1_CTIIRQ 140 // IOP CTI Interrupt
|
||||
#define INT_CPU1_COMMRX 141 // IOP CommRx Interrupt
|
||||
#define INT_CPU1_COMMTX 142 // IOP CommTx Interrupt
|
||||
|
||||
#define INT_L2C 143 // PL310 Interrupt
|
||||
|
||||
// Reserved 144 - 151
|
||||
|
||||
#define INT_PMGR_PMI 152 // PMGR PerfMon Interrupt
|
||||
#define INT_HPERFNTR_PMI 153 // HPerf-NRT PerfMon Interrupt
|
||||
#define INT_HPERFRT_PMI 154 // HPerf-RT PerfMon Interrupt
|
||||
#define INT_DPIPE0_PMI 155 // Display Pipe 0 PerfMon Interrupt
|
||||
#define INT_DPIPE1_PMI 156 // Display Pipe 1 PerfMon Interrupt
|
||||
|
||||
// Reserved 157 - 159
|
||||
|
||||
#define INT_ETB_FULL 160 // ETB Full Interrupt
|
||||
|
||||
#define INT_USB1_OTG 161 // USB1 OTG Interrupt
|
||||
#define INT_USB1_EHCI 162 // USB1 EHCI Interrupt
|
||||
#define INT_USB1_OHCI0 163 // USB1 OHCI 0 Interrupt
|
||||
#define INT_USB1_OHCI1 164 // USB1 OHCI 1 Interrupt
|
||||
#define INT_USB1_RES 165 // USB1 PHY Interrupt
|
||||
#define INT_JPG1 166 // JPEG1 Interrupt
|
||||
#define INT_EDP0 167 // EDisplayPort 0 Interrupt
|
||||
#define INT_EDP1 168 // EDisplayPort 1 Interrupt
|
||||
#define INT_AES 169 // AES Interrupt
|
||||
#define INT_THERMAL_TEMP 170 // Thermal Temp Interrupt
|
||||
#define INT_THERMAL_ALARM 171 // Thermal Alarm Interrupt
|
||||
#define INT_MCU2 172 // MCU Channel 2 Interrupt
|
||||
#define INT_MCU3 173 // MCU Channel 3 Interrupt
|
||||
|
||||
// Reserved 174 - 191
|
||||
|
||||
#if PLATFORM_VARIANT_IOP
|
||||
|
||||
#include <drivers/aic/aic.h>
|
||||
|
||||
#define INT_HOST INT_SW2 // Host processor doorbell
|
||||
#define INT_IOP INT_SW3 // I/O coprocessor doorbell
|
||||
#define INT_IOP_NMI kAIC_VEC_SW_TMR // I/O coprocessor NMI
|
||||
|
||||
#elif PLATFORM_VARIANT_AUDIO
|
||||
|
||||
#include <drivers/audio/audio.h>
|
||||
|
||||
#define INT_HOST AE2_INT_SW0 // Host processor doorbell
|
||||
#define INT_IOP AE2_INT_SW0 // I/O coprocessor doorbell
|
||||
#define INT_IOP_NMI AE2_INT_SW1 // I/O coprocessor NMI
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWISR_H */
|
||||
@@ -0,0 +1,146 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWREGBASE_H
|
||||
#define __PLATFORM_SOC_HWREGBASE_H
|
||||
|
||||
/* S5L8940X Reg Base Defs */
|
||||
|
||||
#define AIC_VERSION 0
|
||||
#define AIC_INT_COUNT (192)
|
||||
#define PMGR_WDG_VERSION 0
|
||||
|
||||
#define SDIO_BASE_ADDR (0x30000000)
|
||||
|
||||
#define SHA1_BASE_ADDR (0x30100000)
|
||||
#define SHA2_BASE_ADDR (0x30200000)
|
||||
|
||||
#define FMI0_BASE_ADDR (0x31200000)
|
||||
#define FMI1_BASE_ADDR (0x31300000)
|
||||
#define FMI2_BASE_ADDR (0x31400000)
|
||||
#define FMI3_BASE_ADDR (0x31500000)
|
||||
#define FMI_VERSION (4)
|
||||
|
||||
#define SPI0_BASE_ADDR (0x32000000)
|
||||
#define SPI1_BASE_ADDR (0x32100000)
|
||||
#define SPI2_BASE_ADDR (0x32200000)
|
||||
#define SPI3_BASE_ADDR (0x32300000)
|
||||
#define SPI4_BASE_ADDR (0x32400000)
|
||||
#define SPI_VERSION (1)
|
||||
#define SPIS_COUNT (5)
|
||||
|
||||
#define UART0_BASE_ADDR (0x32500000)
|
||||
#define UART1_BASE_ADDR (0x32600000)
|
||||
#define UART2_BASE_ADDR (0x32700000)
|
||||
#define UART3_BASE_ADDR (0x32800000)
|
||||
#define UART4_BASE_ADDR (0x32900000)
|
||||
#define UART5_BASE_ADDR (0x32A00000)
|
||||
#define UART6_BASE_ADDR (0x32B00000)
|
||||
#define UART_VERSION (1)
|
||||
#define UARTS_COUNT (7)
|
||||
|
||||
#define PKE_BASE_ADDR (0x33100000)
|
||||
|
||||
#define IIC_BASE_ADDR (0x33200000)
|
||||
#define IIC_SPACING (0x00100000)
|
||||
#define IICS_COUNT (3)
|
||||
|
||||
#define AUDIO_BASE_ADDR (0x34000000)
|
||||
|
||||
#define USBPHY_BASE_ADDR (0x36000000)
|
||||
#define USBPHY_VERSION (3)
|
||||
#define USBOTG_BASE_ADDR (0x36100000)
|
||||
#define UPERF_WIDGETS_BASE_ADDR (0x36200000)
|
||||
#define UPERF_PL301_BASE_ADDR (0x36300000)
|
||||
#define UPERF1_WIDGETS_BASE_ADDR (0x36A00000)
|
||||
#define UPERF1_PL301_BASE_ADDR (0x36B00000)
|
||||
|
||||
#define CDMA_BASE_ADDR (0x37000000)
|
||||
#define CDMA_VERSION 4
|
||||
|
||||
#define VENC_BASE_ADDR (0x38000000)
|
||||
|
||||
#define VDEC_BASE_ADDR (0x38100000)
|
||||
|
||||
#define JPEG_BASE_ADDR (0x38200000)
|
||||
|
||||
#define SCALER_BASE_ADDR (0x38300000)
|
||||
#define SCALER_SPACING (0x00100000)
|
||||
|
||||
#define NRT_DART_BASE_ADDR (0x38B00000)
|
||||
#define NRT_DART_WIDGETS_BASE_ADDR (0x38C00000)
|
||||
#define NRT_DART_PL301_BASE_ADDR (0x38D00000)
|
||||
#define NRT_TOP_WIDGETS_BASE_ADDR (0x38E00000)
|
||||
#define NRT_TOP_PL301_BASE_ADDR (0x38F00000)
|
||||
|
||||
#define CLCD_BASE_ADDR (0x39200000)
|
||||
#define CLCD_VERSION (0)
|
||||
#define CLCD_DITHER_BASE_ADDR (0x39300000)
|
||||
#define DITHER_VERSION (1)
|
||||
|
||||
#define TVOUT_BASE_ADDR (0x39400000)
|
||||
|
||||
#define RGBOUT_BASE_ADDR (0x39600000)
|
||||
#define RGBOUT_DITHER_BASE_ADDR (0x39800000)
|
||||
|
||||
#define EDP_BASE_ADDR (0x39500000)
|
||||
#define DP_BASE_ADDR (0x39700000)
|
||||
#define DISPLAYPORT_VERSION (2)
|
||||
|
||||
#define ISP_BASE_ADDR (0x3A000000)
|
||||
|
||||
#define DISP0_BASE_ADDR (0x3A100000)
|
||||
#define DISP1_BASE_ADDR (0x3A200000)
|
||||
#define CLCD_DISPLAYPIPE_BASE_ADDR (DISP0_BASE_ADDR)
|
||||
#define RGBOUT_DISPLAYPIPE_BASE_ADDR (DISP1_BASE_ADDR)
|
||||
#define DISP_VERSION (4)
|
||||
|
||||
#define RT_DART_BASE_ADDR (0x3A400000)
|
||||
#define RT_TOP_WIDGETS_BASE_ADDR (0x3A500000)
|
||||
#define RT_TOP_PL301_BASE_ADDR (0x3A600000)
|
||||
|
||||
#define HP_BASE_ADDR (0x3B000000)
|
||||
|
||||
#define AMG_BASE_ADDR (0x3D000000)
|
||||
#define AMG_SPACING (0x00100000)
|
||||
|
||||
#define PL310_BASE_ADDR (0x3E000000)
|
||||
#define SCU_BASE_ADDR (0x3E100000)
|
||||
|
||||
#define PMGR_BASE_ADDR (0x3F100000)
|
||||
#define AIC_BASE_ADDR (0x3F200000)
|
||||
|
||||
#define IOP_BASE_ADDR (0x3F300000)
|
||||
|
||||
#define ROSC_BASE_ADDR (0x3F400000)
|
||||
#define ROSC_MASK (0x57FF)
|
||||
#define ROSC_WITH_CLOCK (0)
|
||||
|
||||
#define CHIPID_BASE_ADDR (0x3F500000)
|
||||
|
||||
#define SWI_BASE_ADDR (0x3F600000)
|
||||
#define DWI_BASE_ADDR (0x3F700000)
|
||||
|
||||
#define AMC_BASE_ADDR (0x3F800000)
|
||||
|
||||
#define GPIO_BASE_ADDR (0x3FA00000)
|
||||
#define GPIO_VERSION (1)
|
||||
#define GPIO_GROUP_COUNT (31)
|
||||
#define GPIO_PAD_SPI (GPIO_GROUP_COUNT)
|
||||
|
||||
#define PIO_BASE_ADDR (0x3FB00000)
|
||||
#define PIO_SPACING (0x00100000)
|
||||
|
||||
#define CIF_BASE_ADDR (0x3FD00000)
|
||||
|
||||
#define CDIO_WIDGETS_BASE_ADDR (0x3FE00000)
|
||||
#define CDIO_PL301_BASE_ADDR (0x3FF00000)
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWREGBASE_H */
|
||||
@@ -0,0 +1,186 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_MIU_H
|
||||
#define __PLATFORM_SOC_MIU_H
|
||||
|
||||
#include <lib/devicetree.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rREMAP_CTL (*(volatile u_int32_t *)(PIO_BASE_ADDR + 0x0000))
|
||||
|
||||
#define rPL310_CONTROL (*(volatile u_int32_t *)(PL310_BASE_ADDR + 0x0100))
|
||||
#define rPL310_INVAL_WAY (*(volatile u_int32_t *)(PL310_BASE_ADDR + 0x077C))
|
||||
#define rPL310_FILTER_START (*(volatile u_int32_t *)(PL310_BASE_ADDR + 0x0C00))
|
||||
#define rPL310_FILTER_END (*(volatile u_int32_t *)(PL310_BASE_ADDR + 0x0C04))
|
||||
|
||||
#define rSCU_CONTROL (*(volatile u_int32_t *)(SCU_BASE_ADDR + 0x0000))
|
||||
#define rSCU_POWER_STATUS (*(volatile u_int32_t *)(SCU_BASE_ADDR + 0x0008))
|
||||
#define rSCU_TAG_INVAL (*(volatile u_int32_t *)(SCU_BASE_ADDR + 0x000C))
|
||||
|
||||
#define rCIF_CONTROL (*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0000))
|
||||
#define rCIF_CLKGATE (*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0004))
|
||||
#define rCIF_RTLIMIT (*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0008))
|
||||
#define rCIF_WTLIMIT (*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x000C))
|
||||
#define rCIF_IDLETMR (*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0010))
|
||||
#define rCIF_RDREMAP (*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0040))
|
||||
#define rCIF_WRREMAP (*(volatile u_int32_t *)(CIF_BASE_ADDR + 0x0044))
|
||||
|
||||
#define CDIO_IOP_RTLIMIT (0x0008)
|
||||
#define rCDIO_IOP_RTLIMIT (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_RTLIMIT))
|
||||
#define CDIO_IOP_WTLIMIT (0x000C)
|
||||
#define rCDIO_IOP_WTLIMIT (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_WTLIMIT))
|
||||
#define CDIO_IOP_WREQSP (0x001C)
|
||||
#define rCDIO_IOP_WREQSP (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_IOP_WREQSP))
|
||||
#define CDIO_CDMA_RTLIMIT (0x0028)
|
||||
#define rCDIO_CDMA_RTLIMIT (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_CDMA_RTLIMIT))
|
||||
#define CDIO_CDMA_WTLIMIT (0x002C)
|
||||
#define rCDIO_CDMA_WTLIMIT (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_CDMA_WTLIMIT))
|
||||
#define CDIO_CDMA_WGATHER (0x0030)
|
||||
#define rCDIO_CDMA_WGATHER (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_CDMA_WGATHER))
|
||||
#define CDIO_UPERF_RTLIMIT (0x0048)
|
||||
#define rCDIO_UPERF_RTLIMIT (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPERF_RTLIMIT))
|
||||
#define CDIO_UPERF_WTLIMIT (0x004C)
|
||||
#define rCDIO_UPERF_WTLIMIT (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPERF_WTLIMIT))
|
||||
#define CDIO_UPERF_WGATHER (0x0050)
|
||||
#define rCDIO_UPERF_WGATHER (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPERF_WGATHER))
|
||||
#define CDIO_AUDIO_RTLIMIT (0x0068)
|
||||
#define rCDIO_AUDIO_RTLIMIT (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_AUDIO_RTLIMIT))
|
||||
#define CDIO_AUDIO_WTLIMIT (0x006C)
|
||||
#define rCDIO_AUDIO_WTLIMIT (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_AUDIO_WTLIMIT))
|
||||
#define CDIO_AUDIO_WGATHER (0x0070)
|
||||
#define rCDIO_AUDIO_WGATHER (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_AUDIO_WGATHER))
|
||||
#define CDIO_PIO_RTLIMIT (0x00A8)
|
||||
#define rCDIO_PIO_RTLIMIT (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_PIO_RTLIMIT))
|
||||
#define CDIO_PIO_WTLIMIT (0x00AC)
|
||||
#define rCDIO_PIO_WTLIMIT (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_PIO_WTLIMIT))
|
||||
#define CDIO_UPERF1_RTLIMIT (0x00C8)
|
||||
#define rCDIO_UPERF1_RTLIMIT (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPERF1_RTLIMIT))
|
||||
#define CDIO_UPERF1_WTLIMIT (0x00CC)
|
||||
#define rCDIO_UPERF1_WTLIMIT (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPER1F_WTLIMIT))
|
||||
#define CDIO_UPERF1_WGATHER (0x00D0)
|
||||
#define rCDIO_UPERF1_WGATHER (*(volatile u_int32_t *)(CDIO_WIDGETS_BASE_ADDR + CDIO_UPERF1_WGATHER))
|
||||
|
||||
#define CDIO_AR_CHAN_ARB_MI0 (0x0408)
|
||||
#define rCDIO_AR_CHAN_ARB_MI0 (*(volatile u_int32_t *)(CDIO_PL301_BASE_ADDR + CDIO_AR_CHAN_ARB_MI0))
|
||||
#define CDIO_AW_CHAN_ARB_MI0 (0x040C)
|
||||
#define rCDIO_AW_CHAN_ARB_MI0 (*(volatile u_int32_t *)(CDIO_PL301_BASE_ADDR + CDIO_AW_CHAN_ARB_MI0))
|
||||
#define CDIO_AR_CHAN_ARB_MI1 (0x0428)
|
||||
#define rCDIO_AR_CHAN_ARB_MI1 (*(volatile u_int32_t *)(CDIO_PL301_BASE_ADDR + CDIO_AR_CHAN_ARB_MI1))
|
||||
#define CDIO_AW_CHAN_ARB_MI1 (0x042C)
|
||||
#define rCDIO_AW_CHAN_ARB_MI1 (*(volatile u_int32_t *)(CDIO_PL301_BASE_ADDR + CDIO_AW_CHAN_ARB_MI1))
|
||||
|
||||
#define UPERF_OTG_QOS (0x0014)
|
||||
#define rUPERF_OTG_QOS (*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OTG_QOS))
|
||||
#define UPERF_OTG_CACHE (0x0018)
|
||||
#define rUPERF_OTG_CACHE (*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OTG_CACHE))
|
||||
#define UPERF_EHCI_QOS (0x0034)
|
||||
#define rUPERF_EHCI_QOS (*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_EHCI_QOS))
|
||||
#define UPERF_EHCI_CACHE (0x0038)
|
||||
#define rUPERF_EHCI_CACHE (*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_EHCI_CACHE))
|
||||
#define UPERF_OHCI0_QOS (0x0054)
|
||||
#define rUPERF_OHCI0_QOS (*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OHCI0_QOS))
|
||||
#define UPERF_OHCI0_CACHE (0x0058)
|
||||
#define rUPERF_OHCI0_CACHE (*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OHCI0_CACHE))
|
||||
#define UPERF_OHCI1_QOS (0x0074)
|
||||
#define rUPERF_OHCI1_QOS (*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OHCI1_QOS))
|
||||
#define UPERF_OHCI1_CACHE (0x0078)
|
||||
#define rUPERF_OHCI1_CACHE (*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_OHCI1_CACHE))
|
||||
#define UPERF_RTLIMIT (0x0088)
|
||||
#define rUPERF_RTLIMIT (*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_RTLIMIT))
|
||||
#define UPERF_WTLIMIT (0x008C)
|
||||
#define rUPERF_WTLIMIT (*(volatile u_int32_t *)(UPERF_WIDGETS_BASE_ADDR + UPERF_WTLIMIT))
|
||||
|
||||
#define rUPERF1_OTG_QOS (*(volatile u_int32_t *)(UPERF1_WIDGETS_BASE_ADDR + UPERF_OTG_QOS))
|
||||
#define rUPERF1_OTG_CACHE (*(volatile u_int32_t *)(UPERF1_WIDGETS_BASE_ADDR + UPERF_OTG_CACHE))
|
||||
#define rUPERF1_EHCI_QOS (*(volatile u_int32_t *)(UPERF1_WIDGETS_BASE_ADDR + UPERF_EHCI_QOS))
|
||||
#define rUPERF1_EHCI_CACHE (*(volatile u_int32_t *)(UPERF1_WIDGETS_BASE_ADDR + UPERF_EHCI_CACHE))
|
||||
#define rUPERF1_OHCI0_QOS (*(volatile u_int32_t *)(UPERF1_WIDGETS_BASE_ADDR + UPERF_OHCI0_QOS))
|
||||
#define rUPERF1_OHCI0_CACHE (*(volatile u_int32_t *)(UPERF1_WIDGETS_BASE_ADDR + UPERF_OHCI0_CACHE))
|
||||
#define rUPERF1_OHCI1_QOS (*(volatile u_int32_t *)(UPERF1_WIDGETS_BASE_ADDR + UPERF_OHCI1_QOS))
|
||||
#define rUPERF1_OHCI1_CACHE (*(volatile u_int32_t *)(UPERF1_WIDGETS_BASE_ADDR + UPERF_OHCI1_CACHE))
|
||||
#define rUPERF1_RTLIMIT (*(volatile u_int32_t *)(UPERF1_WIDGETS_BASE_ADDR + UPERF_RTLIMIT))
|
||||
#define rUPERF1_WTLIMIT (*(volatile u_int32_t *)(UPERF1_WIDGETS_BASE_ADDR + UPERF_WTLIMIT))
|
||||
|
||||
#define HPERF_NRT_DART_DART_RTLIMIT (0x0004)
|
||||
#define rHPERF_NRT_DART_DART_RTLIMIT (*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_DART_RTLIMIT))
|
||||
#define HPERF_NRT_DART_DART_WTLIMIT (0x0008)
|
||||
#define rHPERF_NRT_DART_DART_WTLIMIT (*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_DART_WTLIMIT))
|
||||
#define HPERF_NRT_DART_JPEG0_QOS (0x000C)
|
||||
#define rHPERF_NRT_DART_JPEG0_QOS (*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_JPEG0_QOS))
|
||||
#define HPERF_NRT_DART_JPEG1_QOS (0x0010)
|
||||
#define rHPERF_NRT_DART_JPEG1_QOS (*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_JPEG1_QOS))
|
||||
#define HPERF_NRT_DART_SCALER0_RTLIMIT (0x001C)
|
||||
#define rHPERF_NRT_DART_SCALER0_RTLIMIT (*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_SCALER0_RTLIMIT))
|
||||
#define HPERF_NRT_DART_SCALER0_WTLIMIT (0x0020)
|
||||
#define rHPERF_NRT_DART_SCALER0_WTLIMIT (*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_SCALER0_WTLIMIT))
|
||||
#define HPERF_NRT_DART_SCALER1_RTLIMIT (0x0030)
|
||||
#define rHPERF_NRT_DART_SCALER1_RTLIMIT (*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_SCALER1_RTLIMIT))
|
||||
#define HPERF_NRT_DART_SCALER1_WTLIMIT (0x0034)
|
||||
#define rHPERF_NRT_DART_SCALER1_WTLIMIT (*(volatile u_int32_t *)(NRT_DART_WIDGETS_BASE_ADDR + HPERF_NRT_DART_SCALER1_WTLIMIT))
|
||||
|
||||
#define HPERF_NRT_DART_AR_CHAN_ARB_MI (0x0408)
|
||||
#define rHPERF_NRT_DART_AR_CHAN_ARB_MI (*(volatile u_int32_t *)(NRT_DART_PL301_BASE_ADDR + HPERF_NRT_DART_AR_CHAN_ARB_MI0))
|
||||
#define HPERF_NRT_DART_AW_CHAN_ARB_MI (0x040C)
|
||||
#define rHPERF_NRT_DART_AW_CHAN_ARB_MI (*(volatile u_int32_t *)(NRT_DART_PL301_BASE_ADDR + HPERF_NRT_DART_AW_CHAN_ARB_MI0))
|
||||
|
||||
#define HPERF_NRT_TOP_TOP_RTLIMIT (0x0000)
|
||||
#define rHPERF_NRT_TOP_TOP_RTLIMIT (*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_TOP_RTLIMIT))
|
||||
#define HPERF_NRT_TOP_TOP_WTLIMIT (0x0004)
|
||||
#define rHPERF_NRT_TOP_TOP_WTLIMIT (*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_TOP_WTLIMIT))
|
||||
#define HPERF_NRT_TOP_VENC_RTLIMIT (0x0010)
|
||||
#define rHPERF_NRT_TOP_VENC_RTLIMIT (*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VENC_RTLIMIT))
|
||||
#define HPERF_NRT_TOP_VENC_WTLIMIT (0x0014)
|
||||
#define rHPERF_NRT_TOP_VENC_WTLIMIT (*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VENC_WTLIMIT))
|
||||
#define HPERF_NRT_TOP_VENC_WREQSP (0x0018)
|
||||
#define rHPERF_NRT_TOP_VENC_WREQSP (*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VENC_WREQSP))
|
||||
#define HPERF_NRT_TOP_VDEC_RTLIMIT (0x0028)
|
||||
#define rHPERF_NRT_TOP_VDEC_RTLIMIT (*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VDEC_RTLIMIT))
|
||||
#define HPERF_NRT_TOP_VDEC_WTLIMIT (0x002C)
|
||||
#define rHPERF_NRT_TOP_VDEC_WTLIMIT (*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VDEC_WTLIMIT))
|
||||
#define HPERF_NRT_TOP_VDEC_WREQSP (0x0030)
|
||||
#define rHPERF_NRT_TOP_VDEC_WREQSP (*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_VDEC_WREQSP))
|
||||
#define HPERF_NRT_TOP_DART_WGATHER (0x0048)
|
||||
#define rHPERF_NRT_TOP_DART_WGATHER (*(volatile u_int32_t *)(NRT_TOP_WIDGETS_BASE_ADDR + HPERF_NRT_TOP_DART_WGATHER))
|
||||
|
||||
#define HPERF_NRT_TOP_AR_CHAN_ARB_MI (0x0408)
|
||||
#define rHPERF_NRT_TOP_AR_CHAN_ARB_MI (*(volatile u_int32_t *)(NRT_TOP_PL301_BASE_ADDR + HPERF_NRT_TOP_AR_CHAN_ARB_MI0))
|
||||
#define HPERF_NRT_TOP_AW_CHAN_ARB_MI (0x040C)
|
||||
#define rHPERF_NRT_TOP_AW_CHAN_ARB_MI (*(volatile u_int32_t *)(NRT_TOP_PL301_BASE_ADDR + HPERF_NRT_TOP_AW_CHAN_ARB_MI0))
|
||||
|
||||
#define HPERF_RT_TOP_DISP0_RTLIMIT (0x0004)
|
||||
#define rHPERF_RT_TOP_DISP0_RTLIMIT (*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_DISP0_RTLIMIT))
|
||||
#define HPERF_RT_TOP_DISP1_RTLIMIT (0x000C)
|
||||
#define rHPERF_RT_TOP_DISP1_RTLIMIT (*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_DISP1_RTLIMIT))
|
||||
#define HPERF_RT_TOP_ISP_RTLIMIT (0x0018)
|
||||
#define rHPERF_RT_TOP_ISP_RTLIMIT (*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_ISP_WTLIMIT))
|
||||
#define HPERF_RT_TOP_ISP_WTLIMIT (0x001C)
|
||||
#define rHPERF_RT_TOP_ISP_WTLIMIT (*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_ISP_RTLIMIT))
|
||||
#define HPERF_RT_TOP_TOP_RTLIMIT (0x0020)
|
||||
#define rHPERF_RT_TOP_TOP_RTLIMIT (*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_TOP_WTLIMIT))
|
||||
#define HPERF_RT_TOP_TOP_WTLIMIT (0x0024)
|
||||
#define rHPERF_RT_TOP_TOP_WTLIMIT (*(volatile u_int32_t *)(RT_TOP_WIDGETS_BASE_ADDR + HPERF_RT_TOP_TOP_RTLIMIT))
|
||||
|
||||
#define HPERF_RT_TOP_AR_CHAN_ARB_MI (0x0408)
|
||||
#define rHPERF_RT_TOP_AR_CHAN_ARB_MI (*(volatile u_int32_t *)(RT_TOP_PL301_BASE_ADDR + HPERF_RT_TOP_AR_CHAN_ARB_MI0))
|
||||
#define HPERF_RT_TOP_AW_CHAN_ARB_MI (0x040C)
|
||||
#define rHPERF_RT_TOP_AW_CHAN_ARB_MI (*(volatile u_int32_t *)(RT_TOP_PL301_BASE_ADDR + HPERF_RT_TOP_AW_CHAN_ARB_MI0))
|
||||
|
||||
|
||||
enum remap_select {
|
||||
REMAP_SRAM = 0,
|
||||
REMAP_SDRAM
|
||||
};
|
||||
|
||||
extern void miu_select_remap(enum remap_select sel);
|
||||
extern void miu_bypass_prep(void);
|
||||
extern void miu_update_device_tree(DTNode *pmgr_node);
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_MIU_H */
|
||||
@@ -0,0 +1,474 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_PMGR_H
|
||||
#define __PLATFORM_SOC_PMGR_H
|
||||
|
||||
#include <lib/devicetree.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rPMGR_PLL0_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0000))
|
||||
#define rPMGR_PLL0_PARAM (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0004))
|
||||
#define rPMGR_PLL1_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0008))
|
||||
#define rPMGR_PLL1_PARAM (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x000C))
|
||||
#define rPMGR_PLL2_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0010))
|
||||
#define rPMGR_PLL2_PARAM (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0014))
|
||||
#define rPMGR_PLL3_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0018))
|
||||
#define rPMGR_PLL3_PARAM (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x001C))
|
||||
#define rPMGR_PLL4_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0020))
|
||||
#define rPMGR_PLL4_PARAM (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0024))
|
||||
#define rPMGR_PLL5_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0028))
|
||||
#define rPMGR_PLL5_PARAM (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x002C))
|
||||
#define rPMGR_PLLUSB_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0030))
|
||||
#define rPMGR_PLLUSB_PARAM (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0034))
|
||||
|
||||
#define rPMGR_PLL_ENABLE (1 << 31)
|
||||
#define rPMGR_PLL_EXT_BYPASS (1 << 30)
|
||||
#define rPMGR_PLL_REAL_LOCK (1 << 29)
|
||||
#define rPMGR_PLL_LOAD (1 << 27)
|
||||
#define rPMGR_PLL_BYPASS (1 << 23)
|
||||
#define rPMGR_PLL_P(_p) (((_p) & 0x03f) << 14)
|
||||
#define rPMGR_PLL_M(_m) (((_m) & 0x3ff) << 3)
|
||||
#define rPMGR_PLL_S(_s) (((_s) & 0x007) << 0)
|
||||
|
||||
#define rPMGR_PARAM_EXT_AFC(_n) ((_n) << 17)
|
||||
#define rPMGR_PARAM_AFC_EN (1 << 16)
|
||||
#define rPMGR_PARAM_LOCK_TIME(_n) ((_n) << 0)
|
||||
|
||||
#define rPMGR_PLL_GATES (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0040))
|
||||
|
||||
#define rPMGR_DOUBLER_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0044))
|
||||
|
||||
#define rPMGR_DOUBLER_ENABLE (1 << 31)
|
||||
#define rPMGR_DOUBLER_EXT_BYPASS (1 << 30)
|
||||
|
||||
#define rPMGR_CPU_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0048))
|
||||
#define rPMGR_MCU_FIXED_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x004C))
|
||||
#define rPMGR_MCU_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0050))
|
||||
#define rPMGR_PCLK1_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0054))
|
||||
|
||||
#define rPMGR_PREDIV0_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0058))
|
||||
#define rPMGR_PREDIV1_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x005C))
|
||||
#define rPMGR_PREDIV2_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0060))
|
||||
#define rPMGR_PREDIV3_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0064))
|
||||
#define rPMGR_PREDIV4_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0068))
|
||||
#define rPMGR_PREDIV5_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x006C))
|
||||
#define rPMGR_PREDIV6_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0070))
|
||||
|
||||
#define rPMGR_MANAGED0_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0074))
|
||||
#define rPMGR_MANAGED1_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0078))
|
||||
#define rPMGR_MANAGED2_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x007C))
|
||||
#define rPMGR_MANAGED3_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0080))
|
||||
#define rPMGR_MANAGED4_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0084))
|
||||
#define rPMGR_MANAGED5_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0088))
|
||||
#define rPMGR_AES_CORE_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x008C))
|
||||
|
||||
#define rPMGR_VID1_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0090))
|
||||
#define rPMGR_MEDIUM0_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0094))
|
||||
#define rPMGR_VID0_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0098))
|
||||
#define rPMGR_I2C_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x009C))
|
||||
#define rPMGR_SDIO_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00A0))
|
||||
#define rPMGR_AUDIO_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00A4))
|
||||
#define rPMGR_HPARK_PCLK0_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00A8))
|
||||
#define rPMGR_HPARK_TCLK_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00AC))
|
||||
#define rPMGR_UPERF_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00B0))
|
||||
#define rPMGR_DEBUG_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00B4))
|
||||
|
||||
#define rPMGR_HPERFRT_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00B8))
|
||||
#define rPMGR_GFX_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00BC))
|
||||
#define rPMGR_GFX_SLC_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00C0))
|
||||
|
||||
#define rPMGR_HPERFNRT_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00C4))
|
||||
#define rPMGR_ISP_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00C8))
|
||||
#define rPMGR_IOP_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00CC))
|
||||
#define rPMGR_CDIO_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00D0))
|
||||
|
||||
#define rPMGR_LPERFS_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00D4))
|
||||
#define rPMGR_PCLK0_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00D8))
|
||||
#define rPMGR_PCLK2_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00DC))
|
||||
#define rPMGR_PCLK3_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00E0))
|
||||
|
||||
#define rPMGR_MEDIUM1_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00E4))
|
||||
#define rPMGR_SPI0_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00E8))
|
||||
#define rPMGR_SPI1_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00EC))
|
||||
#define rPMGR_SPI2_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00F0))
|
||||
#define rPMGR_SPI3_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00F4))
|
||||
#define rPMGR_SPI4_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00F8))
|
||||
#define rPMGR_SLEEP_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x00FC))
|
||||
#define rPMGR_USBPHY_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0100))
|
||||
#define rPMGR_USBPHY1_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0104))
|
||||
#define rPMGR_USBOHCI_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0108))
|
||||
#define rPMGR_USB12_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x010C))
|
||||
#define rPMGR_NCO_REF0_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0110))
|
||||
#define rPMGR_NCO_REF1_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0114))
|
||||
#define rPMGR_NCO_REF2_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0118))
|
||||
#define rPMGR_VENC_MTX_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x011C))
|
||||
#define rPMGR_VENC_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0120))
|
||||
|
||||
#define rPMGR_SLV_BUS_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0124))
|
||||
|
||||
#define PMGR_FIRST_CLK_CFG (&rPMGR_CPU_CLK_CFG)
|
||||
#define PMGR_LAST_CLK_CFG (&rPMGR_SLV_BUS_CLK_CFG)
|
||||
#define PMGR_CLK_CFG_COUNT (((((u_int32_t)(PMGR_LAST_CLK_CFG)) - ((u_int32_t)(PMGR_FIRST_CLK_CFG))) / 4) + 1)
|
||||
#define PMGR_CLK_NUM(_r) (((u_int32_t)&(rPMGR_ ## _r ## _CLK_CFG) - ((u_int32_t)(PMGR_FIRST_CLK_CFG))) / 4)
|
||||
|
||||
#define rPMGR_I2S0_NCO_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0130))
|
||||
#define rPMGR_I2S0_NCO_N1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0134))
|
||||
#define rPMGR_I2S0_NCO_N2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0138))
|
||||
|
||||
#define rPMGR_I2S1_NCO_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0140))
|
||||
#define rPMGR_I2S1_NCO_N1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0144))
|
||||
#define rPMGR_I2S1_NCO_N2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0148))
|
||||
|
||||
#define rPMGR_I2S2_NCO_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0150))
|
||||
#define rPMGR_I2S2_NCO_N1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0154))
|
||||
#define rPMGR_I2S2_NCO_N2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0158))
|
||||
|
||||
#define rPMGR_I2S3_NCO_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0160))
|
||||
#define rPMGR_I2S3_NCO_N1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0164))
|
||||
#define rPMGR_I2S3_NCO_N2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0168))
|
||||
|
||||
#define rPMGR_SPDIF_NCO_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0170))
|
||||
#define rPMGR_SPDIF_NCO_N1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0174))
|
||||
#define rPMGR_SPDIF_NCO_N2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0178))
|
||||
|
||||
#define rPMGR_DP_NCO_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0180))
|
||||
#define rPMGR_DP_NCO_N1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0184))
|
||||
#define rPMGR_DP_NCO_N2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0188))
|
||||
|
||||
#define rPMGR_AMC_REF_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01C0))
|
||||
|
||||
#define rPMGR_MASH_REF_CLK_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01C4))
|
||||
#define rPMGR_MASH_CFG1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01C8))
|
||||
#define rPMGR_MASH_CFG2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01CC))
|
||||
#define rPMGR_SPREAD_CFG1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x01D0))
|
||||
|
||||
#define rPMGR_CLK_CFG_ENABLE (1 << 31)
|
||||
#define rPMGR_CLK_CFG_PENDING (1 << 30)
|
||||
#define rPMGR_CLK_CFG_DIVIDER(_d) (((_d) & 0x1f) << 0)
|
||||
#define rPMGR_CLK_CFG_DIV_MASK rPMGR_CLK_CFG_DIVIDER(0x1f)
|
||||
|
||||
#define PMGR_PERF_STATE_COUNT (16)
|
||||
#define rPMGR_PERF_STATE_A(_s) (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0200 + ((_s) * 0x10)))
|
||||
#define rPMGR_PERF_STATE_B(_s) (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0204 + ((_s) * 0x10)))
|
||||
#define rPMGR_PERF_STATE_C(_s) (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0208 + ((_s) * 0x10)))
|
||||
#define rPMGR_PERF_STATE_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0300))
|
||||
|
||||
#define PMGR_PERF_STATE_SEL(_s) (((_s) & 0xF) << 0)
|
||||
#define PMGR_PERF_STATE_PENDING (0xFF << 16)
|
||||
|
||||
#define kPERF_STATE_BYPASS (0)
|
||||
#define kPERF_STATE_SECUREROM (1)
|
||||
#define kPERF_STATE_IBOOT (2)
|
||||
#define kPERF_STATE_IBOOT_CNT (5)
|
||||
|
||||
#define rPMGR_MCU_CLK_DEBUG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x0400))
|
||||
|
||||
#define rPMGR_CPU0_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1008))
|
||||
#define rPMGR_CPU1_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x100C))
|
||||
#define rPMGR_SCU_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1010))
|
||||
#define rPMGR_L2RAM0_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1014))
|
||||
#define rPMGR_L2RAM1_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1018))
|
||||
#define rPMGR_CPU_REGS_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x101C))
|
||||
#define rPMGR_MCU_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1020))
|
||||
#define rPMGR_GFX_SYS_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1024))
|
||||
#define rPMGR_GFX_CORES_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1028))
|
||||
#define rPMGR_HPERFNRT_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x102C))
|
||||
#define rPMGR_VDEC_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1030))
|
||||
#define rPMGR_SCALER0_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1034))
|
||||
#define rPMGR_SCALER1_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1038))
|
||||
#define rPMGR_JPG0_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x103C))
|
||||
#define rPMGR_JPG1_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1040))
|
||||
#define rPMGR_VENCD_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1044))
|
||||
#define rPMGR_HPERFRT_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1048))
|
||||
#define rPMGR_ISP_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x104C))
|
||||
#define rPMGR_DISP0_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1054))
|
||||
#define rPMGR_DISP1_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1058))
|
||||
#define rPMGR_DISPOUT_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x105C))
|
||||
#define rPMGR_EDPLINK_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1060))
|
||||
#define rPMGR_CLCD_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1064))
|
||||
#define rPMGR_TVOUT_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1068))
|
||||
#define rPMGR_RGBOUT_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x106C))
|
||||
#define rPMGR_DPLINK_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1070))
|
||||
#define rPMGR_CDIO_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1074))
|
||||
#define rPMGR_CDMA_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1078))
|
||||
#define rPMGR_IOP_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x107C))
|
||||
#define rPMGR_UPERF_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1080))
|
||||
#define rPMGR_UPERF1_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1084))
|
||||
#define rPMGR_USB_OTG0_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1088))
|
||||
#define rPMGR_USB_20_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x108C))
|
||||
#define rPMGR_USB_11_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1090))
|
||||
#define rPMGR_USB_OHCI0_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1094))
|
||||
#define rPMGR_USB_OHCI1_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1098))
|
||||
#define rPMGR_USB_REG_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x109C))
|
||||
#define rPMGR_USB1_OTG0_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10A0))
|
||||
#define rPMGR_USB1_20_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10A4))
|
||||
#define rPMGR_USB1_11_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10A8))
|
||||
#define rPMGR_USB1_OHCI0_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10AC))
|
||||
#define rPMGR_USB1_OHCI1_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10B0))
|
||||
#define rPMGR_USB1_REG_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10B4))
|
||||
#define rPMGR_AUDIO_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10B8))
|
||||
#define rPMGR_I2S0_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10BC))
|
||||
#define rPMGR_I2S1_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10C0))
|
||||
#define rPMGR_I2S2_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10C4))
|
||||
#define rPMGR_I2S3_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10C8))
|
||||
#define rPMGR_SPDIF_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10CC))
|
||||
#define rPMGR_HPARK_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10D0))
|
||||
#define rPMGR_SDIO_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10D4))
|
||||
#define rPMGR_SHA1_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10D8))
|
||||
#define rPMGR_SHA2_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10DC))
|
||||
#define rPMGR_FMI0_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10E0))
|
||||
#define rPMGR_FMI0BCH_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10E4))
|
||||
#define rPMGR_FMI1_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10E8))
|
||||
#define rPMGR_FMI1BCH_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10EC))
|
||||
#define rPMGR_FMI2_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10F0))
|
||||
#define rPMGR_FMI2BCH_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10F4))
|
||||
#define rPMGR_FMI3_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10F8))
|
||||
#define rPMGR_FMI3BCH_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x10FC))
|
||||
#define rPMGR_SPI0_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1100))
|
||||
#define rPMGR_SPI1_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1104))
|
||||
#define rPMGR_SPI2_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1108))
|
||||
#define rPMGR_SPI3_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x110C))
|
||||
#define rPMGR_SPI4_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1110))
|
||||
#define rPMGR_UART0_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1114))
|
||||
#define rPMGR_UART1_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1118))
|
||||
#define rPMGR_UART2_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x111C))
|
||||
#define rPMGR_UART3_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1120))
|
||||
#define rPMGR_UART4_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1124))
|
||||
#define rPMGR_UART5_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1128))
|
||||
#define rPMGR_UART6_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x112C))
|
||||
#define rPMGR_PKE_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1130))
|
||||
#define rPMGR_I2C0_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1134))
|
||||
#define rPMGR_I2C1_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1138))
|
||||
#define rPMGR_I2C2_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x113C))
|
||||
#define rPMGR_PWM_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1140))
|
||||
#define rPMGR_SCRT_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1144))
|
||||
#define rPMGR_GPIO_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1148))
|
||||
#define rPMGR_SWI_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x114C))
|
||||
#define rPMGR_DWI_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1150))
|
||||
#define rPMGR_DEBUG_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1154))
|
||||
#define rPMGR_AIC_PS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1158))
|
||||
|
||||
#define rPMGR_PS_RESET (1 << 31)
|
||||
|
||||
#define PMGR_FIRST_PS (&rPMGR_CPU0_PS)
|
||||
#define PMGR_LAST_PS (&rPMGR_AIC_PS)
|
||||
#define PMGR_DEV_PS_COUNT (((((u_int32_t)(PMGR_LAST_PS)) - ((u_int32_t)(PMGR_FIRST_PS))) / 4) + 1)
|
||||
#define PMGR_PS_NUM(_r) (((u_int32_t)&(rPMGR_ ## _r ## _PS) - ((u_int32_t)(PMGR_FIRST_PS))) / 4)
|
||||
|
||||
#define rPMGR_CPU_CFG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1180))
|
||||
|
||||
#define rPMGR_PWR_GATE_CTL_SET (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1200))
|
||||
#define rPMGR_PWR_GATE_CTL_CLR (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1204))
|
||||
#define rPMGR_PWR_GATE_IOP (1 << 6)
|
||||
#define rPMGR_PWR_GATE_GFX_MODE (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1208))
|
||||
|
||||
#define rPMGR_CORE_OFFLINE_SET (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1210))
|
||||
#define rPMGR_CORE_OFFLINE_CLR (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1214))
|
||||
#define rPMGR_WAKE_CORES (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1220))
|
||||
|
||||
#define PMGR_PWR_GATE_TIME_COUNT (15)
|
||||
#define rPMGR_PWR_GATE_TIME_A(_n) (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x1238 + ((_n) * 8)))
|
||||
#define rPMGR_PWR_GATE_TIME_B(_n) (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x123C + ((_n) * 8)))
|
||||
#define rPMGR_PWR_GATE_DBG0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x12E0))
|
||||
#define rPMGR_PWR_GATE_DBG1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x12E4))
|
||||
|
||||
#define rPMGR_TEST_CLK (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2000))
|
||||
#define rPMGR_OSC_DEBUG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x200C))
|
||||
#define rPMGR_PLL0_DEBUG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2010))
|
||||
#define rPMGR_PLL1_DEBUG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2014))
|
||||
#define rPMGR_PLL2_DEBUG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2018))
|
||||
#define rPMGR_PLL3_DEBUG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x201C))
|
||||
#define rPMGR_PLL4_DEBUG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2020))
|
||||
#define rPMGR_PLL5_DEBUG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2024))
|
||||
#define rPMGR_PLLUSB_DEBUG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2028))
|
||||
#define rPMGR_DOUBLER_DEBUG (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x202C))
|
||||
|
||||
#define rPMGR_PLL_DEBUG_ENABLED (1 << 31)
|
||||
#define rPMGR_PLL_DEBUG_BYP_ENABLED (1 << 30)
|
||||
#define rPMGR_PLL_DEBUG_DBG_STPCLK_EN (1 << 24)
|
||||
#define rPMGR_PLL_DEBUG_LOST_LOCK (1 << 16)
|
||||
#define rPMGR_PLL_DEBUG_STATE(_r) (((_r) >> 0) & 0xff)
|
||||
|
||||
#define rPMGR_EMA_CTL_CPU (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2100))
|
||||
#define rPMGR_EMA_CTL_CPU_SEL (0x01 << 0)
|
||||
#define rPMGR_EMA_CTL_CPU_SPIN (0x01 << 16)
|
||||
#define rPMGR_EMA_CTL_SOC (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2104))
|
||||
#define rPMGR_EMA_CTL_SOC_SEL (0x1f << 0) // XXX BANK_SEL_DISP?
|
||||
#define rPMGR_EMA_CTL_SOC_SPIN (0x01 << 16)
|
||||
|
||||
#define rPMGR_SRAM_EMA_B0_Pn_LO(_n) (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2120 + ((_n) * 8)))
|
||||
#define rPMGR_SRAM_EMA_B0_Pn_HI(_n) (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2124 + ((_n) * 8)))
|
||||
#define rPMGR_SRAM_EMA_B1_Pn_LO(_n) (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x21C0 + ((_n) * 8)))
|
||||
#define rPMGR_SRAM_EMA_B1_Pn_HI(_n) (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x21C4 + ((_n) * 8)))
|
||||
|
||||
enum {
|
||||
EMA_CPU = 0,
|
||||
EMA_MCU = 1,
|
||||
EMA_GFX_PIPES_SYS = 2,
|
||||
EMA_GFX_HYDRA = 3,
|
||||
EMA_VDEC = 4,
|
||||
EMA_VENC = 5,
|
||||
EMA_ISP = 6,
|
||||
EMA_DISP = 7,
|
||||
EMA_NRT = 8,
|
||||
EMA_CIF = 9,
|
||||
EMA_IOP = 10,
|
||||
EMA_SAUDIO = 11,
|
||||
EMA_CDMA = 12,
|
||||
EMA_FMI = 13,
|
||||
EMA_HPARK = 14,
|
||||
};
|
||||
|
||||
#define rPMGR_WDOG_TMR (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3020))
|
||||
#define rPMGR_WDOG_RST (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3024))
|
||||
#define rPMGR_WDOG_INT (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3028))
|
||||
#define rPMGR_WDOG_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x302C))
|
||||
|
||||
#define rPMGR_EVENT_TMR (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3100))
|
||||
#define rPMGR_EVENT_PERIOD (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3104))
|
||||
#define rPMGR_EVENT_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x3108))
|
||||
|
||||
#define rPMGR_PERF_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4000))
|
||||
#define rPMGR_PERF_STATUS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4004))
|
||||
#define rPMGR_PERF_CTR0_LO (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4020))
|
||||
#define rPMGR_PERF_CTR0_HI (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4024))
|
||||
#define rPMGR_PERF_CFG0_LO (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4028))
|
||||
#define rPMGR_PERF_CFG0_MID (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x402C))
|
||||
#define rPMGR_PERF_CFG0_HI (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4030))
|
||||
#define rPMGR_PERF_CFG0_HI2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4034))
|
||||
#define rPMGR_PERF_CTR1_LO (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4040))
|
||||
#define rPMGR_PERF_CTR1_HI (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4044))
|
||||
#define rPMGR_PERF_CFG1_LO (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4048))
|
||||
#define rPMGR_PERF_CFG1_MID (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x404C))
|
||||
#define rPMGR_PERF_CFG1_HI (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4050))
|
||||
#define rPMGR_PERF_CFG1_HI2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x4054))
|
||||
|
||||
#define rPMGR_SCRATCH0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6000))
|
||||
#define rPMGR_SCRATCH1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6004)) // Used: iBoot->pmgr
|
||||
#define rPMGR_SCRATCH2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6008))
|
||||
#define rPMGR_SCRATCH3 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x600C))
|
||||
#define rPMGR_SCRATCH4 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6010))
|
||||
#define rPMGR_SCRATCH5 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6014))
|
||||
#define rPMGR_SCRATCH6 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6018))
|
||||
#define rPMGR_SCRATCH7 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x601C))
|
||||
#define rPMGR_SCRATCH8 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6020))
|
||||
#define rPMGR_SCRATCH9 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6024))
|
||||
#define rPMGR_SCRATCH10 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6028))
|
||||
#define rPMGR_SCRATCH11 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x602C))
|
||||
#define rPMGR_SCRATCH12 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6030))
|
||||
#define rPMGR_SCRATCH13 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6034))
|
||||
#define rPMGR_SCRATCH14 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x6038))
|
||||
#define rPMGR_SCRATCH15 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x603C))
|
||||
|
||||
#define rPMGR_DAC_FS (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x7000))
|
||||
|
||||
#define rPMGR_USB_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x8000))
|
||||
|
||||
#define rPMGR_USB1_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x9000))
|
||||
|
||||
#define rPMGR_SHA_SEL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xA000))
|
||||
|
||||
#define rPMGR_SECURITY (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xB000))
|
||||
|
||||
#define rPMGR_GFX_CTL (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xC000))
|
||||
|
||||
#define rPMGR_THERMAL_CTL0 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xD000))
|
||||
#define rPMGR_THERMAL_CTL1 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xD004))
|
||||
#define rPMGR_THERMAL_CTL2 (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xD008))
|
||||
#define rPMGR_THERMAL_RDBK (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xD00C))
|
||||
#define rPMGR_THERMAL_SUM (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xD010))
|
||||
#define rPMGR_THERMAL_SUM_CNT (*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0xD014))
|
||||
|
||||
#define PGMR_GET_PERF_STATE_INDEX(_n, _x) (((_x) >> ((_n) * 4)) & 0xF)
|
||||
#define PGMR_SET_PERF_STATE_INDEX(_n, _i) (((_i) & 0xF) << ((_n) * 4))
|
||||
#define PMGR_PERF_STATE_V(_n) (_n)
|
||||
#define PMGR_PERF_STATE_P (3)
|
||||
#define PMGR_PERF_STATE_M(_n) (4 + (_n))
|
||||
|
||||
/* This defines the order of clocks in AppleS5L8945XIO.cpp; keep the table there
|
||||
* in synch with this one.
|
||||
*/
|
||||
enum {
|
||||
PMGR_CLK_OSC = 0, // 0x00 - OSC
|
||||
PMGR_CLK_PLL0, // 0x01 - PLL0
|
||||
PMGR_CLK_PLL1, // 0x02 - PLL1
|
||||
PMGR_CLK_PLL2, // 0x03 - PLL2
|
||||
PMGR_CLK_PLL3, // 0x04 - PLL3
|
||||
PMGR_CLK_PLL4, // 0x05 - PLL4
|
||||
PMGR_CLK_PLL5, // 0x06 - PLL5
|
||||
PMGR_CLK_PLLUSB, // 0x07 - PLLUSB
|
||||
PMGR_CLK_DOUBLER, // 0x08 - DOUBLER
|
||||
PMGR_CLK_CPU, // 0x09 - CPU
|
||||
PMGR_CLK_MEM, // 0x0A - MEM
|
||||
PMGR_CLK_PIO, // 0x0B - PIO
|
||||
PMGR_CLK_ACP, // 0x0C - ACP
|
||||
PMGR_CLK_MCU_FIXED, // 0x0D - MCU_FIXED
|
||||
PMGR_CLK_MCU, // 0x0E - MCU
|
||||
PMGR_CLK_PREDIV0, // 0x0F - PREDIV0
|
||||
PMGR_CLK_PREDIV1, // 0x10 - PREDIV1
|
||||
PMGR_CLK_PREDIV2, // 0x11 - PREDIV2
|
||||
PMGR_CLK_PREDIV3, // 0x12 - PREDIV3
|
||||
PMGR_CLK_PREDIV4, // 0x13 - PREDIV4
|
||||
PMGR_CLK_PREDIV5, // 0x14 - PREDIV5
|
||||
PMGR_CLK_PREDIV6, // 0x15 - PREDIV6
|
||||
PMGR_CLK_MANAGED0, // 0x16 - MANAGED0
|
||||
PMGR_CLK_MANAGED1, // 0x17 - MANAGED1
|
||||
PMGR_CLK_MANAGED2, // 0x18 - MANAGED2
|
||||
PMGR_CLK_MANAGED3, // 0x19 - MANAGED3
|
||||
PMGR_CLK_MANAGED4, // 0x1A - MANAGED4
|
||||
PMGR_CLK_MANAGED5, // 0x1B - MANAGED5
|
||||
PMGR_CLK_AES_CORE, // 0x1C - AES_CORE
|
||||
PMGR_CLK_MEDIUM0, // 0x1D - MEDIUM0
|
||||
PMGR_CLK_MEDIUM1, // 0x1E - MEDIUM1
|
||||
PMGR_CLK_VID0, // 0x1F - VID0
|
||||
PMGR_CLK_VID1, // 0x20 - VID1
|
||||
PMGR_CLK_I2C, // 0x21 - I2C
|
||||
PMGR_CLK_SDIO, // 0x22 - SDIO
|
||||
PMGR_CLK_AUDIO, // 0x23 - AUDIO
|
||||
PMGR_CLK_HPARK_PCLK, // 0x24 - HPARK_PCLK
|
||||
PMGR_CLK_HPARK_TCLK, // 0x25 - HPARK_TCLK
|
||||
PMGR_CLK_UPERF, // 0x26 - UPERF
|
||||
PMGR_CLK_DEBUG, // 0x27 - DEBUG
|
||||
PMGR_CLK_HPERFRT, // 0x28 - HPERFRT
|
||||
PMGR_CLK_GFX, // 0x29 - GFX
|
||||
PMGR_CLK_GFX_SLC, // 0x2A - GFX_SLC
|
||||
PMGR_CLK_HPERFNRT, // 0x2B - HPERFNRT
|
||||
PMGR_CLK_ISP, // 0x2C - ISP
|
||||
PMGR_CLK_IOP, // 0x2D - IOP
|
||||
PMGR_CLK_CDIO, // 0x2E - CDIO
|
||||
PMGR_CLK_LPERFS, // 0x2F - LPERFS
|
||||
PMGR_CLK_PCLK0, // 0x30 - PCLK0
|
||||
PMGR_CLK_PCLK1, // 0x31 - PCLK1
|
||||
PMGR_CLK_PCLK2, // 0x32 - PCLK2
|
||||
PMGR_CLK_PCLK3, // 0x33 - PCLK3
|
||||
PMGR_CLK_SPI0, // 0x34 - SPI0
|
||||
PMGR_CLK_SPI1, // 0x35 - SPI1
|
||||
PMGR_CLK_SPI2, // 0x36 - SPI2
|
||||
PMGR_CLK_SPI3, // 0x37 - SPI3
|
||||
PMGR_CLK_SPI4, // 0x38 - SPI4
|
||||
PMGR_CLK_SLOW, // 0x39 - SLOW
|
||||
PMGR_CLK_SLEEP, // 0x3A - SLEEP
|
||||
PMGR_CLK_USBPHY, // 0x3B - USBPHY
|
||||
PMGR_CLK_USBPHY1, // 0x3C - USBPHY1
|
||||
PMGR_CLK_USBOHCI, // 0x3D - USBOHCI
|
||||
PMGR_CLK_USB12, // 0x3E - USB12
|
||||
PMGR_CLK_NCO_REF0, // 0x3F - NCO_REF0
|
||||
PMGR_CLK_NCO_REF1, // 0x40 - NCO_REF1
|
||||
PMGR_CLK_NCO_REF2, // 0x41 - NCO_REF2
|
||||
PMGR_CLK_VENC_MTX, // 0x42 - VENC_MTX
|
||||
PMGR_CLK_VENC, // 0x43 - VENC
|
||||
PMGR_CLK_SLV_BUS, // 0x44 - SLV_BUS
|
||||
PMGR_CLK_COUNT
|
||||
};
|
||||
|
||||
extern void pmgr_update_device_tree(DTNode *pmgr_node);
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_PMGR_H */
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_TRAMPOLINE_H
|
||||
#define __PLATFORM_TRAMPOLINE_H
|
||||
|
||||
#include <platform/memmap.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define SECURITY_REG (PMGR_BASE_ADDR + 0xB000)
|
||||
#define ROM_READ_DISABLE (1 << 0)
|
||||
|
||||
#endif /* ! __PLATFORM_TRAMPOLINE_H */
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_USBCONFIG_H
|
||||
#define __PLATFORM_USBCONFIG_H
|
||||
|
||||
#define USBPHY_CLK_TYPE (3) /* Use CLKCORE */
|
||||
|
||||
#define USBPHY_UVLDCON_VALUE (2)
|
||||
|
||||
#define USBPHY_UOTGTUNE1 (0x349)
|
||||
#define USBPHY_UOTGTUNE2 (0x733)
|
||||
|
||||
#define USBOTG_AHB_DMA_BURST (DWCUSB_GAHBCFG_HBST_INCR8)
|
||||
|
||||
#endif /* ! __PLATFORM_USBCONFIG_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,208 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <arch.h>
|
||||
#include <arch/arm/arm.h>
|
||||
#include <debug.h>
|
||||
#include <drivers/a5iop/a5iop.h>
|
||||
#include <platform.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/int.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <platform/timer.h>
|
||||
#include <platform/soc/hwisr.h>
|
||||
#include <platform/soc/pmgr.h>
|
||||
#include <sys.h>
|
||||
#include <sys/boot.h>
|
||||
#include <sys/callout.h>
|
||||
|
||||
/*
|
||||
* Platform memory layout.
|
||||
*
|
||||
* The IOP sees SDRAM at its physical location uncached, and has an cached aperture
|
||||
* visible elsewhere. SDRAM size of up to 1GB is currently supported.
|
||||
* SRAM is not visible/legally usable.
|
||||
*
|
||||
* For some platforms/targets, SDRAM_LEN is not constant and so we
|
||||
* have to compute a maximum via other means.
|
||||
*
|
||||
* Note that the AE2 Sparrow shares this code.
|
||||
*/
|
||||
#define MEM_CACHED_BASE (SDRAM_BASE | 0xc0000000)
|
||||
#define SDRAM_MAX_LEN (SDRAM_BANK_LEN * SDRAM_BANK_COUNT)
|
||||
struct mem_static_map_entry mem_static_map_entries[] = {
|
||||
{
|
||||
MEM_CACHED_BASE, /* cached */
|
||||
SDRAM_BASE, /* uncached */
|
||||
SDRAM_BASE, /* physical */
|
||||
SDRAM_MAX_LEN /* length */
|
||||
},
|
||||
{MAP_NO_ENTRY, MAP_NO_ENTRY, MAP_NO_ENTRY, 0}
|
||||
};
|
||||
|
||||
void platform_mmu_setup(bool resume)
|
||||
{
|
||||
if (false == resume) {
|
||||
/* Remap text base to zero, outer uncacheable, shared */
|
||||
arm_mmu_map_section(0, TEXT_BASE, kARMMMUInnerNormalOuterNoncached, true);
|
||||
#if MAP_SRAM_CACHED
|
||||
/* Map the SRAM as cacheable, shared */
|
||||
arm_mmu_map_section(SRAM_BASE, SRAM_BASE, kARMMMUNormal, true);
|
||||
#endif // MAP_SRAM_CACHED
|
||||
/* Remap all of SDRAM through the cacheable aperture, outer uncacheable, shared */
|
||||
arm_mmu_map_section_range(MEM_CACHED_BASE, SDRAM_BASE, ROUNDUP(SDRAM_BANK_LEN * SDRAM_BANK_COUNT, MB)/MB,
|
||||
kARMMMUInnerNormalOuterNoncached, true, false);
|
||||
/* Remap all of SDRAM through the uncacheable aperture (existing mappings should be there, but be sure) */
|
||||
arm_mmu_map_section_range(SDRAM_BASE, SDRAM_BASE, ROUNDUP(SDRAM_BANK_LEN * SDRAM_BANK_COUNT, MB)/MB,
|
||||
kARMMMUStronglyOrdered, false, false);
|
||||
}
|
||||
}
|
||||
|
||||
bool platform_get_production_mode(void)
|
||||
{
|
||||
return(true);
|
||||
}
|
||||
|
||||
bool platform_get_secure_mode(void)
|
||||
{
|
||||
return(true);
|
||||
}
|
||||
|
||||
void platform_reset(bool panic)
|
||||
{
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
|
||||
/*
|
||||
* Early init is done every time the IOP starts.
|
||||
*/
|
||||
int
|
||||
platform_early_init()
|
||||
{
|
||||
#if PLATFORM_VARIANT_IOP
|
||||
/* In general we want power-gating to be disabled. */
|
||||
rPMGR_PWR_GATE_CTL_CLR = rPMGR_PWR_GATE_IOP;
|
||||
while (rPMGR_PWR_GATE_CTL_CLR & rPMGR_PWR_GATE_IOP) ;
|
||||
#endif
|
||||
|
||||
interrupt_init();
|
||||
|
||||
timer_init(0);
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Halt waiting for an interrupt.
|
||||
*/
|
||||
void
|
||||
platform_halt(void)
|
||||
{
|
||||
arch_halt();
|
||||
}
|
||||
|
||||
#if SUPPORT_SLEEP
|
||||
|
||||
#if WITH_IOP_POWER_GATING
|
||||
|
||||
/*
|
||||
* Deep idle sleep with power gating
|
||||
*/
|
||||
void
|
||||
platform_deep_idle(void)
|
||||
{
|
||||
rPMGR_PWR_GATE_CTL_SET = rPMGR_PWR_GATE_IOP;
|
||||
while (!(rPMGR_PWR_GATE_CTL_SET & rPMGR_PWR_GATE_IOP)) ;
|
||||
a5iop_sleep(1);
|
||||
rPMGR_PWR_GATE_CTL_CLR = rPMGR_PWR_GATE_IOP;
|
||||
while (rPMGR_PWR_GATE_CTL_CLR & rPMGR_PWR_GATE_IOP) ;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void
|
||||
platform_sleep(void)
|
||||
{
|
||||
/* We assume power-gating is disabled, which it need to be so
|
||||
* the IOP wrapper registers don't disappear. */
|
||||
a5iop_sleep(0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Cache control
|
||||
*/
|
||||
void
|
||||
platform_cache_operation(int operation, void *address, u_int32_t length)
|
||||
{
|
||||
a5iop_cache_operation(operation, address, length);
|
||||
}
|
||||
|
||||
/*
|
||||
* Host doorbell uses a SWI in the AIC.
|
||||
*/
|
||||
static void (* _doorbell_handler)(void *arg);
|
||||
static void
|
||||
platform_doorbell_handler(void *arg)
|
||||
{
|
||||
/* clear the doorbell before passing up */
|
||||
interrupt_clear_ipc(INT_IOP);
|
||||
_doorbell_handler(arg);
|
||||
}
|
||||
|
||||
void
|
||||
platform_init_iop_doorbell(void (* handler)(void *arg), void *arg)
|
||||
{
|
||||
_doorbell_handler = handler;
|
||||
install_int_handler(INT_IOP, platform_doorbell_handler, arg);
|
||||
set_int_type(INT_IOP, INT_TYPE_IRQ | INT_TYPE_LEVEL);
|
||||
unmask_int(INT_IOP);
|
||||
}
|
||||
|
||||
void
|
||||
platform_mask_doorbell(void)
|
||||
{
|
||||
mask_int(INT_IOP);
|
||||
}
|
||||
|
||||
void
|
||||
platform_unmask_doorbell(void)
|
||||
{
|
||||
unmask_int(INT_IOP);
|
||||
}
|
||||
|
||||
void
|
||||
platform_ring_host_doorbell(void)
|
||||
{
|
||||
interrupt_generate_ipc(INT_HOST);
|
||||
}
|
||||
|
||||
int
|
||||
platform_init_nmi(void (*handler)(void *arg), void *arg)
|
||||
{
|
||||
#ifdef INT_IOP_NMI
|
||||
install_int_handler(INT_IOP_NMI, handler, arg);
|
||||
set_int_type(INT_IOP_NMI, INT_TYPE_FIQ | INT_TYPE_LEVEL);
|
||||
unmask_int(INT_IOP_NMI);
|
||||
#endif
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Clock management.
|
||||
*
|
||||
* Currently the IOP does none for this platform.
|
||||
*/
|
||||
void clock_gate(int device, bool enable)
|
||||
{
|
||||
}
|
||||
@@ -0,0 +1,341 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/miu.h>
|
||||
#include <platform.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <platform/miu.h>
|
||||
#include <platform/soc/miu.h>
|
||||
#include <platform/soc/pmgr.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
|
||||
static void miu_configure_bridge(const u_int32_t *bridge_settings);
|
||||
|
||||
#define BRIDGE_SHIFT (16)
|
||||
#define BRIDGE_MASK (0xFFFF)
|
||||
#define NRT_DART_WIDGETS (0 << BRIDGE_SHIFT)
|
||||
#define NRT_DART_BRIDGE (1 << BRIDGE_SHIFT)
|
||||
#define NRT_TOP_WIDGETS (2 << BRIDGE_SHIFT)
|
||||
#define NRT_TOP_BRIDGE (3 << BRIDGE_SHIFT)
|
||||
#define RT_TOP_WIDGETS (4 << BRIDGE_SHIFT)
|
||||
#define RT_TOP_BRIDGE (5 << BRIDGE_SHIFT)
|
||||
#define UPERF_WIDGETS (6 << BRIDGE_SHIFT)
|
||||
#define UPERF_BRIDGE (7 << BRIDGE_SHIFT)
|
||||
#define CDIO_WIDGETS (8 << BRIDGE_SHIFT)
|
||||
#define CDIO_BRIDGE (9 << BRIDGE_SHIFT)
|
||||
#define UPERF1_WIDGETS (10 << BRIDGE_SHIFT)
|
||||
#define UPERF1_BRIDGE (11 << BRIDGE_SHIFT)
|
||||
|
||||
static const u_int32_t bridge_registers[] = {
|
||||
NRT_DART_WIDGETS_BASE_ADDR, NRT_DART_PL301_BASE_ADDR,
|
||||
NRT_TOP_WIDGETS_BASE_ADDR, NRT_TOP_PL301_BASE_ADDR,
|
||||
RT_TOP_WIDGETS_BASE_ADDR, RT_TOP_PL301_BASE_ADDR,
|
||||
UPERF_WIDGETS_BASE_ADDR, UPERF_PL301_BASE_ADDR,
|
||||
CDIO_WIDGETS_BASE_ADDR, CDIO_PL301_BASE_ADDR,
|
||||
UPERF1_WIDGETS_BASE_ADDR, UPERF1_PL301_BASE_ADDR,
|
||||
};
|
||||
|
||||
// The following settings are based on H4 Tunables Revision 0.24
|
||||
|
||||
#if APPLICATION_SECUREROM || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
|
||||
static const u_int32_t bridge_settings_static[] = {
|
||||
// Configure recommended transaction limits in CDIO
|
||||
CDIO_WIDGETS | CDIO_IOP_RTLIMIT, 0x00000808,
|
||||
CDIO_WIDGETS | CDIO_IOP_WTLIMIT, 0x00000808,
|
||||
CDIO_WIDGETS | CDIO_CDMA_RTLIMIT, 0x00000808,
|
||||
CDIO_WIDGETS | CDIO_CDMA_WTLIMIT, 0x00000808,
|
||||
CDIO_WIDGETS | CDIO_UPERF_RTLIMIT, 0x00000404,
|
||||
CDIO_WIDGETS | CDIO_UPERF_WTLIMIT, 0x00000404,
|
||||
CDIO_WIDGETS | CDIO_AUDIO_RTLIMIT, 0x00000808,
|
||||
CDIO_WIDGETS | CDIO_AUDIO_WTLIMIT, 0x00000808,
|
||||
CDIO_WIDGETS | CDIO_PIO_RTLIMIT, 0x00000808,
|
||||
CDIO_WIDGETS | CDIO_PIO_WTLIMIT, 0x00000404,
|
||||
CDIO_WIDGETS | CDIO_UPERF1_RTLIMIT, 0x00000404,
|
||||
CDIO_WIDGETS | CDIO_UPERF1_WTLIMIT, 0x00000404,
|
||||
|
||||
// Configure recommended bridge settings in CDIO
|
||||
CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0, 0x00000000,
|
||||
CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0, 0x01000001,
|
||||
CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0, 0x02000002,
|
||||
CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0, 0x03000003,
|
||||
CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0, 0x04000004,
|
||||
CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0, 0x05000005,
|
||||
CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0, 0x00000000,
|
||||
CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0, 0x01000001,
|
||||
CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0, 0x02000002,
|
||||
CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0, 0x03000003,
|
||||
CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0, 0x04000004,
|
||||
CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0, 0x05000005,
|
||||
CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1, 0x00000000,
|
||||
CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1, 0x01000001,
|
||||
CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1, 0x02000002,
|
||||
CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1, 0x03000003,
|
||||
CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1, 0x04000004,
|
||||
CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1, 0x05000005,
|
||||
CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1, 0x00000000,
|
||||
CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1, 0x01000001,
|
||||
CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1, 0x02000002,
|
||||
CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1, 0x03000003,
|
||||
CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1, 0x04000004,
|
||||
CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1, 0x05000005,
|
||||
|
||||
// Configure recommended features in CDIO
|
||||
CDIO_WIDGETS | CDIO_IOP_WREQSP, 0x00000003,
|
||||
CDIO_WIDGETS | CDIO_CDMA_WGATHER, 0x00000100,
|
||||
CDIO_WIDGETS | CDIO_UPERF_WGATHER, 0x00000100,
|
||||
CDIO_WIDGETS | CDIO_AUDIO_WGATHER, 0x00000100,
|
||||
CDIO_WIDGETS | CDIO_UPERF1_WGATHER, 0x00000100,
|
||||
|
||||
// Configure recommended traffic attributes in UPERF
|
||||
// AxCACHE = Cacheable
|
||||
// AxUSER = enable Shared bit
|
||||
UPERF_WIDGETS | UPERF_OTG_QOS, 0x01010101,
|
||||
UPERF_WIDGETS | UPERF_OTG_CACHE, 0x01020102,
|
||||
UPERF_WIDGETS | UPERF_EHCI_QOS, 0x01010101,
|
||||
UPERF_WIDGETS | UPERF_EHCI_CACHE, 0x01020102,
|
||||
UPERF_WIDGETS | UPERF_OHCI0_QOS, 0x01010101,
|
||||
UPERF_WIDGETS | UPERF_OHCI0_CACHE, 0x01020102,
|
||||
UPERF_WIDGETS | UPERF_OHCI1_QOS, 0x01010101,
|
||||
UPERF_WIDGETS | UPERF_OHCI1_CACHE, 0x01020102,
|
||||
|
||||
UPERF1_WIDGETS | UPERF_OTG_QOS, 0x01010101,
|
||||
UPERF1_WIDGETS | UPERF_OTG_CACHE, 0x01020102,
|
||||
UPERF1_WIDGETS | UPERF_EHCI_QOS, 0x01010101,
|
||||
UPERF1_WIDGETS | UPERF_EHCI_CACHE, 0x01020102,
|
||||
UPERF1_WIDGETS | UPERF_OHCI0_QOS, 0x01010101,
|
||||
UPERF1_WIDGETS | UPERF_OHCI0_CACHE, 0x01020102,
|
||||
UPERF1_WIDGETS | UPERF_OHCI1_QOS, 0x01010101,
|
||||
UPERF1_WIDGETS | UPERF_OHCI1_CACHE, 0x01020102,
|
||||
|
||||
0, 0,
|
||||
0, 0
|
||||
};
|
||||
#endif // APPLICATION_SECUREROM || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
|
||||
|
||||
#if WITH_DEVICETREE || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
|
||||
static const u_int32_t bridge_settings_dynamic[] = {
|
||||
// Configure recommended transaction limits in HPerf-NRT DART
|
||||
NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER0_RTLIMIT, 0x00000707,
|
||||
NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER0_WTLIMIT, 0x00000404,
|
||||
NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER1_RTLIMIT, 0x00000707,
|
||||
NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER1_WTLIMIT, 0x00000404,
|
||||
NRT_DART_WIDGETS | HPERF_NRT_DART_DART_RTLIMIT, 0x00000808,
|
||||
NRT_DART_WIDGETS | HPERF_NRT_DART_DART_WTLIMIT, 0x00000808,
|
||||
|
||||
// Configure recommended bridge settings in HPerf-NRT DART
|
||||
NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI, 0x00000000, // JPEG0 High Priority
|
||||
NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI, 0x01000001, // JPEG1 High Priority
|
||||
NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI, 0x02000102, // Scaler0 Reduced Priority
|
||||
NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI, 0x03000103, // Sclaer1 Reduced Priority
|
||||
NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI, 0x00000000, // JPEG0 High Priority
|
||||
NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI, 0x01000001, // JPEG1 High Priority
|
||||
NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI, 0x02000102, // Scaler0 Reduced Priority
|
||||
NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI, 0x03000103, // Sclaer1 Reduced Priority
|
||||
|
||||
// Configure recommended bridge settings in HPerf-NRT DART
|
||||
NRT_DART_WIDGETS | HPERF_NRT_DART_JPEG0_QOS, 0x01010101, // JPEG0 LLT Traffic for R&W
|
||||
NRT_DART_WIDGETS | HPERF_NRT_DART_JPEG1_QOS, 0x01010101, // JPEG0 LLT Traffic for R&W
|
||||
0, 0,
|
||||
|
||||
// Configure recommended transaction limits in HPerf-NRT Top
|
||||
NRT_TOP_WIDGETS | HPERF_NRT_TOP_VENC_RTLIMIT, 0x00002020,
|
||||
NRT_TOP_WIDGETS | HPERF_NRT_TOP_VENC_WTLIMIT, 0x00000808,
|
||||
NRT_TOP_WIDGETS | HPERF_NRT_TOP_VDEC_RTLIMIT, 0x00001010,
|
||||
NRT_TOP_WIDGETS | HPERF_NRT_TOP_VDEC_WTLIMIT, 0x00000808,
|
||||
NRT_TOP_WIDGETS | HPERF_NRT_TOP_TOP_RTLIMIT, 0x00003F3F,
|
||||
NRT_TOP_WIDGETS | HPERF_NRT_TOP_TOP_WTLIMIT, 0x00000F0F,
|
||||
|
||||
// Configure recommended bridge settings in HPerf-NRT Top
|
||||
NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI, 0x00000000,
|
||||
NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI, 0x01000001,
|
||||
NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI, 0x02000002,
|
||||
NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI, 0x03000003,
|
||||
NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI, 0x00000000,
|
||||
NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI, 0x01000001,
|
||||
NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI, 0x02000002,
|
||||
NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI, 0x03000003,
|
||||
|
||||
// Configure recommended features in HPerf-NRT Top
|
||||
NRT_TOP_WIDGETS | HPERF_NRT_TOP_DART_WGATHER, 0x00000000,
|
||||
NRT_TOP_WIDGETS | HPERF_NRT_TOP_VENC_WREQSP, 0x00000003,
|
||||
NRT_TOP_WIDGETS | HPERF_NRT_TOP_VDEC_WREQSP, 0x00000003,
|
||||
0, 0,
|
||||
|
||||
// Configure recommended transaction limits in HPerf-RT Top
|
||||
RT_TOP_WIDGETS | HPERF_RT_TOP_TOP_RTLIMIT, 0x00003F3F,
|
||||
RT_TOP_WIDGETS | HPERF_RT_TOP_TOP_WTLIMIT, 0x00000F0F,
|
||||
RT_TOP_WIDGETS | HPERF_RT_TOP_DISP0_RTLIMIT, 0x00003F3F,
|
||||
RT_TOP_WIDGETS | HPERF_RT_TOP_DISP1_RTLIMIT, 0x00001818,
|
||||
RT_TOP_WIDGETS | HPERF_RT_TOP_ISP_RTLIMIT, 0x00000C0C,
|
||||
RT_TOP_WIDGETS | HPERF_RT_TOP_ISP_WTLIMIT, 0x00001010,
|
||||
|
||||
// Configure recommended bridge settings in HPerf-RT Top
|
||||
RT_TOP_BRIDGE | HPERF_RT_TOP_AR_CHAN_ARB_MI, 0x00000000,
|
||||
RT_TOP_BRIDGE | HPERF_RT_TOP_AR_CHAN_ARB_MI, 0x01000001,
|
||||
RT_TOP_BRIDGE | HPERF_RT_TOP_AR_CHAN_ARB_MI, 0x02000002,
|
||||
0, 0,
|
||||
|
||||
0, 0
|
||||
};
|
||||
#endif // WITH_DEVICETREE || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
|
||||
|
||||
int miu_initialize_internal_ram(void)
|
||||
{
|
||||
#if APPLICATION_SECUREROM
|
||||
// Ensure that rPMGR_SCRATCH0-3 get cleared
|
||||
rPMGR_SCRATCH0 = 0;
|
||||
rPMGR_SCRATCH1 = 0;
|
||||
rPMGR_SCRATCH2 = 0;
|
||||
rPMGR_SCRATCH3 = 0;
|
||||
#endif /* APPLICATION_SECUREROM */
|
||||
|
||||
// Save the Security Epoch in the top byte of PMGR_SCRATCH0
|
||||
rPMGR_SCRATCH0 &= ~0xFF000000;
|
||||
rPMGR_SCRATCH0 |= (platform_get_security_epoch()) << 24;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int miu_init(void)
|
||||
{
|
||||
#if APPLICATION_IBOOT && !PRODUCT_IBEC
|
||||
// Verify that the Security Epoch in PMGR_SCRATCH0 matches
|
||||
if ((rPMGR_SCRATCH0 >> 24) != platform_get_security_epoch()) {
|
||||
panic("miu_init: Epoch Mismatch\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
#if APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC
|
||||
// Configure recommended transaction limits in CIF
|
||||
rCIF_RTLIMIT = 0x00000808;
|
||||
rCIF_WTLIMIT = 0x00000808;
|
||||
|
||||
// Tunables recommendation, for SCU clock-gating
|
||||
// (will change to 0x80 for <rdar://problem/8267114>)
|
||||
rCIF_IDLETMR = 0x00000010;
|
||||
#endif
|
||||
|
||||
|
||||
#if APPLICATION_SECUREROM || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
|
||||
// Configure bridges that are statically powered
|
||||
clock_gate(CLK_UPERF, true);
|
||||
clock_gate(CLK_UPERF1, true);
|
||||
miu_configure_bridge(bridge_settings_static);
|
||||
clock_gate(CLK_UPERF1, false);
|
||||
clock_gate(CLK_UPERF, false);
|
||||
#endif
|
||||
|
||||
#if APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC
|
||||
// Configure bridges that are dynamically powered
|
||||
clock_gate(CLK_HPERFNRT, true);
|
||||
clock_gate(CLK_HPERFRT, true);
|
||||
miu_configure_bridge(bridge_settings_dynamic);
|
||||
clock_gate(CLK_HPERFNRT, false);
|
||||
clock_gate(CLK_HPERFRT, false);
|
||||
|
||||
/* Enable the SCU. Note that we explicitly do NOT touch the
|
||||
* "power status" register, since the default is supposed to
|
||||
* be correct, and the real control is in the CPU's "SMP"
|
||||
* bit. */
|
||||
rSCU_TAG_INVAL = 0xff; /* invalidate SCU tags for all CPUs */
|
||||
|
||||
/* Enable SCU, standby, speculative linefills, and parity */
|
||||
rSCU_CONTROL = (1 << 5) | (1 << 3) | (1 << 2) | (1 << 0);
|
||||
#endif
|
||||
|
||||
/* remap whatever bank of ram we're in to zero */
|
||||
if (TEXT_BASE == SRAM_BASE)
|
||||
miu_select_remap(REMAP_SRAM);
|
||||
else if ((TEXT_BASE >= SDRAM_BASE) && (TEXT_BASE < SDRAM_END))
|
||||
miu_select_remap(REMAP_SDRAM);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void miu_configure_bridge(const u_int32_t *bridge_settings)
|
||||
{
|
||||
volatile u_int32_t *reg;
|
||||
u_int32_t cnt = 0, bridge, offset, data;
|
||||
|
||||
while ((bridge_settings[cnt] != 0) || (bridge_settings[cnt + 1] != 0)) {
|
||||
while ((bridge_settings[cnt] != 0) || (bridge_settings[cnt + 1] != 0)) {
|
||||
bridge = bridge_settings[cnt] >> BRIDGE_SHIFT;
|
||||
offset = bridge_settings[cnt] & BRIDGE_MASK;
|
||||
data = bridge_settings[cnt + 1];
|
||||
reg = (volatile u_int32_t *)(bridge_registers[bridge] + offset);
|
||||
*reg = data;
|
||||
cnt += 2;
|
||||
}
|
||||
cnt += 2;
|
||||
}
|
||||
}
|
||||
|
||||
void miu_suspend(void)
|
||||
{
|
||||
/* XXX ? */
|
||||
}
|
||||
|
||||
int miu_initialize_dram(bool resume)
|
||||
{
|
||||
#if APPLICATION_IBOOT
|
||||
mcu_initialize_dram(resume);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
void miu_select_remap(enum remap_select sel)
|
||||
{
|
||||
switch (sel) {
|
||||
case REMAP_SRAM:
|
||||
rREMAP_CTL = (rREMAP_CTL & ~3) | (1 << 0); // remap_sel = 1
|
||||
rPL310_FILTER_START = 0x1;
|
||||
break;
|
||||
case REMAP_SDRAM:
|
||||
rREMAP_CTL = (rREMAP_CTL & ~3) | (2 << 0); // remap_sel = 2
|
||||
// Leave low megabyte heading to DRAM for wake-from-sleep,
|
||||
// Otherwise send everything below DRAM to the PIO block.
|
||||
// Currently this is for testing only; it is not POR.
|
||||
rPL310_FILTER_END = 0x80000000;
|
||||
rPL310_FILTER_START = 0x00100001;
|
||||
break;
|
||||
}
|
||||
|
||||
/* read remap register to ensure it has been updated */
|
||||
rREMAP_CTL;
|
||||
}
|
||||
|
||||
void miu_bypass_prep(void)
|
||||
{
|
||||
#if APPLICATION_IBOOT
|
||||
extern void mcu_bypass_prep(void);
|
||||
mcu_bypass_prep();
|
||||
#endif
|
||||
}
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
void miu_update_device_tree(DTNode *pmgr_node)
|
||||
{
|
||||
u_int32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
|
||||
// Fill in the bridge-settings property
|
||||
propName = "bridge-settings";
|
||||
if (FindProperty(pmgr_node, &propName, &propData, &propSize)) {
|
||||
if (propSize >= sizeof(bridge_settings_dynamic)) {
|
||||
memcpy(propData, bridge_settings_dynamic, sizeof(bridge_settings_dynamic));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_MIU=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/miu.o
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,17 @@
|
||||
# Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_CLOCKS=1 \
|
||||
WITH_HW_PLATFORM_POWER=1 \
|
||||
WITH_HW_POWER_GATING=0
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/pmgr.o
|
||||
@@ -0,0 +1,122 @@
|
||||
# Copyright (C) 2010-2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
|
||||
# modules implied by this platform
|
||||
MODULES += \
|
||||
platform/defaults \
|
||||
platform/generic \
|
||||
arch/$(ARCH)
|
||||
|
||||
##############################################################################
|
||||
# Code running on the main CPU
|
||||
#
|
||||
ifeq ($(PLATFORM_VARIANT),)
|
||||
|
||||
ARM_CPU := cortex-a9
|
||||
|
||||
# Devmap chip ID based on sub-platform identifier
|
||||
ifeq ($(SUB_PLATFORM),s5l8945x)
|
||||
DEVMAP_CHIP_ID := 8945
|
||||
endif
|
||||
|
||||
MAX_DFU_SIZE := 180224
|
||||
|
||||
ifeq ($(TEXT_BANK),srom)
|
||||
TEXT_BASE := 0x00000000
|
||||
endif
|
||||
ifeq ($(TEXT_BANK),sram)
|
||||
TEXT_BASE := 0x34000000
|
||||
endif
|
||||
ifeq ($(TEXT_BANK),sdram)
|
||||
TEXT_BASE := 0xBFF00000
|
||||
endif
|
||||
|
||||
OPTIONS += \
|
||||
AIC_CPU_ID=0 \
|
||||
WITH_CLASSIC_SUSPEND_TO_RAM=1 \
|
||||
WITH_LEGACY_PANIC_LOGS=1 \
|
||||
WITH_NO_RANDOM_HEAP_COOKIE=1 \
|
||||
WITH_NO_RANDOM_STACK_COOKIE=1 \
|
||||
WITH_NON_COHERENT_DMA=1 \
|
||||
WITH_ROM_TRAMPOLINE=1 \
|
||||
PLATFORM_ENTROPY_RATIO=200 \
|
||||
PLATFORM_IRQ_COUNT=192 \
|
||||
TEXT_BASE="$(TEXT_BASE)" \
|
||||
TEXT_FOOTPRINT="$(TEXT_FOOTPRINT)"
|
||||
|
||||
# L2_CACHE_SIZE=1048576 \
|
||||
#
|
||||
|
||||
GLOBAL_LDFLAGS += \
|
||||
-seg1addr $(TEXT_BASE)
|
||||
|
||||
ifeq ($(APPLICATION),SecureROM)
|
||||
# This selects the start of the DATA segment and the end of the INSECURE_MEMORY area
|
||||
DATA_BASE := 0x3402C000
|
||||
|
||||
OPTIONS += \
|
||||
DATA_BASE="$(DATA_BASE)"
|
||||
|
||||
GLOBAL_LDFLAGS += \
|
||||
-segaddr __DATA $(DATA_BASE)
|
||||
endif
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/init.o
|
||||
|
||||
endif
|
||||
|
||||
##############################################################################
|
||||
# Code running on the IOP
|
||||
#
|
||||
ifeq ($(PLATFORM_VARIANT),IOP)
|
||||
|
||||
OPTIONS += \
|
||||
PLATFORM_VARIANT_IOP=1 \
|
||||
AIC_CPU_ID=2 \
|
||||
WITH_PLATFORM_HALT=1 \
|
||||
SUPPORT_SLEEP=1 \
|
||||
WITH_IOP_POWER_GATING=1 \
|
||||
DEEP_IDLE_THRESHOLD_US=10000
|
||||
|
||||
ARM_CPU := cortex-a5
|
||||
|
||||
TEXT_BASE := 0x0
|
||||
|
||||
OPTIONS += \
|
||||
TEXT_BASE="$(TEXT_BASE)" \
|
||||
SUPPORT_SLEEP=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/iop_init.o
|
||||
endif
|
||||
|
||||
##############################################################################
|
||||
# Code running on the audio engine
|
||||
#
|
||||
ifeq ($(PLATFORM_VARIANT),Audio)
|
||||
|
||||
OPTIONS += \
|
||||
PLATFORM_VARIANT_AUDIO=1 \
|
||||
WITH_PLATFORM_HALT=1
|
||||
|
||||
ARM_CPU := cortex-a5
|
||||
|
||||
TEXT_BASE := 0x0
|
||||
|
||||
OPTIONS += \
|
||||
TEXT_BASE="$(TEXT_BASE)" \
|
||||
TEXT_FOOTPRINT="$(TEXT_FOOTPRINT)" \
|
||||
SUPPORT_SLEEP=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/iop_init.o
|
||||
|
||||
endif
|
||||
Reference in new issue
Block a user