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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include SUB_PLATFORM_HEADER(amcconfig)
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@@ -0,0 +1,106 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#if WITH_TARGET_AMC_PARAMS
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#include <target/amcconfig.h>
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#else
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static const struct amc_param amc_params = {
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.lat = 0x00060300,
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.phyrdwrtim = 0x00020a04,
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.tREFi = 0x5d,
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.pdn = 0x22000403,
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.derate = 0x24831359,
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.read = 0x00000203,
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.bustat = 0x00222209,
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.bustat2 = 0x00222209,
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.pwrmngten_default = 0x00100100,
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.schen_default = 0x00001110,
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.mcphyupdate = 0x15030000,
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.mcphyupdate1 = 0x00000003,
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.arefparam = 0x0ca2b532,
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.longsr = 0x05022008,
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.mr1 = 0x44,
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.mr2 = 0x1a,
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.mr3 = 0x03,
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.addrcfg = 0x00020201,
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.mccchnldec = 0x00050010,
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.mcuchnhash = 0x0ffffd54,
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.mcschnldec = 0x00010200,
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.qbrparam = 0x00050200,
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.odts = 0x00000320,
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.addrmapmode = 0x00000601,
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.readleveling = 0x00000300,
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.freq = {
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{ // 800MHz
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.cas = 0x00000308,
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.pch = 0x00030612,
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.act = 0x12040908,
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.autoref = 0x19350000,
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.selfref = 0x00039060,
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.modereg = 0x20250782,
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},
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{ // 400MHz
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.cas = 0x00000005,
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.pch = 0x00000009,
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.act = 0x09020505,
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.autoref = 0x0d1b0000,
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.selfref = 0x0001d000,
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.modereg = 0x00130000,
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},
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{ // 200MHz
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.cas = 0x00000003,
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.pch = 0x00000005,
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.act = 0x05010303,
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.autoref = 0x070e0000,
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.selfref = 0x0000f000,
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.modereg = 0x000a0000,
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},
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{ // 50MHz
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.cas = 0x00000002,
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.pch = 0x00000002,
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.act = 0x04010202,
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.autoref = 0x02040000,
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.selfref = 0x00004000,
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.modereg = 0x00030000,
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}
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}
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};
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static const struct amc_tunable amc_tunables[] = {
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{ &rAMC_MCSARBCFG, 0x00000001 },
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{ &rAMC_OPIDLETMR, 0x00200000 },
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{ &rAMC_OPTMRADJPARAM, 0x20400064 },
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{ &rAMC_MIFACTSCH, 0x00000001 },
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{ &rAMC_MIFCASSCH_FREQ(0), 0x10000010 },
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{ &rAMC_PSQRQCTL0, 0xff010110 },
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{ &rAMC_PSQRQCTL1, 0x00001700 },
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{ &rAMC_PSQRQTIMER0, 0x00000040 },
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{ &rAMC_PSQRQTIMER1, 0x00000014 },
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{ &rAMC_PSQRQTIMER2, 0x00000040 },
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{ &rAMC_PSQRQBRST, 0x04100410 },
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{ &rAMC_PSQRQSCHCRD, 0x00101400 },
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{ &rAMC_PSQWQCTL0, 0x00010100 },
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#if DISPLAY_D600_TUNABLES
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{ &rAMC_PSQWQCTL1, 0x00000bd4 },
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#else
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{ &rAMC_PSQWQCTL1, 0x00000158 },
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#endif
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{ &rAMC_PSQWQBRST, 0x04080410 },
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{ &rAMC_PSQWQSCHCRD, 0x00101400 },
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{ &rAMC_MCUQOSLLT, 0x0000011f },
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#if DISPLAY_D600_TUNABLES
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{ &rAMC_PWRMNGTPARAM, 0x0c003000 },
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#else
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{ &rAMC_PWRMNGTPARAM, 0x01803000 },
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#endif
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};
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#endif
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@@ -0,0 +1,99 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#if WITH_TARGET_AMC_PARAMS
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#include <target/amcconfig.h>
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#else
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static const struct amc_param amc_params = {
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.lat = 0x00060300,
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.phyrdwrtim = 0x00020a04,
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.tREFi = 0x5d,
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.pdn = 0x22000403,
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.derate = 0x24831359,
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.read = 0x00000203,
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.bustat = 0x00222209,
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.bustat2 = 0x00222209,
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.pwrmngten_default = 0x00100100,
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.schen_default = 0x00001110,
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.mcphyupdate = 0x15030000,
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.mcphyupdate1 = 0x00000003,
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.arefparam = 0x0ca2b532,
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.longsr = 0x05022008,
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.mr1 = 0x44,
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.mr2 = 0x1a,
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.mr3 = 0x02,
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.addrcfg = 0x00020201,
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.mccchnldec = 0x00050020,
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.mcuchnhash = 0x0ffffd54,
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.mcuchnhash2 = 0x0aaaaaa8,
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.mcschnldec = 0x00020200,
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.qbrparam = 0x00050200,
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.odts = 0x00000320,
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.addrmapmode = 0x00000501,
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.readleveling = 0x00000300,
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.freq = {
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{ // 800MHz
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.cas = 0x00000308,
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.pch = 0x00030612,
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.act = 0x12040908,
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.autoref = 0x19350000,
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.selfref = 0x00039060,
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.modereg = 0x20250782,
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},
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{ // 400MHz
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.cas = 0x00000005,
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.pch = 0x00000009,
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.act = 0x09020505,
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.autoref = 0x0d1b0000,
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.selfref = 0x0001d000,
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.modereg = 0x00130000,
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},
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{ // 200MHz
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.cas = 0x00000003,
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.pch = 0x00000005,
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.act = 0x05010303,
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.autoref = 0x070e0000,
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.selfref = 0x0000f000,
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.modereg = 0x000a0000,
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},
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{ // 50MHz
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.cas = 0x00000002,
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.pch = 0x00000002,
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.act = 0x04010202,
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.autoref = 0x02040000,
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.selfref = 0x00004000,
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.modereg = 0x00030000,
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}
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}
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};
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static const struct amc_tunable amc_tunables[] = {
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{ &rAMC_MCSARBCFG, 0x00000001 },
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{ &rAMC_OPIDLETMR, 0x00200000 },
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{ &rAMC_OPTMRADJPARAM, 0x20400064 },
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{ &rAMC_MIFACTSCH, 0x00000001 },
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{ &rAMC_MIFCASSCH_FREQ(0), 0x10000010 },
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{ &rAMC_PSQRQCTL0, 0xff010110 },
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{ &rAMC_PSQRQCTL1, 0x00001700 },
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{ &rAMC_PSQRQTIMER0, 0x00000040 },
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{ &rAMC_PSQRQTIMER1, 0x00000014 },
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{ &rAMC_PSQRQTIMER2, 0x00000040 },
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{ &rAMC_PSQRQBRST, 0x04100410 },
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{ &rAMC_PSQRQSCHCRD, 0x00101400 },
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{ &rAMC_PSQWQCTL0, 0x00010100 },
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{ &rAMC_PSQWQCTL1, 0x00000336 },
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{ &rAMC_PSQWQBRST, 0x04080410 },
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{ &rAMC_PSQWQSCHCRD, 0x00101400 },
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{ &rAMC_MCUQOSLLT, 0x0000011f },
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{ &rAMC_PWRMNGTPARAM, 0x03523000 },
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};
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#endif
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@@ -0,0 +1,52 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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/*
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* The amc_phy_params struct is defined in drivers/apple/amp_v3/amp_v3.h, and this
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* file should only by included from amp_v3.c.
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*/
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#if WITH_TARGET_AMP_PARAMS
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#include <target/ampconfig.h>
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#else
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static const struct amp_params amc_phy_params = {
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.freq = {
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{
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.caoutdllscl = 0x00000008,
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.dqsindllscl = 0x00000008,
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.rdcapcfg = 0x0101050f,
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},
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{
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.caoutdllscl = 0x00000010,
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.dqsindllscl = 0x00000010,
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.rdcapcfg = 0x21010509,
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},
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{
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.caoutdllscl = 0x00000020,
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.dqsindllscl = 0x00000020,
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.rdcapcfg = 0x41010506,
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},
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{
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.caoutdllscl = 0x0000003f,
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.dqsindllscl = 0x0000003f,
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.rdcapcfg = 0x61010504,
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},
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},
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#if SUB_PLATFORM_T7000
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.dqdqsds = 0x00001212,
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.nondqds = 0x12124a52,
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#else
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.dqdqsds = 0x00001414,
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.nondqds = 0x14145294,
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#endif
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.ampclk = 0x00010000,
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};
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#endif
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@@ -0,0 +1,94 @@
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/*
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* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef _APCIE_REGS_H
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#define _APCIE_REGS_H
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#include <platform/soc/hwregbase.h>
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#define APCIE_COUNTER_PORT_STRIDE (0x40)
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#define APCIE_NUM_COUNTERS (8)
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#define rAPCIE_COUNTER_VALUE(port, n) (*(volatile uint32_t *)(APCIE_COUNTER_BASE_ADDR + (port) * APCIE_COUNTER_PORT_STRIDE + (n) * 4))
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#define rAPCIE_COUNTER_COMMAND(port) (*(volatile uint32_t *)(APCIE_COUNTER_BASE_ADDR + (port) * APCIE_COUNTER_PORT_STRIDE + 0x20))
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#define APCIE_COUNTER_ENABLE (1)
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#define APCIE_COUNTER_CLEAR (2)
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#define APCIE_COUNTER_CAPTURE (4)
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#define APCIE_PORT_BASE_ADDR(port) (APCIE_CONFIG_BASE_ADDR + APCIE_CONFIG_PORT_STRIDE * (port))
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#define rAPCIE_CONFIG_LINKCFG(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x080))
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#define rAPCIE_CONFIG_LINKCTRL(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x084))
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#define rAPCIE_CONFIG_LINKSTS(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x088))
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#define rAPCIE_CONFIG_PMETO(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x08c))
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#define rAPCIE_CONFIG_PMETOACK_TMOTLIM(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x090))
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#define rAPCIE_CONFIG_LTR_THRESH(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x098))
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#define rAPCIE_CONFIG_INBCTRL(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x130))
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#define rAPCIE_CONFIG_OUTBCTRL(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x134))
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#define rAPCIE_CONFIG_LINKPMGRSTS(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x804))
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#define rAPCIE_CONFIG_LINKCDMSTS(port) (*(volatile uint32_t *)(APCIE_PORT_BASE_ADDR(port) + 0x808))
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#define APCIE_CONFIG_LINKCFG_LTSSM_EN (1 << 0)
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#define APCIE_CONFIG_LINKSTS_LINK_STATUS (1 << 0)
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#define APCIE_CONFIG_LINKSTS_CORE_RST_PEND (1 << 1)
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#define APCIE_CONFIG_LINKSTS_PIPE_CLK_ACTIVE (1 << 2)
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#define APCIE_CONFIG_LINKSTS_CLKREQ_N (1 << 3)
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#define APCIE_CONFIG_LINKSTS_L1_STATE (1 << 4)
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#define APCIE_CONFIG_LINKSTS_L1_SUBSTATE (1 << 5)
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#define APCIE_CONFIG_LINKSTS_L2_STATE (1 << 6)
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#define APCIE_CONFIG_INBCTRL_CPL_MUST_PUSH_EN (1 << 1)
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#define APCIE_CONFIG_OUTBCTRL_EARLY_PT_RESP_EN (1 << 0)
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#define rAPCIE_CONFIG_SPACE8(port, offset) (*(volatile uint8_t *)(PCI_CONFIG_BASE + ((port) << PCI_DEVICE_SHIFT) + (offset)))
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#define rAPCIE_CONFIG_SPACE16(port, offset) (*(volatile uint16_t *)(PCI_CONFIG_BASE + ((port) << PCI_DEVICE_SHIFT) + (offset)))
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#define rAPCIE_CONFIG_SPACE32(port, offset) (*(volatile uint32_t *)(PCI_CONFIG_BASE + ((port) << PCI_DEVICE_SHIFT) + (offset)))
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#define rAPCIE_PCIE_CAP_LINK_CONTROL2(port) rAPCIE_CONFIG_SPACE16(port, 0xa0)
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#define rAPCIE_PORT_LOGIC_PORT_LINK_CTRL(port) rAPCIE_CONFIG_SPACE32(port, 0x710)
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#define rAPCIE_PORT_LOGIC_GEN2_CTRL(port) rAPCIE_CONFIG_SPACE32(port, 0x80c)
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#if SUB_PLATFORM_T7000
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#define APCIE_V1_0_COMMON_BASE_ADDR (PCI_REG_BASE)
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#define rAPCIE_V1_0_PORT_CTRL (*(volatile uint32_t *)(APCIE_V1_0_COMMON_BASE_ADDR + 0x04))
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#define rAPCIE_V1_0_APP_ACG_CTRL (*(volatile uint32_t *)(APCIE_V1_0_COMMON_BASE_ADDR + 0x08))
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#define rAPCIE_V1_0_RST_CTRL (*(volatile uint32_t *)(APCIE_V1_0_COMMON_BASE_ADDR + 0x0c))
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#define rAPCIE_V1_0_PORT_PERST_CTRL(n) (*(volatile uint32_t *)(APCIE_V1_0_COMMON_BASE_ADDR + 0x10 + 4 * n))
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#define rAPCIE_V1_0_AUXCLK_CTRL (*(volatile uint32_t *)(APCIE_V1_0_COMMON_BASE_ADDR + 0x20))
|
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#define rAPCIE_V1_0_REFCLK_CTRL (*(volatile uint32_t *)(APCIE_V1_0_COMMON_BASE_ADDR + 0x24))
|
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#define rAPCIE_V1_0_NANDSYSCLK_CTRL (*(volatile uint32_t *)(APCIE_V1_0_COMMON_BASE_ADDR + 0x28))
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#define rAPCIE_V1_0_CLKREQ_OVERRIDE_CTRL (*(volatile uint32_t *)(APCIE_V1_0_COMMON_BASE_ADDR + 0x30))
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||||
#define rAPCIE_V1_0_PIPE_OVERRIDE_CTRL (*(volatile uint32_t *)(APCIE_V1_0_COMMON_BASE_ADDR + 0x34))
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#define rAPCIE_V1_0_PIPE_OVERRIDE_VAL0 (*(volatile uint32_t *)(APCIE_V1_0_COMMON_BASE_ADDR + 0x38))
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#define rAPCIE_V1_0_PIPE_OVERRIDE_VAL1 (*(volatile uint32_t *)(APCIE_V1_0_COMMON_BASE_ADDR + 0x3c))
|
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#define APCIE_V1_0_PORT_CTRL_PORT_EN0 (1 << 0)
|
||||
#define APCIE_V1_0_PORT_CTRL_PORT_EN1 (1 << 1)
|
||||
#define APCIE_V1_0_PORT_CTRL_NVME_EN0 (1 << 8)
|
||||
#define APCIE_V1_0_PORT_CTRL_AUTO_DIS0 (1 << 16)
|
||||
#define APCIE_V1_0_PORT_CTRL_AUTO_DIS1 (1 << 17)
|
||||
|
||||
#define APCIE_V1_0_RST_CTRL_PHY01_SW_RESET (1 << 0)
|
||||
|
||||
#define APCIE_V1_0_PIPE_OVERRIDE_CTRL_EN0 (1 << 0)
|
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#define APCIE_V1_0_PIPE_OVERRIDE_CTRL_EN1 (1 << 1)
|
||||
|
||||
#define APCIE_V1_0_REFCLK_CTRL_REFCLK_EN0 (1 << 0)
|
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#define APCIE_V1_0_REFCLK_CTRL_REFCLK_EN1 (1 << 1)
|
||||
#define APCIE_V1_0_REFCLK_CTRL_REFCLK_AUTO_DIS0 (1 << 8)
|
||||
#define APCIE_V1_0_REFCLK_CTRL_REFCLK_AUTO_DIS1 (1 << 9)
|
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|
||||
#endif // SUB_PLATFORM_T7000
|
||||
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||||
#endif /* _APCIE_REGS_H */
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@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_ERROR_HANDLER_H
|
||||
#define __PLATFORM_ERROR_HANDLER_H
|
||||
|
||||
void platform_enable_error_handler();
|
||||
|
||||
#endif // __PLATFORM_ERROR_HANDLER_H
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_GPIODEF_H
|
||||
#define __PLATFORM_GPIODEF_H
|
||||
|
||||
#include <platform.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#if WITH_TARGET_CONFIG
|
||||
# include <target/gpiodef.h>
|
||||
#endif
|
||||
|
||||
#include SUB_PLATFORM_HEADER(gpiodef)
|
||||
|
||||
#endif /* ! __PLATFORM_GPIODEF_H */
|
||||
@@ -0,0 +1,78 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_GPIODEF_T7000_H
|
||||
#define __PLATFORM_GPIODEF_T7000_H
|
||||
|
||||
#if !SUB_PLATFORM_T7000
|
||||
#error "Only include for T7000 platform"
|
||||
#endif
|
||||
|
||||
/* T7000 specific gpio -> pin mappings - Fiji I/O Spreadsheet v9.3 */
|
||||
|
||||
/* define platform-specific gpios in a generic fashion here. */
|
||||
#define GPIO_BOARD_ID0 GPIO( 7, 4) // 60 - Alias of GPIO_SPI0_SCLK
|
||||
#define GPIO_BOARD_ID1 GPIO( 7, 5) // 61 - Alias of GPIO_SPI0_MOSI
|
||||
#define GPIO_BOARD_ID2 GPIO( 7, 6) // 62 - Alias of GPIO_SPI0_MISO
|
||||
#define GPIO_BOARD_ID3 GPIO( 6, 4) // 52
|
||||
#define GPIO_BOARD_ID4 GPIO( 8, 6) // 70
|
||||
|
||||
/* Boot configuration pins */
|
||||
#define GPIO_BOOT_CONFIG0 GPIO( 6, 6) // 54
|
||||
#define GPIO_BOOT_CONFIG1 GPIO( 8, 4) // 68
|
||||
#define GPIO_BOOT_CONFIG2 GPIO( 8, 5) // 69
|
||||
|
||||
/* Boot configuration pin encodings */
|
||||
#define BOOT_CONFIG_SPI0 0
|
||||
#define BOOT_CONFIG_SPI0_TEST 1
|
||||
#define BOOT_CONFIG_ANS 2
|
||||
#define BOOT_CONFIG_ANS_TEST 3
|
||||
#define BOOT_CONFIG_NVME0 4
|
||||
#define BOOT_CONFIG_NVME0_TEST 5
|
||||
// #define BOOT_CONFIG_UNUSED 6
|
||||
#define BOOT_CONFIG_FAST_SPI0_TEST 7
|
||||
|
||||
#define GPIO_REQUEST_DFU1 GPIO( 4, 1) // 33 - formerly known as HOLD_KEY
|
||||
#define GPIO_REQUEST_DFU2 GPIO( 4, 0) // 32 - formerly known as MENU_KEY
|
||||
#define GPIO_FORCE_DFU GPIO(13, 4) // 108
|
||||
#define GPIO_DFU_STATUS GPIO(13, 5) // 109
|
||||
|
||||
#define SPI_NOR0 (0)
|
||||
|
||||
#define GPIO_SPI0_SCLK GPIO( 7, 4) // 60
|
||||
#define GPIO_SPI0_MOSI GPIO( 7, 5) // 61
|
||||
#define GPIO_SPI0_MISO GPIO( 7, 6) // 62
|
||||
#define GPIO_SPI0_SSIN GPIO( 7, 7) // 63
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define GPIO_SPI0_CS GPIO(GPIO_PAD_SPI, 0)
|
||||
#else
|
||||
#define GPIO_SPI0_CS GPIO( 7, 7) // 63 - Alias of GPIO_SPI0_SSIN
|
||||
#endif
|
||||
|
||||
#define GPIO_IIC0_SCL GPIO(12, 1) // 97
|
||||
#define GPIO_IIC0_SDA GPIO(12, 0) // 96
|
||||
#define GPIO_IIC1_SCL GPIO(17, 3) // 139
|
||||
#define GPIO_IIC1_SDA GPIO(17, 2) // 138
|
||||
#define GPIO_IIC2_SCL GPIO( 8, 1) // 65
|
||||
#define GPIO_IIC2_SDA GPIO( 8, 0) // 64
|
||||
#define GPIO_IIC3_SCL GPIO(10, 7) // 87
|
||||
#define GPIO_IIC3_SDA GPIO(10, 6) // 86
|
||||
|
||||
#define GPIO_PCIE0_PERST GPIO( 9, 3) // 75
|
||||
#define GPIO_PCIE0_CLKREQ GPIO( 5, 0) // 40
|
||||
#define GPIO_PCIE1_PERST GPIO( 9, 5) // 77
|
||||
#define GPIO_PCIE1_CLKREQ GPIO( 5, 1) // 41
|
||||
|
||||
#define GPIO_S3E_RESETN GPIO( 1, 1) // 9
|
||||
#define GPIO_NAND_SYS_CLK GPIO( 5, 2) // 42
|
||||
|
||||
#endif /* ! __PLATFORM_GPIODEF_T7000_H */
|
||||
@@ -0,0 +1,93 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_GPIODEF_T7001_H
|
||||
#define __PLATFORM_GPIODEF_T7001_H
|
||||
|
||||
#if !SUB_PLATFORM_T7001
|
||||
#error "Only include for T7001 platform"
|
||||
#endif
|
||||
|
||||
/* T7001 specific gpio -> pin mappings - Capri I/O Spreadsheet v10.29 */
|
||||
|
||||
/* define platform-specific gpios in a generic fashion here. */
|
||||
#define GPIO_BOARD_ID0 GPIO( 8, 3) // 67 - Alias of GPIO_SPI0_SCLK
|
||||
#define GPIO_BOARD_ID1 GPIO( 8, 4) // 68 - Alias of GPIO_SPI0_MOSI
|
||||
#define GPIO_BOARD_ID2 GPIO( 8, 5) // 69 - Alias of GPIO_SPI0_MISO
|
||||
#define GPIO_BOARD_ID3 GPIO( 12, 0) // 96
|
||||
#define GPIO_BOARD_ID4 GPIO( 13, 5) // 109
|
||||
|
||||
/* Boot configuration pins */
|
||||
#define GPIO_BOOT_CONFIG0 GPIO( 12, 2) // 98
|
||||
#define GPIO_BOOT_CONFIG1 GPIO( 13, 1) // 105
|
||||
#define GPIO_BOOT_CONFIG2 GPIO( 13, 4) // 108
|
||||
#define GPIO_BOOT_CONFIG3 GPIO( 13, 7) // 111
|
||||
|
||||
/* Boot configuration pin encodings */
|
||||
#define BOOT_CONFIG_SPI0 0
|
||||
#define BOOT_CONFIG_SPI0_TEST 1
|
||||
#define BOOT_CONFIG_ANS 2
|
||||
#define BOOT_CONFIG_ANS_TEST 3
|
||||
#define BOOT_CONFIG_NVME0 4
|
||||
#define BOOT_CONFIG_NVME0_TEST 5
|
||||
#define BOOT_CONFIG_LOW_POWER_ANS 6
|
||||
#define BOOT_CONFIG_FAST_SPI0_TEST 7
|
||||
#define BOOT_CONFIG_NVME1 8
|
||||
#define BOOT_CONFIG_NVME1_TEST 9
|
||||
|
||||
#define BOOT_CONFIG_TBT0_EXTREF 10
|
||||
#define BOOT_CONFIG_TBT0_EXTREF_TEST 11
|
||||
#define BOOT_CONFIG_TBT0_INTREF 12
|
||||
#define BOOT_CONFIG_TBT0_INTREF_TEST 13
|
||||
|
||||
#define GPIO_REQUEST_DFU1 GPIO( 0, 1) // 1 - HOLD_KEY
|
||||
#define GPIO_REQUEST_DFU2 GPIO( 0, 0) // 0 - MENU_KEY
|
||||
#define GPIO_FORCE_DFU GPIO(13, 2) // 106
|
||||
#define GPIO_DFU_STATUS GPIO(13, 3) // 107
|
||||
|
||||
#define SPI_NOR0 (0)
|
||||
|
||||
#define GPIO_SPI0_SCLK GPIO( 8, 3) // 67
|
||||
#define GPIO_SPI0_MOSI GPIO( 8, 4) // 68
|
||||
#define GPIO_SPI0_MISO GPIO( 8, 5) // 69
|
||||
#define GPIO_SPI0_SSIN GPIO( 8, 6) // 70
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define GPIO_SPI0_CS GPIO(GPIO_PAD_SPI, 0)
|
||||
#else
|
||||
#define GPIO_SPI0_CS GPIO( 8, 6) // 70 - Alias of GPIO_SPI0_SSIN
|
||||
#endif
|
||||
|
||||
#define GPIO_IIC0_SCL GPIO(4, 6) // 38
|
||||
#define GPIO_IIC0_SDA GPIO(4, 5) // 37
|
||||
#define GPIO_IIC1_SCL GPIO(8, 2) // 66
|
||||
#define GPIO_IIC1_SDA GPIO(8, 1) // 65
|
||||
#define GPIO_IIC2_SCL GPIO( 16, 5) // 133
|
||||
#define GPIO_IIC2_SDA GPIO( 16, 4) // 132
|
||||
#define GPIO_IIC3_SCL GPIO(16, 7) // 135
|
||||
#define GPIO_IIC3_SDA GPIO(16, 6) // 134
|
||||
|
||||
#define GPIO_PCIE0_PERST GPIO( 22, 2) // 178
|
||||
#define GPIO_PCIE0_CLKREQ GPIO( 21, 5) // 173
|
||||
#define GPIO_PCIE1_PERST GPIO( 22, 3) // 179
|
||||
#define GPIO_PCIE1_CLKREQ GPIO( 21, 6) // 174
|
||||
#define GPIO_PCIE2_PERST GPIO( 22, 4) // 180
|
||||
#define GPIO_PCIE2_CLKREQ GPIO( 21, 7) // 175
|
||||
#define GPIO_PCIE3_PERST GPIO( 22, 5) // 181
|
||||
#define GPIO_PCIE3_CLKREQ GPIO( 22, 0) // 176
|
||||
|
||||
#define GPIO_PCIE_PHY01_CLKREQ GPIO( 21, 1) // 169
|
||||
#define GPIO_PCIE_PHY23_CLKREQ GPIO( 21, 0) // 168
|
||||
|
||||
#define GPIO_S3E_RESETN GPIO( 20, 7) // 167
|
||||
#define GPIO_NAND_SYS_CLK GPIO( 22, 1) // 177
|
||||
|
||||
#endif /* ! __PLATFORM_GPIODEF_T7001_H */
|
||||
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_IMAGE_DEVICES_H
|
||||
#define __PLATFORM_IMAGE_DEVICES_H
|
||||
|
||||
static const struct image_device platform_image_devices[] = {
|
||||
#if defined(WITH_HW_ASP)
|
||||
{ "asp_fw", 0x00000 },
|
||||
#elif defined(WITH_ANC_FIRMWARE)
|
||||
{ "anc_firmware", 0x00000 },
|
||||
#endif
|
||||
#if defined(WITH_NVME)
|
||||
{ "nvme_firmware0", 0x0000 },
|
||||
#endif
|
||||
#if !defined(WITH_HW_ASP) && !defined(WITH_ANC_FIRMWARE) && !defined(WITH_NVME)
|
||||
{ "nor0", 0x00000 },
|
||||
#endif
|
||||
};
|
||||
|
||||
#if WITH_SYSCFG
|
||||
static const struct image_device platform_syscfg_devices[] = {
|
||||
#if defined(WITH_NAND_BOOT)
|
||||
{ "nand_syscfg", 0x00000 },
|
||||
#endif
|
||||
#if defined(WITH_NVME)
|
||||
{ "nvme_syscfg0", 0x0000 },
|
||||
#endif
|
||||
#if !defined(WITH_NAND_BOOT) && !defined(WITH_NVME)
|
||||
{ "nor0", 0x00000 },
|
||||
#endif
|
||||
};
|
||||
#endif /* WITH_SYSCFG */
|
||||
|
||||
#endif /* ! __PLATFORM_IMAGE_DEVICES_H */
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_MEMCONFIG_H
|
||||
#define __PLATFORM_MEMCONFIG_H
|
||||
|
||||
/* T7000 SoC Mem Pin Configuration */
|
||||
|
||||
static const gpio_t memory_interface_gpios[] = {
|
||||
/* Not needed */
|
||||
};
|
||||
#endif /* ! __PLATFORM_MEMCONFIG_H */
|
||||
@@ -0,0 +1,245 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_MEMMAP_H
|
||||
#define __PLATFORM_MEMMAP_H
|
||||
|
||||
#include <platform/memmap_defaults.h>
|
||||
|
||||
/* T7000 specific memory map (explicit addresses assume standard defaults) */
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
// 0x800000000 + dram_size -------------------------------
|
||||
// | ASP (varies) |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | TZ1 (512KiB) |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | Consistent Debug (4KiB) |
|
||||
// |-----------------------------|
|
||||
// | Sleep Token Buffer (4KiB) |
|
||||
// |-----------------------------|
|
||||
// | Panic (512KiB) |
|
||||
// |-----------------------------|
|
||||
// | Display |
|
||||
// | (Framebuffer + scratch) |
|
||||
// | |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | |
|
||||
// | iBoot (Heap) |
|
||||
// | (Variable size depending |
|
||||
// (Capri) (Fiji) | on DISPLAY_SIZE) |
|
||||
// 0x870180000 / 0x830180000 --> |-----------------------------|
|
||||
// | iBoot (Stacks) |
|
||||
// (Capri) (Fiji) | (STACKS_SIZE) |
|
||||
// 0x87017C000 / 0x83017C000 --> |-----------------------------|
|
||||
// | iBoot (Page Tables) |
|
||||
// (Capri) (Fiji) | (PAGE_TABLES_SIZE) |
|
||||
// 0x870100000 / 0x830100000 --> |-----------------------------|
|
||||
// | iBoot (Text + Data) |
|
||||
// (Capri) (Fiji) | (TEXT_FOOTPRINT) |
|
||||
// 0x870000000 / 0x830000000 --> |-----------------------------| <-- 0x800000000 + dram_size - 256MB
|
||||
// | |
|
||||
// | Unused |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | |
|
||||
// | (Ramdisk) |
|
||||
// | (Kernel + DeviceTree) |
|
||||
// | Secure memory |
|
||||
// | |
|
||||
// |-----------------------------|
|
||||
// | |
|
||||
// | Load region / |
|
||||
// | Insecure Memory |
|
||||
// | (overlaps with TZ0) | |-----------------------------|
|
||||
// | | | TZ0 (varies) |
|
||||
// 0x800000000 --> ------------------------------- -------------------------------
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define SDRAM_BASE (0x800000000ULL)
|
||||
#define SDRAM_BANK_LEN (SDRAM_LEN)
|
||||
#define SDRAM_BANK_COUNT (1)
|
||||
#define SDRAM_END (SDRAM_BASE + SDRAM_LEN)
|
||||
|
||||
// We'll map the DRAM uncached at the end of the cached mapping
|
||||
#define SDRAM_BASE_UNCACHED (SDRAM_END)
|
||||
|
||||
#define VROM_BASE (0x100000000ULL)
|
||||
#define VROM_BANK_LEN (0x00100000ULL)
|
||||
#define VROM_LEN (0x00080000ULL)
|
||||
#define VROM_RSVD (0x00100000ULL) // 512 KiB reserved for SecureROM testing, remaining 512 KiB for Data and book-keeping
|
||||
#define SRAM_BASE (0x180000000ULL)
|
||||
#if SUB_PLATFORM_T7000 && SUPPORT_FPGA
|
||||
#define SRAM_LEN (0x000200000ULL) // 2 MiB
|
||||
#else
|
||||
#define SRAM_LEN (0x000400000ULL) // 4 MiB
|
||||
#endif
|
||||
#define SRAM_BANK_LEN (SRAM_LEN)
|
||||
#define SRAM_BANK_COUNT (1)
|
||||
#define SRAM_END (SRAM_BASE + SRAM_LEN)
|
||||
|
||||
#define IO_BASE (0x200000000ULL)
|
||||
#define IO_SIZE (0x10000000ULL)
|
||||
|
||||
#define PCI_REG_BASE (0x600000000ULL)
|
||||
#define PCI_REG_LEN (0x6000000ULL)
|
||||
#define PCI_CONFIG_BASE (0x610000000ULL)
|
||||
#define PCI_CONFIG_LEN (0x10000000ULL)
|
||||
#define PCI_32BIT_BASE (0x7C0000000ULL)
|
||||
#define PCI_32BIT_LEN (0x2000000ULL) // 32 MiB fits nicely into a 32 MiB L2 MMU block
|
||||
|
||||
#define SECUREROM_LOAD_ADDRESS (VROM_BASE)
|
||||
|
||||
/* reserved for ASP */
|
||||
// NOTE ASP_SIZE is now defined by the platform or target makefile.
|
||||
#define ASP_BASE (SDRAM_END - (ASP_SIZE))
|
||||
|
||||
// Reserved for TZ1/AP Monitor
|
||||
#define TZ1_SIZE (0x00080000ULL)
|
||||
#define TZ1_BASE (ASP_BASE - TZ1_SIZE)
|
||||
|
||||
#define CONSISTENT_DEBUG_SIZE (0x00004000ULL)
|
||||
#define CONSISTENT_DEBUG_BASE (TZ1_BASE - CONSISTENT_DEBUG_SIZE)
|
||||
|
||||
/* reserved area for sleep token info */
|
||||
#define SLEEP_TOKEN_BUFFER_SIZE (0x00001000ULL)
|
||||
#define SLEEP_TOKEN_BUFFER_BASE (CONSISTENT_DEBUG_BASE - SLEEP_TOKEN_BUFFER_SIZE)
|
||||
|
||||
/* reserved area for panic info */
|
||||
#define PANIC_SIZE (0x00080000ULL)
|
||||
#define PANIC_BASE (SLEEP_TOKEN_BUFFER_BASE - PANIC_SIZE)
|
||||
|
||||
/* reserved area for display */
|
||||
// DISPLAY_SIZE comes from platform's rules.mk
|
||||
#define DISPLAY_BASE (PANIC_BASE - DISPLAY_SIZE)
|
||||
|
||||
// Reserved for TZ0/SEP
|
||||
// TZ0_SIZE is defined by the platform or target makefile
|
||||
#define TZ0_BASE (SDRAM_BASE)
|
||||
|
||||
/* where to stick heap and insecure memory */
|
||||
#if APPLICATION_SECUREROM
|
||||
|
||||
#define DATA_SIZE (0x00040000ULL)
|
||||
|
||||
#define BOOK_KEEPING_BASE (DATA_BASE + DATA_SIZE)
|
||||
#define BOOK_KEEPING_SIZE (0x00020000ULL)
|
||||
|
||||
#define BOOT_TRAMPOLINE_BASE (BOOK_KEEPING_BASE + BOOK_KEEPING_SIZE)
|
||||
#define BOOT_TRAMPOLINE_SIZE (0x1000ULL)
|
||||
|
||||
#define HEAP_BASE (SRAM_BASE + VROM_RSVD)
|
||||
#if !SUPPORT_FPGA
|
||||
#define HEAP_SIZE (0x00100000ULL)
|
||||
#else
|
||||
#define HEAP_SIZE (0x00080000ULL)
|
||||
#endif
|
||||
#define HEAP_END (HEAP_BASE + HEAP_SIZE)
|
||||
|
||||
#define INSECURE_MEMORY_SIZE (0x00080000ULL)
|
||||
#define INSECURE_MEMORY_BASE (SRAM_BASE + SRAM_LEN - INSECURE_MEMORY_SIZE)
|
||||
|
||||
#endif /* APPLICATION_SECUREROM */
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
|
||||
#if WITH_DFU_MODE
|
||||
/* LLB, iBSS DFU */
|
||||
|
||||
/* reserved area for iBoot */
|
||||
#define IBOOT_SIZE (0x01400000ULL)
|
||||
#define IBOOT_BASE (DISPLAY_BASE - IBOOT_SIZE)
|
||||
|
||||
#define INSECURE_MEMORY_SIZE (IBOOT_SIZE)
|
||||
#define INSECURE_MEMORY_BASE (IBOOT_BASE)
|
||||
|
||||
// SRAM memory map will usually look like the following:
|
||||
//
|
||||
// ROM Testing 0x000000 - 0x100000 (1024 KiB)
|
||||
// Heap 0x100000 - 0x1FEFFF (1020 KiB)
|
||||
// Guard 0x1FF000 - 0x1FFFFF ( 4 KiB)
|
||||
// Unused 0x200000 - 0x37FFFF (1536 KiB)
|
||||
// Code/Data 0x380000 - 0x3DFFFF ( 384 KiB)
|
||||
// Page Tables 0x3E0000 - 0x3FBFFF ( 112 KiB)
|
||||
// Stacks 0x3FC000 - 0x3FFFFF ( 16 KiB)
|
||||
|
||||
#define HEAP_BASE (SRAM_BASE + VROM_RSVD)
|
||||
#if !SUPPORT_FPGA
|
||||
#define HEAP_SIZE (0x00100000ULL - PAGE_SIZE)
|
||||
#else
|
||||
#define HEAP_SIZE (0x00080000ULL - PAGE_SIZE)
|
||||
#endif
|
||||
#define HEAP_END (HEAP_BASE + HEAP_SIZE)
|
||||
#define HEAP_GUARD (HEAP_END)
|
||||
|
||||
#define PAGE_TABLES_BASE (TEXT_BASE + TEXT_FOOTPRINT)
|
||||
#define PAGE_TABLES_SIZE (STACKS_BASE - PAGE_TABLES_BASE)
|
||||
#define STACKS_BASE (SRAM_BASE + SRAM_LEN - STACKS_SIZE)
|
||||
#define STACKS_SIZE (EXCEPTION_STACK_SIZE + BOOTSTRAP_STACK_SIZE + INTERRUPT_STACK_SIZE)
|
||||
|
||||
#else /* !WITH_DFU_MODE */
|
||||
|
||||
/* iBoot, iBEC */
|
||||
|
||||
// SDRAM memory map will usually look like the following for T7000:
|
||||
//
|
||||
// iBoot Text 0x830000000 - 0x8300FFFFF ( 1 MiB)
|
||||
// Page Tables 0x830100000 - 0x83017AFFF (492 KiB)
|
||||
// Stacks 0x83017B000 - 0x83017EFFF ( 16 KiB)
|
||||
// Boot trampoline 0x83017F000 - 0x83017FFFF ( 4 KiB)
|
||||
// Heap 0x830180000 - (DISPLAY_BASE - 1 page)
|
||||
// Guard (DISPLAY_BASE - 1 page) - DISPLAY_BASE
|
||||
|
||||
// And for T7001:
|
||||
//
|
||||
// iBoot Text 0x870000000 - 0x8700FFFFF ( 1 MiB)
|
||||
// Page Tables 0x870100000 - 0x87017BFFF (492 KiB)
|
||||
// Stacks 0x87017B000 - 0x87017EFFF ( 16 KiB)
|
||||
// Boot trampoline 0x87017F000 - 0x83017FFFF ( 4 KiB)
|
||||
// Heap 0x870180000 - (DISPLAY_BASE - 1 page)
|
||||
// Guard (DISPLAY_BASE - 1 page) - DISPLAY_BASE
|
||||
|
||||
/* reserved area for iBoot */
|
||||
#define IBOOT_BASE (TEXT_BASE)
|
||||
#define IBOOT_SIZE (HEAP_END - IBOOT_BASE)
|
||||
|
||||
#define PAGE_TABLES_BASE (IBOOT_BASE + TEXT_FOOTPRINT)
|
||||
#define PAGE_TABLES_SIZE (0x0007B000ULL)
|
||||
#define STACKS_BASE (PAGE_TABLES_BASE + PAGE_TABLES_SIZE)
|
||||
#define STACKS_SIZE (EXCEPTION_STACK_SIZE + BOOTSTRAP_STACK_SIZE + INTERRUPT_STACK_SIZE)
|
||||
#define BOOT_TRAMPOLINE_BASE (STACKS_BASE + STACKS_SIZE)
|
||||
#define BOOT_TRAMPOLINE_SIZE (PAGE_SIZE)
|
||||
|
||||
#define HEAP_BASE (BOOT_TRAMPOLINE_BASE + BOOT_TRAMPOLINE_SIZE)
|
||||
#define HEAP_SIZE (DISPLAY_BASE - HEAP_BASE - PAGE_SIZE)
|
||||
#define HEAP_END (HEAP_BASE + HEAP_SIZE)
|
||||
#define HEAP_GUARD (HEAP_END)
|
||||
#if (HEAP_GUARD != (DISPLAY_BASE - PAGE_SIZE))
|
||||
#error "Memory map configuration error"
|
||||
#endif
|
||||
|
||||
#define INSECURE_MEMORY_BASE (SDRAM_BASE)
|
||||
#define INSECURE_MEMORY_SIZE (DEFAULT_LOAD_SIZE)
|
||||
|
||||
#define SECURE_MEMORY_BASE (INSECURE_MEMORY_BASE + INSECURE_MEMORY_SIZE)
|
||||
#define SECURE_MEMORY_SIZE (DEFAULT_FREE_ADDRESS - SECURE_MEMORY_BASE)
|
||||
|
||||
/* unused area */
|
||||
#define UNUSED_MEMORY_BASE (SECURE_MEMORY_BASE + SECURE_MEMORY_SIZE)
|
||||
#define UNUSED_MEMORY_SIZE (IBOOT_BASE - UNUSED_MEMORY_BASE)
|
||||
|
||||
#endif /* !WITH_DFU_MODE */
|
||||
|
||||
#endif /* APPLICATION_IBOOT */
|
||||
|
||||
#endif /* ! __PLATFORM_MEMMAP_H */
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_PCIMAP_H
|
||||
#define __PLATFORM_PCIMAP_H
|
||||
|
||||
/* S5L8970X specific bus/device/function and PCI base address map */
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define PCIE_PORT0_MEMORY_BASE (PCIE_MEMORY_BASE)
|
||||
#define PCIE_PORT0_MEMORY_LEN (0x100000ULL)
|
||||
|
||||
#define NVME0_PCI_BDF (PCI_BDF(1, 0, 0))
|
||||
#define NVME0_BASE_ADDR (PCIE_PORT0_MEMORY_BASE)
|
||||
#define NVME0_SIZE (0x2000)
|
||||
#define NVME0_DART_ID (PCIE_PORT0_DART_ID)
|
||||
|
||||
|
||||
#endif /* ! __PLATFORM_PCIMAP_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#include SUB_PLATFORM_HEADER(pinconfig)
|
||||
@@ -0,0 +1,279 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_PINCONFIG_H
|
||||
#define __PLATFORM_PINCONFIG_H
|
||||
|
||||
/* Default T7000 SoC Pin Configuration - Fiji I/O Spreadsheet v9.3 */
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_DISABLED, // ULPI_DIR ->
|
||||
CFG_DISABLED, // ULPI_STP ->
|
||||
CFG_DISABLED, // ULPI_NXT ->
|
||||
CFG_DISABLED, // ULPI_DATA7 ->
|
||||
CFG_DISABLED, // ULPI_DATA6 ->
|
||||
CFG_DISABLED, // ULPI_DATA5 ->
|
||||
CFG_DISABLED, // ULPI_DATA4 ->
|
||||
CFG_DISABLED, // ULPI_CLK ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // ULPI_DATA3 ->
|
||||
CFG_DISABLED, // ULPI_DATA2 ->
|
||||
CFG_DISABLED, // ULPI_DATA1 ->
|
||||
CFG_DISABLED, // ULPI_DATA0 ->
|
||||
CFG_DISABLED, // SPI1_SCLK ->
|
||||
CFG_DISABLED, // SPI1_MOSI ->
|
||||
CFG_DISABLED, // SPI1_MISO ->
|
||||
CFG_DISABLED, // SPI1_SSIN ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_IN, // GPIO11 -> REQUEST_DFU2 (formerly known as MENU_KEY)
|
||||
CFG_IN, // GPIO12 -> REQUEST_DFU1 (formerly known as HOLD_KEY)
|
||||
CFG_DISABLED, // I2S3_MCK ->
|
||||
CFG_DISABLED, // I2S3_LRCK ->
|
||||
CFG_DISABLED, // I2S3_BCLK ->
|
||||
CFG_DISABLED, // I2S3_DOUT ->
|
||||
CFG_DISABLED, // I2S3_DIN ->
|
||||
CFG_DISABLED, // CLK32K_OUT ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // PCIE_CLKREQ0_N ->
|
||||
CFG_DISABLED, // PCIE_CLKREQ1_N ->
|
||||
CFG_DISABLED, // NAND_SYS_CLK ->
|
||||
CFG_DISABLED, // GPIO0 ->
|
||||
CFG_DISABLED, // GPIO1 ->
|
||||
CFG_DISABLED, // GPIO2 ->
|
||||
CFG_DISABLED, // GPIO3 ->
|
||||
CFG_DISABLED, // GPIO4 ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED, // GPIO5 ->
|
||||
CFG_DISABLED, // GPIO6 ->
|
||||
CFG_DISABLED, // GPIO7 ->
|
||||
CFG_DISABLED, // GPIO14 ->
|
||||
CFG_DISABLED, // GPIO16 -> BOARD_ID[3]
|
||||
CFG_DISABLED, // GPIO17 ->
|
||||
CFG_DISABLED, // GPIO18 -> BOOT_CONFIG[0]
|
||||
CFG_DISABLED, // GPIO20 ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_DISABLED, // GPIO21 ->
|
||||
CFG_DISABLED, // UART5_RTXD ->
|
||||
CFG_DISABLED, // UART8_TXD ->
|
||||
CFG_DISABLED, // UART8_RXD ->
|
||||
CFG_DISABLED, // SPI0_SCLK -> SPI0_SCLK/BOARD_ID[0]
|
||||
CFG_DISABLED, // SPI0_MOSI -> SPI0_MOSI/BOARD_ID[1]
|
||||
CFG_DISABLED, // SPI0_MISO -> SPI0_MISO/BOARD_ID[2]
|
||||
CFG_DISABLED, // SPI0_SSIN ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // I2C2_SDA ->
|
||||
CFG_DISABLED, // I2C2_SCL ->
|
||||
CFG_DISABLED, // GPIO22 ->
|
||||
CFG_DISABLED, // GPIO23 ->
|
||||
CFG_DISABLED, // GPIO25 -> BOOT_CONFIG[1]
|
||||
CFG_DISABLED, // GPIO28 -> BOOT_CONFIG[2]
|
||||
CFG_DISABLED, // GPIO29 -> BOARD_ID[4]
|
||||
CFG_DISABLED, // GPIO34 ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // GPIO35 ->
|
||||
CFG_DISABLED, // GPIO36 ->
|
||||
CFG_DISABLED, // GPIO37 ->
|
||||
CFG_DISABLED, // GPIO39 ->
|
||||
CFG_DISABLED, // GPIO42 ->
|
||||
CFG_DISABLED, // GPIO43 ->
|
||||
CFG_DISABLED, // DISP_VSYNC ->
|
||||
CFG_DISABLED, // UART0_TXD ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // UART0_RXD ->
|
||||
CFG_DISABLED, // TMR32_PWM0 ->
|
||||
CFG_DISABLED, // TMR32_PWM1 ->
|
||||
CFG_DISABLED, // TMR32_PWM2 ->
|
||||
CFG_DISABLED, // UART6_TXD ->
|
||||
CFG_DISABLED, // UART6_RXD ->
|
||||
CFG_DISABLED, // I2C3_SDA ->
|
||||
CFG_DISABLED, // I2C3_SCL ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // I2C0_SDA ->
|
||||
CFG_DISABLED, // I2C0_SCL ->
|
||||
CFG_DISABLED, // GPIO38 ->
|
||||
CFG_DISABLED, // UART2_TXD ->
|
||||
CFG_DISABLED, // UART2_RXD ->
|
||||
CFG_DISABLED, // UART2_RTSN ->
|
||||
CFG_DISABLED, // UART2_CTSN ->
|
||||
CFG_DISABLED, // DWI_DO ->
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // DWI_CLK ->
|
||||
CFG_FUNC0, // WDOG ->
|
||||
CFG_DISABLED, // GPIO13 ->
|
||||
CFG_DISABLED, // GPIO19 ->
|
||||
CFG_IN | PULL_DOWN, // GPIO26 -> FORCE_DFU
|
||||
CFG_DISABLED | PULL_DOWN, // GPIO27 -> DFU_STATUS
|
||||
CFG_DISABLED, // SOCHOT0 ->
|
||||
CFG_DISABLED, // SOCHOT1 ->
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // CPU_SLEEP_STATUS ->
|
||||
CFG_DISABLED, // TST_CLKOUT ->
|
||||
CFG_DISABLED, // GPIO8 ->
|
||||
CFG_DISABLED, // GPIO9 ->
|
||||
CFG_DISABLED, // GPIO10 ->
|
||||
CFG_DISABLED, // GPIO15 ->
|
||||
CFG_DISABLED, // UART4_TXD ->
|
||||
CFG_DISABLED, // UART4_RXD ->
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // UART4_RTSN ->
|
||||
CFG_DISABLED, // UART4_CTSN ->
|
||||
CFG_DISABLED, // SPI3_MOSI ->
|
||||
CFG_DISABLED, // SPI3_MISO ->
|
||||
CFG_DISABLED, // SPI3_SCLK ->
|
||||
CFG_DISABLED, // SPI3_SSIN ->
|
||||
CFG_DISABLED, // GPIO24 ->
|
||||
CFG_DISABLED, // GPIO30 ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED, // GPIO31 ->
|
||||
CFG_DISABLED, // GPIO32 ->
|
||||
CFG_DISABLED, // GPIO33 ->
|
||||
CFG_DISABLED, // GPIO40 ->
|
||||
CFG_DISABLED, // GPIO41 ->
|
||||
CFG_DISABLED, // I2S4_MCK ->
|
||||
CFG_DISABLED, // I2S4_LRCK ->
|
||||
CFG_DISABLED, // I2S4_BCLK ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // I2S4_DOUT ->
|
||||
CFG_DISABLED, // I2S4_DIN ->
|
||||
CFG_DISABLED, // I2C1_SDA ->
|
||||
CFG_DISABLED, // I2C1_SCL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // I2S0_LRCK ->
|
||||
CFG_DISABLED, // I2S0_BCLK ->
|
||||
CFG_DISABLED, // I2S0_DOUT ->
|
||||
CFG_DISABLED, // I2S0_DIN ->
|
||||
CFG_DISABLED, // I2S1_MCK ->
|
||||
CFG_DISABLED, // I2S1_LRCK ->
|
||||
CFG_DISABLED, // I2S1_BCLK ->
|
||||
CFG_DISABLED, // I2S1_DOUT ->
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // I2S1_DIN ->
|
||||
CFG_DISABLED, // I2S2_LRCK ->
|
||||
CFG_DISABLED, // I2S2_BCLK ->
|
||||
CFG_DISABLED, // I2S2_DOUT ->
|
||||
CFG_DISABLED, // I2S2_DIN ->
|
||||
CFG_DISABLED, // UART1_TXD ->
|
||||
CFG_DISABLED, // UART1_RXD ->
|
||||
CFG_DISABLED, // UART1_RTSN ->
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // UART1_CTSN ->
|
||||
CFG_DISABLED, // EDP_HPD ->
|
||||
CFG_DISABLED, // UART3_TXD ->
|
||||
CFG_DISABLED, // UART3_RXD ->
|
||||
CFG_DISABLED, // UART3_RTSN ->
|
||||
CFG_DISABLED, // UART3_CTSN ->
|
||||
CFG_DISABLED, // SPI2_SCLK ->
|
||||
CFG_DISABLED, // SPI2_MOSI ->
|
||||
|
||||
/* Port 23 */
|
||||
CFG_DISABLED, // SPI2_MISO ->
|
||||
CFG_DISABLED, // SPI2_SSIN ->
|
||||
CFG_DISABLED, // ISP0_SDA ->
|
||||
CFG_DISABLED, // ISP0_SCL ->
|
||||
CFG_DISABLED, // ISP1_SDA ->
|
||||
CFG_DISABLED, // ISP1_SCL ->
|
||||
CFG_DISABLED, // SENSOR0_RST ->
|
||||
CFG_DISABLED, // SENSOR0_CLK ->
|
||||
|
||||
/* Port 24 */
|
||||
CFG_DISABLED, // SENSOR0_XSHUTDOWN ->
|
||||
CFG_DISABLED, // SENSOR0_ISTRB ->
|
||||
CFG_DISABLED, // ISP_UART0_TXD ->
|
||||
CFG_DISABLED, // ISP_UART0_RXD ->
|
||||
CFG_DISABLED, // SENSOR1_RST ->
|
||||
CFG_DISABLED, // SENSOR1_CLK ->
|
||||
CFG_DISABLED, // SENSOR1_XSHUTDOWN ->
|
||||
CFG_DISABLED, // SENSOR1_ISTRB ->
|
||||
|
||||
/* Port 25 */
|
||||
CFG_DISABLED, // UART7_TXD ->
|
||||
CFG_DISABLED, // UART7_RXD ->
|
||||
CFG_DISABLED, // I2S0_MCK ->
|
||||
CFG_DISABLED, // I2S2_MCK ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
};
|
||||
|
||||
#endif /* ! __PLATFORM_PINCONFIG_H */
|
||||
@@ -0,0 +1,249 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_PINCONFIG_H
|
||||
#define __PLATFORM_PINCONFIG_H
|
||||
|
||||
/* Default T7001 SoC Pin Configuration - Capri I/O Spreadsheet v10.29 */
|
||||
|
||||
static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
|
||||
|
||||
/* Port 0 */
|
||||
CFG_IN, // MENU_KEY_L -> REQUEST_DFU2
|
||||
CFG_IN, // HOLD_KEY_L -> REQUEST_DFU1
|
||||
CFG_DISABLED, // ISP0_SDA ->
|
||||
CFG_DISABLED, // ISP0_SCL ->
|
||||
CFG_DISABLED, // ISP1_SDA ->
|
||||
CFG_DISABLED, // ISP1_SCL ->
|
||||
CFG_DISABLED, // SENSOR0_RST ->
|
||||
CFG_DISABLED, // SENSOR0_CLK ->
|
||||
|
||||
/* Port 1 */
|
||||
CFG_DISABLED, // SENSOR0_XSHUTDOWN ->
|
||||
CFG_DISABLED, // SENSOR0_ISTRB ->
|
||||
CFG_DISABLED, // SENSOR1_RST ->
|
||||
CFG_DISABLED, // SENSOR1_CLK ->
|
||||
CFG_DISABLED, // SENSOR1_XSHUTDOWN ->
|
||||
CFG_DISABLED, // SENSOR1_ISTRB ->
|
||||
CFG_DISABLED, // UART3_TXD ->
|
||||
CFG_DISABLED, // UART3_RXD ->
|
||||
|
||||
/* Port 2 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 3 */
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 4 */
|
||||
CFG_DISABLED, // UART3_RTSN ->
|
||||
CFG_DISABLED, // UART3_CTSN ->
|
||||
CFG_DISABLED, // UART5_RTXD ->
|
||||
CFG_DISABLED, // DWI0_DO ->
|
||||
CFG_DISABLED, // DWI0_CLK ->
|
||||
CFG_DISABLED, // I2C0_SDA ->
|
||||
CFG_DISABLED, // I2C0_SCL ->
|
||||
CFG_DISABLED, // I2S0_LRCK ->
|
||||
|
||||
/* Port 5 */
|
||||
CFG_DISABLED, // I2S0_BCLK ->
|
||||
CFG_DISABLED, // I2S0_DOUT ->
|
||||
CFG_DISABLED, // I2S0_DIN ->
|
||||
CFG_DISABLED, // I2S1_MCK ->
|
||||
CFG_DISABLED, // I2S1_LRCK ->
|
||||
CFG_DISABLED, // I2S1_BCLK ->
|
||||
CFG_DISABLED, // I2S1_DOUT ->
|
||||
CFG_DISABLED, // I2S1_DIN ->
|
||||
|
||||
/* Port 6 */
|
||||
CFG_DISABLED, // SPI3_MOSI ->
|
||||
CFG_DISABLED, // SPI3_MISO ->
|
||||
CFG_DISABLED, // SPI3_SCLK ->
|
||||
CFG_DISABLED, // SPI3_SSIN ->
|
||||
CFG_DISABLED, // TMR32_PWM0 ->
|
||||
CFG_DISABLED, // TMR32_PWM1 ->
|
||||
CFG_DISABLED, // TMR32_PWM2 ->
|
||||
CFG_DISABLED, // DISP_VSYNC ->
|
||||
|
||||
/* Port 7 */
|
||||
CFG_FUNC0, // WDOG ->
|
||||
CFG_DISABLED, // SOCHOT0 ->
|
||||
CFG_DISABLED, // SOCHOT1 ->
|
||||
CFG_DISABLED, // CPU_SLEEP_STATUS ->
|
||||
CFG_DISABLED, // TST_CLKOUT ->
|
||||
CFG_DISABLED, // ISP_UART0_TXD ->
|
||||
CFG_DISABLED, // ISP_UART0_RXD ->
|
||||
CFG_DISABLED, // UART7_TXD ->
|
||||
|
||||
/* Port 8 */
|
||||
CFG_DISABLED, // UART7_RXD ->
|
||||
CFG_DISABLED, // I2C1_SDA ->
|
||||
CFG_DISABLED, // I2C1_SCL ->
|
||||
CFG_DISABLED, // SPI0_SCLK -> BOARD_ID0
|
||||
CFG_DISABLED, // SPI0_MOSI -> BOARD_ID1
|
||||
CFG_DISABLED, // SPI0_MISO -> BOARD_ID2
|
||||
CFG_DISABLED, // SPI0_SSIN ->
|
||||
CFG_DISABLED, // I2S3_MCK ->
|
||||
|
||||
/* Port 9 */
|
||||
CFG_DISABLED, // I2S3_LRCK ->
|
||||
CFG_DISABLED, // I2S3_BCLK ->
|
||||
CFG_DISABLED, // I2S3_DOUT ->
|
||||
CFG_DISABLED, // I2S3_DIN ->
|
||||
CFG_DISABLED, // UART4_TXD ->
|
||||
CFG_DISABLED, // UART4_RXD ->
|
||||
CFG_DISABLED, // UART4_RTSN ->
|
||||
CFG_DISABLED, // UART4_CTSN ->
|
||||
|
||||
/* Port 10 */
|
||||
CFG_DISABLED, // GPIO0 ->
|
||||
CFG_DISABLED, // GPIO1 ->
|
||||
CFG_DISABLED, // GPIO2 ->
|
||||
CFG_DISABLED, // GPIO3 ->
|
||||
CFG_DISABLED, // GPIO4 ->
|
||||
CFG_DISABLED, // GPIO5 ->
|
||||
CFG_DISABLED, // GPIO6 ->
|
||||
CFG_DISABLED, // GPIO7 ->
|
||||
|
||||
/* Port 11 */
|
||||
CFG_DISABLED, // GPIO8 ->
|
||||
CFG_DISABLED, // GPIO9 ->
|
||||
CFG_DISABLED, // GPIO10 ->
|
||||
CFG_DISABLED, // GPIO11 ->
|
||||
CFG_DISABLED, // GPIO12 ->
|
||||
CFG_DISABLED, // GPIO13 ->
|
||||
CFG_DISABLED, // GPIO14 ->
|
||||
CFG_DISABLED, // GPIO15 ->
|
||||
|
||||
/* Port 12 */
|
||||
CFG_DISABLED, // GPIO16 -> BOARD_ID3
|
||||
CFG_DISABLED, // GPIO17 ->
|
||||
CFG_DISABLED, // GPIO18 -> BOOT_CONFIG0
|
||||
CFG_DISABLED, // GPIO19 ->
|
||||
CFG_DISABLED, // GPIO20 ->
|
||||
CFG_DISABLED, // GPIO21 ->
|
||||
CFG_DISABLED, // GPIO22 ->
|
||||
CFG_DISABLED, // GPIO23 ->
|
||||
|
||||
/* Port 13 */
|
||||
CFG_DISABLED, // GPIO24 ->
|
||||
CFG_DISABLED, // GPIO25 -> BOOT_CONFIG1
|
||||
CFG_IN | PULL_DOWN, // GPIO26 -> FORCE_DFU
|
||||
CFG_DISABLED | PULL_DOWN, // GPIO27 -> DFU_STATUS
|
||||
CFG_DISABLED, // GPIO28 -> BOOT_CONFIG2
|
||||
CFG_DISABLED, // GPIO29 -> BOARD_ID4
|
||||
CFG_DISABLED, // GPIO30 ->
|
||||
CFG_DISABLED, // GPIO31 -> BOOT_CONFIG3
|
||||
|
||||
/* Port 14 */
|
||||
CFG_DISABLED, // GPIO32 ->
|
||||
CFG_DISABLED, // GPIO33 ->
|
||||
CFG_DISABLED, // GPIO34 ->
|
||||
CFG_DISABLED, // GPIO35 ->
|
||||
CFG_DISABLED, // GPIO36 ->
|
||||
CFG_DISABLED, // GPIO37 ->
|
||||
CFG_DISABLED, // SPI2_SCLK ->
|
||||
CFG_DISABLED, // SPI2_MOSI ->
|
||||
|
||||
/* Port 15 */
|
||||
CFG_DISABLED, // SPI2_MISO ->
|
||||
CFG_DISABLED, // SPI2_SSIN ->
|
||||
CFG_DISABLED, // UART8_TXD ->
|
||||
CFG_DISABLED, // UART8_RXD ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
CFG_DISABLED, // NULL ->
|
||||
|
||||
/* Port 16 */
|
||||
CFG_DISABLED, // UART0_TXD ->
|
||||
CFG_DISABLED, // UART0_RXD ->
|
||||
CFG_DISABLED, // UART6_TXD ->
|
||||
CFG_DISABLED, // UART6_RXD ->
|
||||
CFG_DISABLED, // I2C2_SDA ->
|
||||
CFG_DISABLED, // I2C2_SCL ->
|
||||
CFG_DISABLED, // I2C3_SDA ->
|
||||
CFG_DISABLED, // I2C3_SCL ->
|
||||
|
||||
/* Port 17 */
|
||||
CFG_DISABLED, // UART2_TXD ->
|
||||
CFG_DISABLED, // UART2_RXD ->
|
||||
CFG_DISABLED, // UART2_RTSN ->
|
||||
CFG_DISABLED, // UART2_CTSN ->
|
||||
CFG_DISABLED, // UART1_TXD ->
|
||||
CFG_DISABLED, // UART1_RXD ->
|
||||
CFG_DISABLED, // UART1_RTSN ->
|
||||
CFG_DISABLED, // UART1_CTSN ->
|
||||
|
||||
/* Port 18 */
|
||||
CFG_DISABLED, // EDP_HPD ->
|
||||
CFG_DISABLED, // I2S4_MCK ->
|
||||
CFG_DISABLED, // I2S4_LRCK ->
|
||||
CFG_DISABLED, // I2S4_BCLK ->
|
||||
CFG_DISABLED, // I2S4_DOUT ->
|
||||
CFG_DISABLED, // I2S4_DIN ->
|
||||
CFG_DISABLED, // I2S2_LRCK ->
|
||||
CFG_DISABLED, // I2S2_BCLK ->
|
||||
|
||||
/* Port 19 */
|
||||
CFG_DISABLED, // I2S2_DOUT ->
|
||||
CFG_DISABLED, // I2S2_DIN ->
|
||||
CFG_DISABLED, // SPI1_SCLK ->
|
||||
CFG_DISABLED, // SPI1_MOSI ->
|
||||
CFG_DISABLED, // SPI1_MISO ->
|
||||
CFG_DISABLED, // SPI1_SSIN ->
|
||||
CFG_DISABLED, // CLK32K_OUT ->
|
||||
CFG_DISABLED, // ULPI_DIR ->
|
||||
|
||||
/* Port 20 */
|
||||
CFG_DISABLED, // ULPI_STP ->
|
||||
CFG_DISABLED, // ULPI_NXT ->
|
||||
CFG_DISABLED, // ULPI_DATA7 ->
|
||||
CFG_DISABLED, // ULPI_DATA6 ->
|
||||
CFG_DISABLED, // ULPI_DATA5 ->
|
||||
CFG_DISABLED, // ULPI_DATA4 ->
|
||||
CFG_DISABLED, // ULPI_CLK ->
|
||||
CFG_DISABLED, // ULPI_DATA3 ->
|
||||
|
||||
/* Port 21 */
|
||||
CFG_DISABLED, // ULPI_DATA2 ->
|
||||
CFG_DISABLED, // ULPI_DATA1 ->
|
||||
CFG_DISABLED, // ULPI_DATA0 ->
|
||||
CFG_DISABLED, // DWI1_DO ->
|
||||
CFG_DISABLED, // DWI1_CLK ->
|
||||
CFG_DISABLED, // PCIE_CLKREQ0_N ->
|
||||
CFG_DISABLED, // PCIE_CLKREQ1_N ->
|
||||
CFG_DISABLED, // PCIE_CLKREQ2_N ->
|
||||
|
||||
/* Port 22 */
|
||||
CFG_DISABLED, // PCIE_CLKREQ3_N ->
|
||||
CFG_DISABLED, // NAND_SYS_CLK ->
|
||||
CFG_DISABLED, // PCIE_PERST0_N ->
|
||||
CFG_DISABLED, // PCIE_PERST1_N ->
|
||||
CFG_DISABLED, // PCIE_PERST2_N ->
|
||||
CFG_DISABLED, // PCIE_PERST3_N ->
|
||||
CFG_DISABLED, // I2S0_MCK ->
|
||||
CFG_DISABLED, // I2S2_MCK ->
|
||||
};
|
||||
|
||||
#endif /* ! __PLATFORM_PINCONFIG_H */
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_SOC_CCC_H
|
||||
#define __PLATFORM_SOC_CCC_H
|
||||
|
||||
#define rCCC_CPU0_IMPL_IORVBAR (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + 0x000))
|
||||
#define rCCC_CPU0_IMPL_CPU_IOACC_CTL_EL3 (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + 0x008))
|
||||
#define rCCC_CPU0_IMPL_FED_ERR_STS (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + 0x010))
|
||||
#define rCCC_CPU0_IMPL_LSU_ERR_STS (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + 0x018))
|
||||
#define rCCC_CPU0_IMPL_MMU_ERR_STS (*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + 0x020))
|
||||
|
||||
#define CCC0_IMPL_BASE_ADDR (CCC0_SYS_BASE_ADDR + 0x40000)
|
||||
#define rCCC_CCC_IMPL_CPM_IOACC_CTL_EL3 (*(volatile u_int64_t *)(CCC0_IMPL_BASE_ADDR + 0x000))
|
||||
#define rCCC_CCC_IMPL_L2C_ERR_STS (*(volatile u_int64_t *)(CCC0_IMPL_BASE_ADDR + 0x008))
|
||||
#define rCCC_CCC_IMPL_L2C_ERR_ADR (*(volatile u_int64_t *)(CCC0_IMPL_BASE_ADDR + 0x010))
|
||||
#define rCCC_CCC_IMPL_L2C_ERR_INF (*(volatile u_int64_t *)(CCC0_IMPL_BASE_ADDR + 0x018))
|
||||
|
||||
#define rCCC_CPU1_IMPL_IORVBAR (*(volatile u_int64_t *)(CCC_CPU1_SYS_BASE_ADDR + 0x000))
|
||||
#define rCCC_CPU2_IMPL_IORVBAR (*(volatile u_int64_t *)(CCC_CPU2_SYS_BASE_ADDR + 0x000))
|
||||
|
||||
#endif /* __PLATFORM_SOC_CCC_H */
|
||||
@@ -0,0 +1,179 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_CHIPID_H
|
||||
#define __PLATFORM_SOC_CHIPID_H
|
||||
|
||||
#include <platform/chipid.h>
|
||||
#include <platform/soc/pmgr.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rCFG_FUSE0 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x00))
|
||||
#define rCFG_FUSE1 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x04))
|
||||
#define rCFG_FUSE2 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x08))
|
||||
#define rCFG_FUSE3 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x0C))
|
||||
#define rCFG_FUSE4 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x10))
|
||||
#define rCFG_FUSE5 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x14))
|
||||
#define rCFG_FUSE6 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x18))
|
||||
#define rCFG_FUSE7 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x1C))
|
||||
#define rCFG_FUSE8 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x20))
|
||||
#define rCFG_FUSE9 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x24))
|
||||
#define rCFG_FUSE15 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x3C))
|
||||
|
||||
#if SUB_PLATFORM_T7001
|
||||
#define CFG_FUSE8_PCIE_REF_PLL_VREG_ADJ_SHIFT (24)
|
||||
#define CFG_FUSE8_PCIE_REF_PLL_VREG_ADJ_MASK (0x7)
|
||||
#endif
|
||||
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define MINIMUM_FUSE_REVISION 0x9
|
||||
#elif SUB_PLATFORM_T7001
|
||||
// Fuse Rev 0x2 means Capri A1 or later.
|
||||
// So all binning are against Capri A1 in "Capri Test Plan Version 1.1"
|
||||
#define MINIMUM_FUSE_REVISION 0x2
|
||||
// Fuse Rev 0x41 means Capri with updated binning for J99 P5 and P6.
|
||||
#define MINIMUM_BINNED_GPU_P6_REVISION 0x41
|
||||
#define P6_VOL_OFFSET_FROM_P4_BINNING 143
|
||||
#endif
|
||||
|
||||
#define CFG_FUSE9_PLL_VCO_RCTRL_SEL (0x8) // VCO_RCTRL_OW value is valid if set
|
||||
#define CFG_FUSE9_PLL_VCO_RCTRL_OW_MASK (0x7) // PLL analog override value if valid
|
||||
|
||||
#define CFG_FUSE9_PLL_0_SHIFT (0)
|
||||
#define CFG_FUSE9_PLL_1_SHIFT (4)
|
||||
#define CFG_FUSE9_PLL_2_SHIFT (8)
|
||||
#define CFG_FUSE9_PLL_3_SHIFT (12)
|
||||
#define CFG_FUSE9_PLL_4_SHIFT (16)
|
||||
#define CFG_FUSE9_PLL_5_SHIFT (20)
|
||||
#define CFG_FUSE9_PLL_CPU_SHIFT (24)
|
||||
#define CFG_FUSE9_PLL_LPDP_SHIFT (28)
|
||||
|
||||
#define CFG_FUSE2_THERMAL_SEN_MASK (0x1f)
|
||||
#define CFG_FUSE2_THERMAL_SEN_SHIFT(_idx) (5 * (_idx))
|
||||
#define CFG_FUSE2_THERMAL_SEN(_idx) ((rCFG_FUSE2 >> CFG_FUSE2_THERMAL_SEN_SHIFT(_idx)) & CFG_FUSE2_THERMAL_SEN_MASK)
|
||||
|
||||
#define rECIDLO (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x80))
|
||||
#define rECIDHI (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x84))
|
||||
|
||||
#define rSEP_SECURITY (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x104))
|
||||
|
||||
#define rCFG_FUSE0_RAW (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x200))
|
||||
|
||||
#define CHIPID_SOC_VOLTAGE_BYPASS (0)
|
||||
#define CHIPID_SOC_VOLTAGE_SECUREROM (1)
|
||||
#define CHIPID_SOC_VOLTAGE_IBOOT_MEM_LOW_PERF (2)
|
||||
#define CHIPID_SOC_VOLTAGE_VMIN (3)
|
||||
#define CHIPID_SOC_VOLTAGE_VNOM (4)
|
||||
|
||||
uint32_t chipid_get_soc_voltage(uint32_t index);
|
||||
|
||||
|
||||
/* Wahtever is the platform CHIPID_GPU_VOLTAGE_V0_DIDT index
|
||||
* will always follows immediatly the last CHIPID_GPU_VOLTAGE_V[0-9]
|
||||
* So, CHIPID_GPU_VOLTAGE_V0_DIDT will also be the number of regular voltages,
|
||||
* i.e. all voltages excepts DIDT ones.*/
|
||||
#if SUB_TARGET_N56 || SUB_TARGET_J42 || SUB_TARGET_J42D
|
||||
#define CHIPID_GPU_VOLTAGE_OFF (0)
|
||||
#define CHIPID_GPU_VOLTAGE_V0 (1)
|
||||
#define CHIPID_GPU_VOLTAGE_V1 (2)
|
||||
#define CHIPID_GPU_VOLTAGE_V2 (3)
|
||||
#define CHIPID_GPU_VOLTAGE_V3 (4)
|
||||
#define CHIPID_GPU_VOLTAGE_V0_DIDT (5)
|
||||
#define CHIPID_GPU_VOLTAGE_V1_DIDT (6)
|
||||
#define CHIPID_GPU_VOLTAGE_V2_DIDT (7)
|
||||
#define CHIPID_GPU_VOLTAGE_V3_DIDT (8)
|
||||
#elif SUB_PLATFORM_T7001 || SUB_TARGET_J96 || SUB_TARGET_J97
|
||||
#define CHIPID_GPU_VOLTAGE_OFF (0)
|
||||
#define CHIPID_GPU_VOLTAGE_V0 (1)
|
||||
#define CHIPID_GPU_VOLTAGE_V1 (2)
|
||||
#define CHIPID_GPU_VOLTAGE_V2 (3)
|
||||
#define CHIPID_GPU_VOLTAGE_V3 (4)
|
||||
#define CHIPID_GPU_VOLTAGE_V4 (5)
|
||||
#define CHIPID_GPU_VOLTAGE_V5 (6)
|
||||
#define CHIPID_GPU_VOLTAGE_V0_DIDT (7)
|
||||
#define CHIPID_GPU_VOLTAGE_V1_DIDT (8)
|
||||
#define CHIPID_GPU_VOLTAGE_V2_DIDT (9)
|
||||
#define CHIPID_GPU_VOLTAGE_V3_DIDT (10)
|
||||
#define CHIPID_GPU_VOLTAGE_V4_DIDT (11)
|
||||
#define CHIPID_GPU_VOLTAGE_V5_DIDT (12)
|
||||
#define CHIPID_GPU_VOLTAGE_V_UVD CHIPID_GPU_VOLTAGE_V5
|
||||
#else
|
||||
#define CHIPID_GPU_VOLTAGE_OFF (0)
|
||||
#define CHIPID_GPU_VOLTAGE_V0 (1)
|
||||
#define CHIPID_GPU_VOLTAGE_V1 (2)
|
||||
#define CHIPID_GPU_VOLTAGE_V2 (3)
|
||||
#define CHIPID_GPU_VOLTAGE_V0_DIDT (4)
|
||||
#define CHIPID_GPU_VOLTAGE_V1_DIDT (5)
|
||||
#define CHIPID_GPU_VOLTAGE_V2_DIDT (6)
|
||||
#endif
|
||||
|
||||
uint32_t chipid_get_gpu_voltage(uint32_t index);
|
||||
|
||||
#define CHIPID_CPU_VOLTAGE_BYPASS (0)
|
||||
#define CHIPID_CPU_VOLTAGE_SECUREROM (1)
|
||||
#define CHIPID_CPU_VOLTAGE_V0 (2)
|
||||
#define CHIPID_CPU_VOLTAGE_V1 (3)
|
||||
#define CHIPID_CPU_VOLTAGE_V2 (4)
|
||||
#define CHIPID_CPU_VOLTAGE_V3 (5)
|
||||
#define CHIPID_CPU_VOLTAGE_V4 (6)
|
||||
#define CHIPID_CPU_VOLTAGE_V5 (7)
|
||||
// Currently pmgr expect any CHIPID_CPU_VOLTAGE_V* to be
|
||||
// an index in the DVFM table. So, between 0 and 7.
|
||||
// It will no more be the case for 1.6GHz
|
||||
// who would be CHIPID_CPU_VOLTAGE_V6 or CHIPID_CPU_VOLTAGE_V6_UNBINNED.
|
||||
#define CHIPID_CPU_VOLTAGE_V6 (8)
|
||||
#define CHIPID_CPU_VOLTAGE_V6_UNBINNED (9)
|
||||
|
||||
|
||||
uint32_t chipid_get_cpu_voltage(uint32_t index);
|
||||
|
||||
uint32_t chipid_get_ram_voltage(uint32_t index);
|
||||
|
||||
uint32_t chipid_get_gpu_ram_voltage(uint32_t index);
|
||||
|
||||
int32_t chipid_get_cpu_temp_offset(uint32_t cpu_number);
|
||||
|
||||
uint32_t chipid_get_soc_temp_sensor_trim(uint32_t sensor_index);
|
||||
|
||||
uint32_t chipid_get_fuse_revision(void);
|
||||
|
||||
uint32_t chipid_get_total_rails_leakage(void);
|
||||
|
||||
enum chipid_vol_adj_type {
|
||||
CHIPID_VOL_ADJ_CPU,
|
||||
CHIPID_VOL_ADJ_SOC,
|
||||
};
|
||||
|
||||
struct chipid_vol_adj {
|
||||
uint32_t region_uV[4];
|
||||
};
|
||||
void chipid_get_vol_adj(enum chipid_vol_adj_type vol_adj_type, uint32_t index, struct chipid_vol_adj * vol_adj);
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
|
||||
#define FPGA_HAS_ALWAYS (1 << 0)
|
||||
#define FPGA_HAS_VXD (1 << 1)
|
||||
#define FPGA_HAS_AVE (1 << 2)
|
||||
#define FPGA_HAS_ISP (1 << 3)
|
||||
#define FPGA_HAS_DISP0 (1 << 4)
|
||||
#define FPGA_HAS_DISP1 (1 << 5)
|
||||
#define FPGA_HAS_MSR (1 << 6)
|
||||
#define FPGA_HAS_JPEG (1 << 7)
|
||||
#define FPGA_HAS_GFX (1 << 8)
|
||||
#define FPGA_HAS_MEDIA (1 << 9)
|
||||
#define FPGA_HAS_PCIE (1 << 10)
|
||||
|
||||
#define rECID_FUSE7 (*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x9c))
|
||||
|
||||
uint32_t chipid_get_fpga_block_instantiation(void);
|
||||
|
||||
#endif // SUPPORT_FPGA
|
||||
|
||||
#endif /* __PLATFORM_SOC_CHIPID_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include SUB_PLATFORM_HEADER(soc/display)
|
||||
|
||||
@@ -0,0 +1,175 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_H
|
||||
#define __APPLE_DISPLAY_H
|
||||
|
||||
static struct adfe_v2_tuneable adfe_tuneables[] =
|
||||
{
|
||||
#if DISPLAY_IPHONE_TUNABLES
|
||||
#if DISPLAY_D600_TUNABLES
|
||||
{
|
||||
.name = "D600",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x20) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x617),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x7f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x1082) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x61d),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x60d),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x453),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x443),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x4b) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = 0,
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
#endif //DISPLAY_D600_TUNABLES
|
||||
|
||||
|
||||
#if DISPLAY_D500_TUNABLES || DISPLAY_D410_TUNABLES
|
||||
{
|
||||
#if DISPLAY_D500_TUNABLES
|
||||
.name = "D500",
|
||||
#else
|
||||
.name = "D410",
|
||||
#endif
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x20) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x282),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x7f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x17c5) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x280),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x278),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x1c5),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x1bd),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x4b) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = 0,
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
#endif //DISPLAY_D500_TUNABLES || DISPLAY_D410_TUNABLES
|
||||
|
||||
#if DISPLAY_D403_TUNABLES
|
||||
{
|
||||
.name = "D403",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x20) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x1BF),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x7f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x74A) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x1C5),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x1B5),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x144),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x134),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x4b) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = 0,
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
#endif // DISPLAY_D403_TUNABLES
|
||||
|
||||
#if DISPLAY_D500_2LANE_TUNABLES
|
||||
{
|
||||
.name = "D500_2LANE",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x20) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x282),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x7f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x17c5) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x280),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x278),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x1c5),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x1bd),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x4b) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = 0,
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
#endif //DISPLAY_D500_2LANE_TUNABLES
|
||||
#endif //DISPLAY_IPHONE_TUNABLES
|
||||
|
||||
//Tunables for targets using the the timing based on landscape ipads
|
||||
#if DISPLAY_LANDSCAPE_IPAD_TUNABLES || DISPLAY_APPLE_TV_TUNABLES || DISPLAY_FPGA_TUNABLES
|
||||
{
|
||||
.name = "default",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x20) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x547),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x7f8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x159a) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x54d),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x53d),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x3a9),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x399),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x4b) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = 0,
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
|
||||
#if DISPLAY_IPHONE_TUNABLES
|
||||
#error DISPLAY_IPHONE_TUNABLES set for IPAD
|
||||
#endif
|
||||
|
||||
#endif //DISPLAY_LANDSCAPE_IPAD_TUNABLES || DISPLAY_APPLE_TV_TUNABLES || DISPLAY_FPGA_TUNABLES
|
||||
};
|
||||
|
||||
#endif /* ! __APPLE_DISPLAY_H */
|
||||
@@ -0,0 +1,102 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_H
|
||||
#define __APPLE_DISPLAY_H
|
||||
|
||||
static struct adfe_v2_tuneable adfe_tuneables[] =
|
||||
{
|
||||
//Tunables for targets using the the timing based on landscape ipads
|
||||
#if DISPLAY_LANDSCAPE_IPAD_TUNABLES || DISPLAY_APPLE_TV_TUNABLES || DISPLAY_FPGA_TUNABLES
|
||||
#if DISPLAY_X136_TUNABLES
|
||||
{
|
||||
.name = "default",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x20) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x904),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0xff8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x1a24) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x90e),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x8fa),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x63e),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x62a),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x4b) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0x30) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
|
||||
{
|
||||
// XXX - needs updated with correct values!
|
||||
.name = "camelia",
|
||||
.disp_dpcclkcntl = (0),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x800),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0x800),
|
||||
.disp_dpcqoscfg = (0),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0),
|
||||
.disp_dpclinkdown = (0),
|
||||
.disp_dpgpreqaggr = (0),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0x18)),
|
||||
.disp_dpcenab = (0),
|
||||
},
|
||||
#endif
|
||||
|
||||
#if !DISPLAY_X136_TUNABLES
|
||||
{
|
||||
.name = "default",
|
||||
.disp_dpcclkcntl = (ADPCCLKCNTL_FLOOR(0x20) | \
|
||||
ADPCCLKCNTL_PIPE_ENABLE | \
|
||||
ADPCCLKCNTL_LB_ENABLE | \
|
||||
ADPCCLKCNTL_PIO_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_STAT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_EXT_GATE_ENABLE | \
|
||||
ADPCCLKCNTL_DYN_GATE_ENABLE),
|
||||
.disp_dpcclklvl_clock_on_level = ADPCCLKLVL_ONLVL(0x547),
|
||||
.disp_dpcclklvl_clock_off_level = ADPCCLKLVL_OFFLVL(0xff8),
|
||||
.disp_dpcqoscfg = (ADPCQOSCFG_QOS_TIMER(0x15b5) | \
|
||||
ADPCQOSCFG_PIPE_ENABLE | \
|
||||
ADPCQOSCFG_QOS_ENABLE),
|
||||
.disp_dpcqosylvl_yellow_off = ADPCQOSYLVL_YELLOW_OFF(0x545),
|
||||
.disp_dpcqosylvl_yellow_on = ADPCQOSYLVL_YELLOW_ON(0x53d),
|
||||
.disp_dpcqosrlvl_red_off = ADPCQOSRLVL_RED_OFF(0x3a1),
|
||||
.disp_dpcqosrlvl_red_on = ADPCQOSRLVL_RED_ON(0x399),
|
||||
.disp_dpclinkdown = (ADPCLINKDOWN_TEARDOWNNOSCL | \
|
||||
ADPCLINKDOWN_TEARDOWNEN),
|
||||
.disp_dpgpreqaggr = (ADPGPREQAGGR_REQAGGRTHRESH(0x4b) | \
|
||||
ADPGPREQAGGR_CACHEHINT(0x3) | \
|
||||
ADPGPREQAGGR_REQAGGRENAB),
|
||||
.disp_dpcafclkgate = (ADPAFIDLECOUNT(0x30) | \
|
||||
ADPAFDYNCLKGATEEN),
|
||||
.disp_dpcenab = (ADPCENAB_IDEAL_ARB_ENAB),
|
||||
},
|
||||
#endif //!DISPLAY_X136_TUNABLES
|
||||
|
||||
#if DISPLAY_IPHONE_TUNABLES
|
||||
#error DISPLAY_IPHONE_TUNABLES set for IPAD
|
||||
#endif
|
||||
|
||||
#endif //DISPLAY_LANDSCAPE_IPAD_TUNABLES || DISPLAY_APPLE_TV_TUNABLES || DISPLAY_FPGA_TUNABLES
|
||||
};
|
||||
|
||||
#endif /* ! __APPLE_DISPLAY_H */
|
||||
@@ -0,0 +1,268 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_TIMINGS_H
|
||||
#define __APPLE_DISPLAY_TIMINGS_H
|
||||
|
||||
//Supported timings by this platform
|
||||
static struct display_timing timing_list[] =
|
||||
{
|
||||
#if DEBUG_BUILD || SUB_TARGET_TYPHONIC
|
||||
{
|
||||
.display_name = "D403",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 61540000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 640,
|
||||
.h_pulse_width = 6,
|
||||
.h_back_porch = 4,
|
||||
.h_front_porch = 32,
|
||||
.v_active = 1136,
|
||||
.v_pulse_width = 3,
|
||||
.v_back_porch = 13,
|
||||
.v_front_porch = 352,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_PINOT,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || SUB_TARGET_N102
|
||||
{
|
||||
.display_name = "D410",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 61540000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 640,
|
||||
.h_pulse_width = 6,
|
||||
.h_back_porch = 4,
|
||||
.h_front_porch = 32,
|
||||
.v_active = 1136,
|
||||
.v_pulse_width = 3,
|
||||
.v_back_porch = 13,
|
||||
.v_front_porch = 352,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_PINOT,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || SUB_TARGET_N61 || SUB_TARGET_TYPHONIC
|
||||
{
|
||||
.display_name = "D500",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 88890000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 750,
|
||||
.h_pulse_width = 6,
|
||||
.h_back_porch = 28,
|
||||
.h_front_porch = 4,
|
||||
.v_active = 1334,
|
||||
.v_pulse_width = 3,
|
||||
.v_back_porch = 4,
|
||||
.v_front_porch = 540,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_PINOT,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || SUB_TARGET_N56
|
||||
{
|
||||
.display_name = "D600",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 200000000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 1080,
|
||||
.h_pulse_width = 2,
|
||||
.h_back_porch = 4,
|
||||
.h_front_porch = 146,
|
||||
.v_active = 1920,
|
||||
.v_pulse_width = 3,
|
||||
.v_back_porch = 5,
|
||||
.v_front_porch = 778,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_PINOT,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || SUB_TARGET_T7000FPGA || SUB_TARGET_T7001FPGA
|
||||
{
|
||||
.display_name = "fpga-wsvga",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 5000000,
|
||||
.dot_pitch = 243,
|
||||
.h_active = 1024,
|
||||
.h_pulse_width = 50,
|
||||
.h_back_porch = 50,
|
||||
.h_front_porch = 51,
|
||||
.v_active = 600,
|
||||
.v_pulse_width = 50,
|
||||
.v_back_porch = 218,
|
||||
.v_front_porch = 6,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 18,
|
||||
.display_type = DISPLAY_TYPE_DUMB,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || SUB_TARGET_J96 || SUB_TARGET_J97
|
||||
{
|
||||
.display_name = "ipad5",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 200000000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 1536,
|
||||
.h_pulse_width = 16,
|
||||
.h_back_porch = 48,
|
||||
.h_front_porch = 12,
|
||||
.v_active = 2048,
|
||||
.v_pulse_width = 4,
|
||||
.v_back_porch = 8,
|
||||
.v_front_porch = 8,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_EDP,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || SUB_TARGET_J81 || SUB_TARGET_J82 || SUB_TARGET_T7001PADSIM
|
||||
{
|
||||
.display_name = "ipad4",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 200000000,
|
||||
.dot_pitch = 264,
|
||||
.h_active = 1536,
|
||||
.h_pulse_width = 15,
|
||||
.h_back_porch = 52,
|
||||
.h_front_porch = 16,
|
||||
.v_active = 2048,
|
||||
.v_pulse_width = 1,
|
||||
.v_back_porch = 3,
|
||||
.v_front_porch = 7,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_EDP,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || SUB_TARGET_J98 || SUB_TARGET_J99
|
||||
{
|
||||
.display_name = "ipad5c",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 400000000,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 2732,
|
||||
.h_pulse_width = 20,
|
||||
.h_back_porch = 56,
|
||||
.h_front_porch = 16,
|
||||
.v_active = 2048,
|
||||
.v_pulse_width = 2,
|
||||
.v_back_porch = 4,
|
||||
.v_front_porch = 307,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_EDP,
|
||||
.display_config = NULL,
|
||||
},
|
||||
|
||||
{
|
||||
.display_name = "j99POC",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 342857142,
|
||||
.dot_pitch = 326,
|
||||
.h_active = 2732,
|
||||
.h_pulse_width = 16,
|
||||
.h_back_porch = 52,
|
||||
.h_front_porch = 16,
|
||||
.v_active = 2048,
|
||||
.v_pulse_width = 4,
|
||||
.v_back_porch = 2,
|
||||
.v_front_porch = 6,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_EDP,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
#if DEBUG_BUILD || WITH_HW_DISPLAY_DISPLAYPORT
|
||||
{
|
||||
.display_name = "720p",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 74250000,
|
||||
.dot_pitch = 243,
|
||||
.h_active = 1280,
|
||||
.h_pulse_width = 40,
|
||||
.h_back_porch = 110,
|
||||
.h_front_porch = 220,
|
||||
.v_active = 720,
|
||||
.v_pulse_width = 5,
|
||||
.v_back_porch = 5,
|
||||
.v_front_porch = 20,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_DP,
|
||||
.display_config = NULL,
|
||||
},
|
||||
{
|
||||
.display_name = "720p-e86",
|
||||
.host_clock_id = CLK_VCLK0,
|
||||
.pixel_clock = 74250000,
|
||||
.dot_pitch = 243,
|
||||
.h_active = 1280,
|
||||
.h_pulse_width = 40,
|
||||
.h_back_porch = 110,
|
||||
.h_front_porch = 220,
|
||||
.v_active = 720,
|
||||
.v_pulse_width = 5,
|
||||
.v_back_porch = 5,
|
||||
.v_front_porch = 20,
|
||||
.neg_vclk = 0,
|
||||
.neg_hsync = 0,
|
||||
.neg_vsync = 0,
|
||||
.neg_vden = 0,
|
||||
.display_depth = 24,
|
||||
.display_type = DISPLAY_TYPE_DP,
|
||||
.display_config = NULL,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
#endif /* ! __APPLE_DISPLAY_TIMINGS_H */
|
||||
@@ -0,0 +1,138 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWCLOCKS_H
|
||||
#define __PLATFORM_SOC_HWCLOCKS_H
|
||||
|
||||
#include <platform/clocks.h>
|
||||
|
||||
#if SUPPORT_FPGA
|
||||
#define OSC_FREQ (5000000UL)
|
||||
#else
|
||||
#define OSC_FREQ (24000000UL)
|
||||
#endif
|
||||
|
||||
// Start from an offset of 128. So that we are safely outside the PS indexes.
|
||||
#define CLK_FCLK (HWCLOCK_BASE+128)
|
||||
#define CLK_ACLK (HWCLOCK_BASE+129)
|
||||
#define CLK_HCLK (HWCLOCK_BASE+130)
|
||||
#define CLK_PCLK (HWCLOCK_BASE+131)
|
||||
#define CLK_VCLK0 (HWCLOCK_BASE+132)
|
||||
#define CLK_VCLK1 (HWCLOCK_BASE+133)
|
||||
#define CLK_MCLK (HWCLOCK_BASE+134)
|
||||
#define CLK_NCLK (HWCLOCK_BASE+135)
|
||||
#define CLK_USBPHYCLK (HWCLOCK_BASE+136)
|
||||
#define CLK_NCOREF (HWCLOCK_BASE+137)
|
||||
#define CLK_ANS_LINK (HWCLOCK_BASE+138)
|
||||
|
||||
/*
|
||||
* T7000 clock gate devices.
|
||||
* Refers to the ps register offsets.
|
||||
*/
|
||||
enum { // enum : reg
|
||||
CLK_CPU0, // 0: 0x20000
|
||||
CLK_CPU1, // 1: 0x20008
|
||||
#if SUB_PLATFORM_T7001
|
||||
CLK_CPU2, // 1: 0x20010
|
||||
#endif
|
||||
CLK_CPM = 8, // 8: 0x20040
|
||||
CLK_LIO = 32, // 32: 0x20100
|
||||
CLK_IOMUX, // 33: 0x20108
|
||||
CLK_AIC, // 34: 0x20110
|
||||
CLK_DEBUG, // 35: 0x20118
|
||||
CLK_DWI, // 36: 0x20120
|
||||
CLK_GPIO, // 37: 0x20128
|
||||
CLK_MCA0, // 38: 0x20130
|
||||
CLK_MCA1, // 39: 0x20138
|
||||
CLK_MCA2, // 40: 0x20140
|
||||
CLK_MCA3, // 41: 0x20148
|
||||
CLK_MCA4, // 42: 0x20150
|
||||
CLK_PWM0, // 43: 0x20158
|
||||
CLK_I2C0, // 44: 0x20160
|
||||
CLK_I2C1, // 45: 0x20168
|
||||
CLK_I2C2, // 46: 0x20170
|
||||
CLK_I2C3, // 47: 0x20178
|
||||
CLK_SPI0, // 48: 0x20180
|
||||
CLK_SPI1, // 49: 0x20188
|
||||
CLK_SPI2, // 50: 0x20190
|
||||
CLK_SPI3, // 51: 0x20198
|
||||
CLK_UART0, // 52: 0x201a0
|
||||
CLK_UART1, // 53: 0x201a8
|
||||
CLK_UART2, // 54: 0x201b0
|
||||
CLK_UART3, // 55: 0x201b8
|
||||
CLK_UART4, // 56: 0x201c0
|
||||
CLK_UART5, // 57: 0x201c8
|
||||
CLK_UART6, // 58: 0x201d0
|
||||
CLK_UART7, // 59: 0x201d8
|
||||
CLK_UART8, // 60: 0x201e0
|
||||
CLK_AES0, // 61: 0x201e8
|
||||
CLK_SIO, // 62: 0x201f0
|
||||
CLK_SIO_P, // 63: 0x201f8
|
||||
CLK_HSIC0PHY, // 64: 0x20200
|
||||
CLK_HSIC1PHY, // 65: 0x20208
|
||||
CLK_ISPSENS0, // 66: 0x20210
|
||||
CLK_ISPSENS1, // 67: 0x20218
|
||||
CLK_PCIE_REF, // 68: 0x20220
|
||||
CLK_ANP, // 69: 0x20228
|
||||
CLK_MCC, // 70: 0x20230
|
||||
CLK_MCU, // 71: 0x20238
|
||||
CLK_AMP, // 72: 0x20240
|
||||
CLK_USB, // 73: 0x20248
|
||||
CLK_USBCTLREG, // 74: 0x20250
|
||||
CLK_USB2HOST0, // 75: 0x20258
|
||||
CLK_USB2HOST0_OHCI, // 76: 0x20260
|
||||
CLK_USB2HOST1, // 77: 0x20268
|
||||
CLK_USB2HOST1_OHCI, // 78: 0x20270
|
||||
CLK_USB2HOST2, // 79: 0x20278
|
||||
CLK_USB2HOST2_OHCI, // 80: 0x20280
|
||||
CLK_USB_OTG, // 81: 0x20288
|
||||
CLK_SMX, // 82: 0x20290
|
||||
CLK_SF, // 83: 0x20298
|
||||
CLK_CP, // 84: 0x202a0
|
||||
#if SUB_PLATFORM_T7000
|
||||
CLK_DISP_BUSMUX, // 85: 0x202a8
|
||||
#elif SUB_PLATFORM_T7001
|
||||
CLK_DISP0_BUSIF, // 85: 0x202a8
|
||||
#endif
|
||||
CLK_DISP0, // 86: 0x202b0
|
||||
#if SUB_PLATFORM_T7000
|
||||
CLK_MIPI_DSI, // 87: 0x202b8
|
||||
CLK_MIPI = CLK_MIPI_DSI,
|
||||
CLK_DP, // 88: 0x202c0
|
||||
CLK_EDPLINK = CLK_DP,
|
||||
CLK_DPLINK = CLK_DP,
|
||||
#elif SUB_PLATFORM_T7001
|
||||
CLK_DP, // 87: 0x202b8
|
||||
CLK_EDPLINK = CLK_DP,
|
||||
CLK_DPLINK = CLK_DP,
|
||||
CLK_DISP1_BUSIF, // 88: 0x202c0
|
||||
#endif
|
||||
CLK_DISP1, // 89: 0x202c8
|
||||
CLK_ISP, // 90: 0x202d0
|
||||
CLK_MEDIA, // 91: 0x202d8
|
||||
CLK_MSR, // 92: 0x202e0
|
||||
CLK_JPG, // 93: 0x202e8
|
||||
CLK_VDEC0, // 94: 0x202f0
|
||||
CLK_UNUSED_0, // 95: 0x202f8 UNUSED
|
||||
CLK_VENC_CPU, // 96: 0x20300
|
||||
CLK_PCIE, // 97: 0x20308
|
||||
CLK_PCIE_AUX, // 98: 0x20310
|
||||
CLK_ANS, // 99: 0x20318
|
||||
CLK_GFX, // 100: 0x20320
|
||||
|
||||
PMGR_LAST_DEVICE,
|
||||
PMGR_FIRST_DEVICE = CLK_LIO,
|
||||
CLK_SEP = 128, // 128: 0x20400
|
||||
CLK_VENC_PIPE = 512, // 512: 0x21000
|
||||
CLK_VENC_ME0, // 513: 0x21008
|
||||
CLK_VENC_ME1, // 514: 0x21010
|
||||
};
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWCLOCKS_H */
|
||||
@@ -0,0 +1,299 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWISR_H
|
||||
#define __PLATFORM_SOC_HWISR_H
|
||||
|
||||
#define INT_SW0 0 // 0x00: Software 0 Interrupt
|
||||
#define INT_SW1 1 // 0x01: Software 1 Interrupt
|
||||
#define INT_SW2 2 // 0x02: Software 2 Interrupt
|
||||
#define INT_SW3 3 // 0x03: Software 3 Interrupt
|
||||
#define INT_WDT 4 // 0x04: Watchdog Timer Interrupt
|
||||
#define INT_DWI 5 // 0x05: DWI Interrupt
|
||||
#define INT_PMGR_PERF_CNTRS 6 // 0x06: PMGR Performace Counters Interrupt
|
||||
#define INT_THERM_TEMP0 7 // 0x07: Thermal Temp 0 Interrupt
|
||||
#define INT_THERM_ALARM0 8 // 0x08: Thermal Alarm 0 Interrupt
|
||||
#define INT_THERM_TEMP1 9 // 0x09: Thermal Temp 1 Interrupt
|
||||
#define INT_THERM_ALARM1 10 // 0x0a: Thermal Alarm 1 Interrupt
|
||||
|
||||
// Reserved 11 - 21
|
||||
|
||||
#define INT_CPM_THERM_TEMP 22 // 0x16: CPM Thermal temp Interrupt
|
||||
#define INT_CPM_THERM_ALARM 23 // 0x17: CPM Thermal alarm Interrupt
|
||||
#define INT_CPU0_THERM_TEMP 24 // 0x18: CPU0 Thermal temp Interrupt
|
||||
#define INT_CPU0_THERM_ALARM 25 // 0x19: CPU0 Thermal alarm Interrupt
|
||||
#define INT_CPU1_THERM_TEMP 26 // 0x1a: CPU1 Thermal temp Interrupt
|
||||
#define INT_CPU1_THERM_ALARM 27 // 0x1b: CPU1 Thermal alarm Interrupt
|
||||
#if SUB_PLATFORM_T7001
|
||||
#define INT_CPU2_THERM_TEMP 28 // 0x1c: CPU2 Thermal temp Interrupt
|
||||
#define INT_CPU2_THERM_ALARM 29 // 0x1d: CPU2 Thermal alarm Interrupt
|
||||
#endif
|
||||
|
||||
// Reserved 28 - 35 (T7000)
|
||||
// Reserved 30 - 35 (T7001)
|
||||
|
||||
#define INT_ANS_KF_INBOX_EMPTY 36 // 0x24: ANS KF Inbox Empty Interrupt
|
||||
#define INT_ANS_KF_INBOX_NOTEMPTY 37 // 0x25: ANS KF Inbox Not Empty Interrupt
|
||||
#define INT_ANS_KF_OUTBOX_EMPTY 38 // 0x26: ANS KF Outbox Empty Interrupt
|
||||
#define INT_ANS_KF_OUTBOX_NOTEMPTY 39 // 0x27: ANS KF Outbox Not Empty Interrupt
|
||||
#define INT_ANS_CHNL0 40 // 0x28: ANS Channel 0 Interrupt
|
||||
#define INT_ANS_CHNL1 41 // 0x29: ANS Channel 1 Interrupt
|
||||
|
||||
// Reserved 42 - 46
|
||||
|
||||
#define INT_THERM_FS_ACT0 47 // 0x2f: Thermal Failsafe Active 0 Interrupt
|
||||
#define INT_THERM_FS_ACT1 48 // 0x30: Thermal Failsafe Active 1 Interrupt
|
||||
#define INT_THERM_FS_EXT0 49 // 0x31: Thermal Failsafe Exit 0 Interrupt
|
||||
#define INT_THERM_FS_EXT1 50 // 0x32: Thermal Failsafe Exit 1 Interrupt
|
||||
#define INT_SOC_THERM_FS_ACT0 51 // 0x33: SoC Thermal Failsafe Active 0 Interrupt
|
||||
#define INT_SOC_THERM_FS_ACT1 52 // 0x34: SoC Thermal Failsafe Active 1 Interrupt
|
||||
|
||||
// Reserved 53 - 54
|
||||
|
||||
#define INT_CTM_TRIGGER0 55 // 0x37: CTM Trigger 0 Interrupt
|
||||
#define INT_CTM_TRIGGER1 56 // 0x38: CTM Trigger 1 Interrupt
|
||||
#define INT_CTM_TRIGGER2 57 // 0x39: CTM Trigger 2 Interrupt
|
||||
#define INT_CTM_TRIGGER3 58 // 0x3a: CTM Trigger 3 Interrupt
|
||||
#define INT_COHERENCE_PNT_ERR 59 // 0x3b: Coherence Point Error Interrupt
|
||||
#define INT_COHERENCE_PNT_PERF_CNTRS 60 // 0x3c: Coherence Point Performance Counters Interrupt
|
||||
|
||||
// Reserved 61
|
||||
|
||||
#define INT_GPIO_CLASS0 62 // 0x3e: GPIO Class 0 Interrupt
|
||||
#define INT_GPIO_CLASS1 63 // 0x3f: GPIO Class 1 Interrupt
|
||||
#define INT_GPIO_CLASS2 64 // 0x40: GPIO Class 2 Interrupt
|
||||
#define INT_GPIO_CLASS3 65 // 0x41: GPIO Class 3 Interrupt
|
||||
#define INT_GPIO_CLASS4 66 // 0x42: GPIO Class 4 Interrupt
|
||||
#define INT_GPIO_CLASS5 67 // 0x43: GPIO Class 5 Interrupt
|
||||
#define INT_GPIO_CLASS6 68 // 0x44: GPIO Class 6 Interrupt
|
||||
|
||||
// Reserved 61
|
||||
|
||||
#define INT_MEM_CONTROLLER 70 // 0x46: Memory Controller MCC Interrupt
|
||||
#define INT_MCU 71 // 0x47: Memory Controller MCU Interrupt
|
||||
|
||||
// Reserved 72
|
||||
|
||||
#define INT_CPU0_COMM_TX 73 // 0x49: CPU 0 COMM TX Interrupt
|
||||
#define INT_CPU0_COMM_RX 74 // 0x4a: CPU 0 COMM RX Interrupt
|
||||
#define INT_CPU0_PMU_IRQ 75 // 0x4b: CPU 0 PMU IRQ Interrupt
|
||||
#define INT_CPU1_COMM_TX 76 // 0x4c: CPU 1 COMM TX Interrupt
|
||||
#define INT_CPU1_COMM_RX 77 // 0x4d: CPU 1 COMM RX Interrupt
|
||||
#define INT_CPU1_PMU_IRQ 78 // 0x4e: CPU 1 PMU IRQ Interrupt
|
||||
#if SUB_PLATFORM_T7001
|
||||
#define INT_CPU2_COMM_TX 79 // 0x4f: CPU 2 COMM TX Interrupt
|
||||
#define INT_CPU2_COMM_RX 80 // 0x50: CPU 2 COMM RX Interrupt
|
||||
#define INT_CPU2_PMU_IRQ 81 // 0x51: CPU 2 PMU IRQ Interrupt
|
||||
#endif
|
||||
|
||||
// Reserved 79 - 84 (T7000)
|
||||
// Reserved 82 - 84 (T7001)
|
||||
|
||||
#define INT_CCC_UNIFIED_TRIGGER 85 // 0x55: CCC Unified Trigger Interrupt
|
||||
|
||||
// Reserved 86
|
||||
|
||||
#define INT_ISP_KF_INBOX_EMPTY 87 // 0x57: ISP KF Inbox Empty Interrupt
|
||||
#define INT_ISP_KF_INBOX_NOTEMPTY 88 // 0x58: ISP KF Inbox Not Empty Interrupt
|
||||
#define INT_ISP_KF_OUTBOX_EMPTY 89 // 0x59: ISP KF Outbox Empty Interrupt
|
||||
#define INT_ISP_KF_OUTBOX_NOTEMPTY 90 // 0x5a: ISP KF Outbox Not Empty Interrupt
|
||||
#define INT_ISP0 91 // 0x5b: ISP 0 Interrupt
|
||||
#define INT_ISP1 92 // 0x5c: ISP 1 Interrupt
|
||||
#define INT_ISP2 93 // 0x5d: ISP 2 Interrupt
|
||||
#define INT_ISP3 94 // 0x5e: ISP 3 Interrupt
|
||||
#define INT_ISP_DART 95 // 0x5f: ISP DART Interrupt
|
||||
|
||||
// Reserved 96
|
||||
|
||||
#define INT_SEP_KF_INBOX_EMPTY 97 // 0x61: SEP KF Inbox Empty Interrupt
|
||||
#define INT_SEP_KF_INBOX_NOTEMPTY 98 // 0x62: SEP KF Inbox Not Empty Interrupt
|
||||
#define INT_SEP_KF_OUTBOX_EMPTY 99 // 0x63: SEP KF Outbox Empty Interrupt
|
||||
#define INT_SEP_KF_OUTBOX_NOTEMPTY 100 // 0x64: SEP KF Outbox Not Empty Interrupt
|
||||
#define INT_SEP_AUTH_ERROR 101 // 0x65: SEP Authentication Error Interrupt
|
||||
#define INT_SEP_CRIT_PATH_MONITOR 102 // 0x66: SEP Critical Path Monitor Interrupt
|
||||
#define INT_DISP0 103 // 0x67: Display 0 Interrupt
|
||||
#define INT_DISP0_PARTIAL_FRAME 104 // 0x68: Display 0 Partial Frame Interrupt
|
||||
#define INT_DISP0_PERF_CNTRS 105 // 0x69: Display 0 Performace Counters Interrupt
|
||||
#define INT_DISP0_DART 106 // 0x6a: Display 0 DART Interrupt
|
||||
#define INT_DISP0_SMMU 107 // 0x6b: Display 0 SMMU Interrupt
|
||||
#define INT_DISP0_BACK_END_BLU 108 // 0x6c: Display 0 Back End Back Light Update Interrupt
|
||||
#define INT_DISP0_BACK_END_VBI 109 // 0x6d: Display 0 Back End VBI Interrupt
|
||||
#define INT_DISP0_BACK_END_VFTG 110 // 0x6e: Display 0 Back End VFTG Idle Interrupt
|
||||
#define INT_DISP0_BACK_END_VBL 111 // 0x6f: Display 0 Back End VBL counter Interrupt
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define INT_MIPIDSI0 112 // 0x70: MIPI DSI 0 Interrupt
|
||||
#define INT_MIPIDSI1 113 // 0x71: MIPI DSI 1 Interrupt
|
||||
#define INT_DISPLAY_PORT 114 // 0x72: Display Port
|
||||
#define INT_EDP0 INT_DISPLAY_PORT
|
||||
#define INT_DPORT0 INT_DISPLAY_PORT
|
||||
#else
|
||||
#define INT_DISPLAY_PORT 112 // 0x70: Display Port
|
||||
#define INT_EDP0 INT_DISPLAY_PORT
|
||||
#define INT_DPORT0 INT_DISPLAY_PORT
|
||||
#endif
|
||||
#define INT_DISP1 115 // 0x73: Display 1 Interrupt
|
||||
#define INT_DISP1_PARTIAL_FRAME 116 // 0x74: Display 1 Partial Frame Interrupt
|
||||
#define INT_DISP1_PERF_CNTRS 117 // 0x75: Display 1 Performace Counters Interrupt
|
||||
#define INT_DISP1_DART 118 // 0x76: Display 1 DART Interrupt
|
||||
#define INT_DISP1_SMMU 119 // 0x77: Display 1 SMMU Interrupt
|
||||
#define INT_VDEC0 120 // 0x78: Video Decoder 0 Interrupt
|
||||
|
||||
// Reserved 121 - 122
|
||||
|
||||
#define INT_AVE_KF_INBOX_EMPTY 123 // 0x7b: AVE KF Inbox Empty Interrupt
|
||||
#define INT_AVE_KF_INBOX_NOTEMPTY 124 // 0x7c: AVE KF Inbox Not Empty Interrupt
|
||||
#define INT_AVE_KF_OUTBOX_EMPTY 125 // 0x7d: AVE KF Outbox Empty Interrupt
|
||||
#define INT_AVE_KF_OUTBOX_NOTEMPTY 126 // 0x7e: AVE KF Outbox Not Empty Interrupt
|
||||
#define INT_AVE_DART 127 // 0x7f: AVE DART Interrupt
|
||||
#define INT_AVE_SMMU 128 // 0x80: AVE SMMU Interrupt
|
||||
#define INT_AVE 129 // 0x81: AVE Interrupt
|
||||
#define INT_SVE_SYNC 130 // 0x82: SVE Driver Synchronization Interrupt
|
||||
|
||||
// Reserved 131 - 133
|
||||
|
||||
#define INT_GFX 134 // 0x86: GFX Interrupt
|
||||
#define INT_GFX_SLEEP 135 // 0x87: GFX Sleep Interrupt
|
||||
#define INT_GFX_WAKE 136 // 0x88: GFX Wake Interrupt
|
||||
#define INT_GFX_CHG 137 // 0x89: GFX Change Interrupt
|
||||
|
||||
// Reserved 138
|
||||
|
||||
#define INT_JPEG 139 // 0x8b: JPEG Interrupt
|
||||
#define INT_JPEG_DART 140 // 0x8c: JPEG DART Interrupt
|
||||
#define INT_JPEG_DART_PERF 141 // 0x8d: JPEG DART Performance Interrupt
|
||||
|
||||
// Reserved 142
|
||||
|
||||
#define INT_MSR 143 // 0x8f: MSR Interrupt
|
||||
#define INT_MSR_SMMU 144 // 0x90: MSR SMMU Interrupt
|
||||
#define INT_MSR_DART 145 // 0x91: MSR DART Interrupt
|
||||
#define INT_MSR_DAR_PERF 146 // 0x92: MSR DART Performance Interrupt
|
||||
|
||||
// Reserved 147
|
||||
|
||||
#define INT_SIO_KF_INBOX_EMPTY 148 // 0x94: SIO KF Inbox Empty Interrupt
|
||||
#define INT_SIO_KF_INBOX_NOTEMPTY 149 // 0x95: SIO KF Inbox Not Empty Interrupt
|
||||
#define INT_SIO_KF_OUTBOX_EMPTY 150 // 0x96: SIO KF Outbox Empty Interrupt
|
||||
#define INT_SIO_KF_OUTBOX_NOTEMPTY 151 // 0x97: SIO KF Outbox Not Empty Interrupt
|
||||
#define INT_SPI0 152 // 0x98: SPI 0 Interrupt
|
||||
#define INT_SPI1 153 // 0x99: SPI 1 Interrupt
|
||||
#define INT_SPI2 154 // 0x9a: SPI 2 Interrupt
|
||||
#define INT_SPI3 155 // 0x9b: SPI 3 Interrupt
|
||||
|
||||
// Reserved 156 - 157
|
||||
|
||||
#define INT_UART0 158 // 0x9e: UART 0 Interrupt
|
||||
#define INT_UART1 159 // 0x9f: UART 1 Interrupt
|
||||
#define INT_UART2 160 // 0xa0: UART 2 Interrupt
|
||||
#define INT_UART3 161 // 0xa1: UART 3 Interrupt
|
||||
#define INT_UART4 162 // 0xa2: UART 4 Interrupt
|
||||
#define INT_UART5 163 // 0xa3: UART 5 Interrupt
|
||||
#define INT_UART6 164 // 0xa4: UART 6 Interrupt
|
||||
#define INT_UART7 165 // 0xa5: UART 7 Interrupt
|
||||
#define INT_UART8 166 // 0xa6: UART 8 Interrupt
|
||||
|
||||
// Reserved 167 - 168
|
||||
|
||||
#define INT_MCA0 169 // 0xa9: Multi-Channel Audio 0 Interrupt
|
||||
#define INT_MCA1 170 // 0xab: Multi-Channel Audio 1 Interrupt
|
||||
#define INT_MCA2 171 // 0xac: Multi-Channel Audio 2 Interrupt
|
||||
#define INT_MCA3 172 // 0xad: Multi-Channel Audio 3 Interrupt
|
||||
#define INT_MCA4 173 // 0xae: Multi-Channel Audio 4 Interrupt
|
||||
#define INT_IIC0 174 // 0xaf: I2C 0 Interrupt
|
||||
#define INT_IIC1 175 // 0xb0: I2C 1 Interrupt
|
||||
#define INT_IIC2 176 // 0xb1: I2C 2 Interrupt
|
||||
#define INT_IIC3 177 // 0xb2: I2C 3 Interrupt
|
||||
#define INT_PWM 178 // 0xb3: PWM Interrupt
|
||||
#define INT_AES0 179 // 0xb4: AES 0 Interrupt
|
||||
|
||||
// Reserved 180 - 181
|
||||
|
||||
#define INT_USB_OTG 182 // 0xb6: USB OTG Interrupt
|
||||
#define INT_USB2HOST0_EHCI 183 // 0xb7: USB EHCI 0 Interrupt
|
||||
#define INT_USB2HOST0_OHCI 184 // 0xb8: USB OHCI 0 Interrupt
|
||||
#define INT_USB2HOST1_EHCI 185 // 0xb9: USB EHCI 1 Interrupt
|
||||
#define INT_USB2HOST2_EHCI 186 // 0xba: USB EHCI 2 Interrupt
|
||||
#define INT_USBOTG_RESUME 187 // 0xbb: USB OTG Resume Interrupt
|
||||
#define INT_USB_20_BATT_CHRG_DET 188 // 0xbc: USB 2.0 Battery Charge Detect Interrupt
|
||||
#define INT_USB2HOST0_PHY_RESUME 189 // 0xbd: USB Host 0 Resume Interrupt
|
||||
#define INT_USB2HOST1_PHY_RESUME 190 // 0xbe: USB Host 1 Resume Interrupt
|
||||
#define INT_USB2HOST2_PHY_RESUME 191 // 0xbf: USB Host 2 Resume Interrupt
|
||||
#define INT_OTG_IN_EP0 192 // 0xc0: OTG IN Endpoint 0 Interrupt
|
||||
#define INT_OTG_IN_EP1 193 // 0xc1: OTG IN Endpoint 1 Interrupt
|
||||
#define INT_OTG_IN_EP2 194 // 0xc2: OTG IN Endpoint 2 Interrupt
|
||||
#define INT_OTG_IN_EP3 195 // 0xc3: OTG IN Endpoint 3 Interrupt
|
||||
#define INT_OTG_IN_EP4 196 // 0xc4: OTG IN Endpoint 4 Interrupt
|
||||
#define INT_OTG_IN_EP5 197 // 0xc5: OTG IN Endpoint 5 Interrupt
|
||||
#define INT_OTG_IN_EP6 198 // 0xc6: OTG IN Endpoint 6 Interrupt
|
||||
#define INT_OTG_IN_EP7 199 // 0xc7: OTG IN Endpoint 7 Interrupt
|
||||
#define INT_OTG_IN_EP8 200 // 0xc8: OTG IN Endpoint 8 Interrupt
|
||||
#define INT_OTG_OUT_EP0 201 // 0xc9: OTG OUT Endpoint 0 Interrupt
|
||||
#define INT_OTG_OUT_EP1 202 // 0xca: OTG OUT Endpoint 1 Interrupt
|
||||
#define INT_OTG_OUT_EP2 203 // 0xcb: OTG OUT Endpoint 2 Interrupt
|
||||
#define INT_OTG_OUT_EP3 204 // 0xcc: OTG OUT Endpoint 3 Interrupt
|
||||
#define INT_OTG_OUT_EP4 205 // 0xcd: OTG OUT Endpoint 4 Interrupt
|
||||
#define INT_OTG_OUT_EP5 206 // 0xce: OTG OUT Endpoint 5 Interrupt
|
||||
#define INT_OTG_OUT_EP6 207 // 0xcf: OTG OUT Endpoint 6 Interrupt
|
||||
#define INT_OTG_OUT_EP7 208 // 0xd0: OTG OUT Endpoint 7 Interrupt
|
||||
#define INT_OTG_OUT_EP8 209 // 0xd1: OTG OUT Endpoint 8 Interrupt
|
||||
|
||||
// Reserved 210 - 211
|
||||
|
||||
#define PCIE_LINK0 212 // 0xd4: PCIE Link 0 Interrupt
|
||||
#define PCIE_LINK0_DART 213 // 0xd5: PCIE Link 0 DART Interrupt
|
||||
#define PCIE_LINK0_MMU 214 // 0xd6: PCIE Link 0 MMU Interrupt
|
||||
#define PCIE_LINK1 215 // 0xd7: PCIE Link 1 Interrupt
|
||||
#define PCIE_LINK1_DART 216 // 0xd8: PCIE Link 1 DART Interrupt
|
||||
#define PCIE_LINK1_MMU 217 // 0xd9: PCIE Link 1 MMU Interrupt
|
||||
#if SUB_PLATFORM_T7001
|
||||
#define PCIE_LINK2 218 // 0xda: PCIE Link 1 Interrupt
|
||||
#define PCIE_LINK2_DART 219 // 0xdb: PCIE Link 1 DART Interrupt
|
||||
#define PCIE_LINK2_MMU 220 // 0xdc: PCIE Link 1 MMU Interrupt
|
||||
#define PCIE_LINK3 221 // 0xdd: PCIE Link 1 Interrupt
|
||||
#define PCIE_LINK3_DART 222 // 0xde: PCIE Link 1 DART Interrupt
|
||||
#define PCIE_LINK3_MMU 223 // 0xdf: PCIE Link 1 MMU Interrupt
|
||||
#endif
|
||||
|
||||
// Reserved 218 - 223 (T7000)
|
||||
|
||||
#define PCIE_MSI0 224 // 0xe0: PCIE MSI 0 Interrupt
|
||||
#define PCIE_MSI1 225 // 0xe1: PCIE MSI 1 Interrupt
|
||||
#define PCIE_MSI2 226 // 0xe2: PCIE MSI 2 Interrupt
|
||||
#define PCIE_MSI3 227 // 0xe3: PCIE MSI 3 Interrupt
|
||||
#define PCIE_MSI4 228 // 0xe4: PCIE MSI 4 Interrupt
|
||||
#define PCIE_MSI5 229 // 0xe5: PCIE MSI 5 Interrupt
|
||||
#define PCIE_MSI6 230 // 0xe6: PCIE MSI 6 Interrupt
|
||||
#define PCIE_MSI7 231 // 0xe7: PCIE MSI 7 Interrupt
|
||||
#define PCIE_MSI8 232 // 0xe8: PCIE MSI 8 Interrupt
|
||||
#define PCIE_MSI9 233 // 0xe9: PCIE MSI 9 Interrupt
|
||||
#define PCIE_MSI10 234 // 0xea: PCIE MSI 10 Interrupt
|
||||
#define PCIE_MSI11 235 // 0xeb: PCIE MSI 11 Interrupt
|
||||
#define PCIE_MSI12 236 // 0xec: PCIE MSI 12 Interrupt
|
||||
#define PCIE_MSI13 237 // 0xed: PCIE MSI 13 Interrupt
|
||||
#define PCIE_MSI14 238 // 0xee: PCIE MSI 14 Interrupt
|
||||
#define PCIE_MSI15 239 // 0xef: PCIE MSI 15 Interrupt
|
||||
#define PCIE_MSI16 240 // 0xf0: PCIE MSI 16 Interrupt
|
||||
#define PCIE_MSI17 241 // 0xf1: PCIE MSI 17 Interrupt
|
||||
#define PCIE_MSI18 242 // 0xf2: PCIE MSI 18 Interrupt
|
||||
#define PCIE_MSI19 243 // 0xf3: PCIE MSI 19 Interrupt
|
||||
#define PCIE_MSI20 244 // 0xf4: PCIE MSI 20 Interrupt
|
||||
#define PCIE_MSI21 245 // 0xf5: PCIE MSI 21 Interrupt
|
||||
#define PCIE_MSI22 246 // 0xf6: PCIE MSI 22 Interrupt
|
||||
#define PCIE_MSI23 247 // 0xf7: PCIE MSI 23 Interrupt
|
||||
#define PCIE_MSI24 248 // 0xf8: PCIE MSI 24 Interrupt
|
||||
#define PCIE_MSI25 249 // 0xf9: PCIE MSI 25 Interrupt
|
||||
#define PCIE_MSI26 250 // 0xfa: PCIE MSI 26 Interrupt
|
||||
#define PCIE_MSI27 251 // 0xfb: PCIE MSI 27 Interrupt
|
||||
#define PCIE_MSI28 252 // 0xfc: PCIE MSI 28 Interrupt
|
||||
#define PCIE_MSI29 253 // 0xfd: PCIE MSI 29 Interrupt
|
||||
#define PCIE_MSI30 254 // 0xfe: PCIE MSI 30 Interrupt
|
||||
#define PCIE_MSI31 255 // 0xff: PCIE MSI 31 Interrupt
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWISR_H */
|
||||
@@ -0,0 +1,337 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_HWREGBASE_H
|
||||
#define __PLATFORM_SOC_HWREGBASE_H
|
||||
|
||||
#include <platform/memmap.h>
|
||||
|
||||
/* T7000 and T7001 Reg Base Defs */
|
||||
|
||||
#define AMCC_BASE_ADDR (IO_BASE + 0x000000000) // AMCC Config
|
||||
#define AMCX_BASE_ADDR (IO_BASE + 0x000100000) // AMCX Config
|
||||
|
||||
#define SWTCH_FAB_BASE_ADDR (IO_BASE + 0x000800000) // Switch Fabric Config
|
||||
|
||||
#define CP_COM_BASE_ADDR (IO_BASE + 0x000D00000) // CP Common Registers
|
||||
#define CP_COM_INT_BASE_ADDR (CP_COM_BASE_ADDR + 0x10000) // CP Common Interrupt Config Registers
|
||||
|
||||
#define CP_0_DT_BASE_ADDR (IO_BASE + 0x000D20000) // Dup Tag Config and Debug
|
||||
#define CP_0_DT_DBG_CA0_ADDR (IO_BASE + 0x000D30000) // Dup Tag Debug backdoor Ram Access For CP0/CA0
|
||||
#define CP_0_CCU_CSR_BASE_ADDR (IO_BASE + 0x000D90000) // CTT and MIU Config and Debug
|
||||
#define CP_1_DT_BASE_ADDR (IO_BASE + 0x000E20000) // Dup Tag Config and Debug
|
||||
#define CP_1_DT_DBG_CA0_ADDR (IO_BASE + 0x000E30000) // Dup Tag Debug backdoor Ram Access For CP1/CA0
|
||||
#define CP_1_CCU_CSR_BASE_ADDR (IO_BASE + 0x000E90000) // CTT and MIU Config and Debug
|
||||
|
||||
#define RGX_CR_BASE_ADDR (IO_BASE + 0x001000000) // Templar4 Space
|
||||
#define GPC_BASE_ADDR (IO_BASE + 0x001e00000) // Templar4 Power Controller Space
|
||||
|
||||
#define IMGV42AF_AFC_AIU_BASE_ADDR (IO_BASE + 0x001f00000) // IMGv42AF: Local PIO Config Space of AF AIU Block
|
||||
#define IMGV42AF_AFUSR_BASE_ADDR (IO_BASE + 0x001f02000) // IMGv42AF: Bridge PIO Space
|
||||
|
||||
#define CCC_ROM_TABLE_BASE_ADDR (IO_BASE + 0x002000000) // Typhoon ROM Table
|
||||
#define CCC_CPU0_DBG_BASE_ADDR (IO_BASE + 0x002010000) // Typhoon CPU0 Debug Registers
|
||||
#define CCC_CPU0_CTI_BASE_ADDR (IO_BASE + 0x002020000) // Typhoon CPU0 CTI Registers
|
||||
#define CCC_CPU0_PMU_BASE_ADDR (IO_BASE + 0x002030000) // Typhoon CPU0 PMU Registgers
|
||||
#define CCC_CPU0_TRC_BASE_ADDR (IO_BASE + 0x002040000) // Typhoon CPU0 TRACE Registers
|
||||
#define CCC_CPU0_SYS_BASE_ADDR (IO_BASE + 0x002050000) // Typhoon CPU0 Implementation Specific Registers
|
||||
#define CCC_CPU1_DBG_BASE_ADDR (IO_BASE + 0x002110000) // Typhoon CPU1 Debug Registers
|
||||
#define CCC_CPU1_CTI_BASE_ADDR (IO_BASE + 0x002120000) // Typhoon CPU1 CTI Registers
|
||||
#define CCC_CPU1_PMU_BASE_ADDR (IO_BASE + 0x002130000) // Typhoon CPU1 PMU Registgers
|
||||
#define CCC_CPU1_TRC_BASE_ADDR (IO_BASE + 0x002140000) // Typhoon CPU1 TRACE Registers
|
||||
#define CCC_CPU1_SYS_BASE_ADDR (IO_BASE + 0x002150000) // Typhoon CPU1 Implementation Specific Registers
|
||||
#define CCC_CCC_DBG_BASE_ADDR (IO_BASE + 0x002250000) // Typhoon CCC Debug Registers
|
||||
#if SUB_PLATFORM_T7001
|
||||
#define CCC_CPU2_TRC_BASE_ADDR (IO_BASE + 0x002440000) // Typhoon CPU2 Trace Registers
|
||||
#define CCC_CPU2_SYS_BASE_ADDR (IO_BASE + 0x002450000) // Typhoon CPU2 Implementation Specific Registers
|
||||
#endif
|
||||
#define CCC0_SYS_BASE_ADDR (IO_BASE + 0x002200000) // Typhoon Core Complex Registers
|
||||
#define CCC_SOC_BUSMUX_BASE_ADDR (IO_BASE + 0x004000000) // AF SoC BusMux Config
|
||||
#define SOC_BUSMUX_BASE_ADDR (IO_BASE + 0x004000000) // AF SoC BusMux Config
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define CCC_CAM_BUSMUX_BASE_ADDR (IO_BASE + 0x005000000) // AF Camera BusMux Config
|
||||
#endif
|
||||
|
||||
#define ISP_AFC_AIU_0_BASE_ADDR (IO_BASE + 0x005B00000) // ISP AXI to AF Bridge
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define ISP_AFC_AIU_1_BASE_ADDR (IO_BASE + 0x005B10000) // ISP AXI to AF Bridge
|
||||
#endif
|
||||
#define ISP_INTR2AXI_BASE_ADDR (IO_BASE + 0x005B20000) // ISP Interrupt to AXI Widget
|
||||
#define ISP_DART_BASE_ADDR (IO_BASE + 0x005B22000) // ISP DART
|
||||
#define ISP_SMMU_BASE_ADDR (IO_BASE + 0x005B24000) // ISP SMMU
|
||||
#define ISP_ISPCTRL_R0_BASE_ADDR (IO_BASE + 0x005B40000) // SISP Region 0 Control
|
||||
#define ISP_MIPI_CSI_0_BASE_ADDR (IO_BASE + 0x005B80000) // MIPI CSI Controller
|
||||
#define ISP_MIPI_CSI_1_BASE_ADDR (IO_BASE + 0x005B81000) // MIPI CSI Controller
|
||||
#define ISP_SMB_0_BASE_ADDR (IO_BASE + 0x005B82000) // SMB Controller
|
||||
#define ISP_SMB_1_BASE_ADDR (IO_BASE + 0x005B83000) // SMB Controller
|
||||
#define ISP_FD_BASE_ADDR (IO_BASE + 0x005B84000) // Face Detect
|
||||
#define ISP_AISP_BASE_ADDR (IO_BASE + 0x005BA0000) // AISP
|
||||
#define ISP_ISPCTRL_R1_BASE_ADDR (IO_BASE + 0x005BC0000) // SISP Region 1 Control
|
||||
#define ISP_AKF_BASE_ADDR (IO_BASE + 0x005C00000) // SISP KF Widgets and Config
|
||||
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define DISP_BUSMUX_BASE_ADDR (IO_BASE + 0x006000000) // AF Display BusMux Config
|
||||
#endif
|
||||
#define DISP0_FAB_BASE_ADDR (IO_BASE + 0x006100000) // DisplayPipe0 AF and AXI Config
|
||||
#define DISP0_BASE_ADDR (IO_BASE + 0x006200000) // DisplayPipe0
|
||||
#define DISP0_ADP_BASE_ADDR (IO_BASE + 0x006200000) // DisplayPipe0 Configuration
|
||||
#define DISP0_SMMU_BASE_ADDR (IO_BASE + 0x006300000) // DisplayPipe0 SMMU Configuration
|
||||
#define DISP0_ADBE_BASE_ADDR (IO_BASE + 0x006400000) // DisplayPipe0 Backend Config
|
||||
#define DISP0_AAP_BASE_ADDR (IO_BASE + 0x006440000) // DisplayPipe0 Ambient-Adaptive Pixel Config
|
||||
#define DISP0_DPB_BASE_ADDR (IO_BASE + 0x006480000) // DisplayPipe0 Pixel Backlight Config
|
||||
#define DISP0_DITHER_BASE_ADDR (IO_BASE + 0x0064C0000) // DisplayPipe0 Dither Config
|
||||
#define DITHER_BASE_ADDR DISP0_DITHER_BASE_ADDR
|
||||
#define DITHER_VERSION (3)
|
||||
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define DISP0_MIPI_DSI_BASE_ADDR (IO_BASE + 0x006600000) // DisplayPipe0 MIPI DSI Config
|
||||
#endif
|
||||
#define DISP0_DPTX_BASE_ADDR (IO_BASE + 0x006700000) // DisplayPipe0 DisplayPort TX Config
|
||||
|
||||
#define DISP1_FAB_BASE_ADDR (IO_BASE + 0x006900000) // DisplayPipe1 AF and AXI Config
|
||||
#define DISP1_BASE_ADDR (IO_BASE + 0x006A00000) // DisplayPipe1
|
||||
#define DISP1_ADP_BASE_ADDR (IO_BASE + 0x006A00000) // DisplayPipe1 Ambient-Adaptive Pixel Config
|
||||
#define DISP1_SMMU_BASE_ADDR (IO_BASE + 0x006B00000) // DisplayPipe1 SMMU Configuration
|
||||
|
||||
#define DISP1_MEDIA_BUSMUX_BASE_ADDR (IO_BASE + 0x007000000) // DisplayPipe1 AF Media BusMux Config
|
||||
|
||||
#define MSR_AFC_AIU_BASE_ADDR (IO_BASE + 0x007800000) // MSR AXI2AF AFC_AIU
|
||||
#define MSR_BASE_ADDR (IO_BASE + 0x007900000) // Memory Scalar Rotator
|
||||
#define MSR_SMMU_BASE_ADDR (IO_BASE + 0x007904000) // MSR SMMU
|
||||
#define MSR_DART_BASE_ADDR (IO_BASE + 0x007908000) // DART for MSR SMMU
|
||||
#define MSR_INTR2AXI_BASE_ADDR (IO_BASE + 0x00790C000) // MSR Interrupt to AXI Widget
|
||||
|
||||
#define AJPEG_AFC_AIU_BASE_ADDR (IO_BASE + 0x007A00000) // AJPEG AXI2AF AFC_AIU
|
||||
#define AJPEG_BASE_ADDR (IO_BASE + 0x007B00000) // AJPEG Wrap
|
||||
#define AJPEG_DART_BASE_ADDR (IO_BASE + 0x007B02000) // AJPEG DART
|
||||
#define AJPEG_INTR2AXI_BASE_ADDR (IO_BASE + 0x007B04000) // AJPEG Interrupt to AXI Widget
|
||||
|
||||
#define SVE_BASE_ADDR (IO_BASE + 0x007C00000) // SVE Video Encoder Subsystem
|
||||
#define SVE_AVE_AXI2AF (IO_BASE + 0x007C00000) // SVE AVE AXI to Apple Fabric Bridge
|
||||
#define SVE_AFC_AIU_BASE_ADDR (IO_BASE + 0x007C00000) // SVE AXI2AF AFC_AIU
|
||||
#define SVE_INTR2AXI_BASE_ADDR (IO_BASE + 0x007C10000) // SVE VENC Interrupt to AXI Widget
|
||||
#define SVE_SMMU_BASE_ADDR (IO_BASE + 0x007C20000) // SVE Streaming MMU for AVE
|
||||
#define SVE_DART_BASE_ADDR (IO_BASE + 0x007C30000) // SVE DART for AVE SMMU
|
||||
#define SVE_PL301_BASE_ADDR (IO_BASE + 0x007C40000) // SVE PL301 Config
|
||||
#define SVE_AKF_BASE_ADDR (IO_BASE + 0x007C80000) // SVE Kingfisher Wrapper Configuration
|
||||
// XXX #define SVE_AVE_KF_DBG_BASE_ADDR (IO_BASE + 0x007CA0000) // SVE Kingfisher Wrapper Debug APB
|
||||
#define SVE_CTRL_BASE_ADDR (IO_BASE + 0x007CC0000) // SVE Control Registers
|
||||
|
||||
#define VXD_AFC_AIU_BASE_ADDR (IO_BASE + 0x007E00000) // VXD AXI2AF AFC_AIU
|
||||
#define VXD_INTR2AXI_BASE_ADDR (IO_BASE + 0x007E10000) // VXD Interrupt to AXI Widget
|
||||
#define VXD_PL301_BASE_ADDR (IO_BASE + 0x007E20000) // VXD PL301 Config
|
||||
#define VXD_CFG_BASE_ADDR (IO_BASE + 0x007F00000) // VXD Config Registers
|
||||
|
||||
#define ANS_AFC_AIU_BASE_ADDR (IO_BASE + 0x008000000) // ANS AXI2AF AFC_AIU
|
||||
#define ANS_PL301_BASE_ADDR (IO_BASE + 0x008010000) // ANS PL301 Config
|
||||
#define ANS_AKF_PL301_TLMT_BASE_ADDR (IO_BASE + 0x008020000) // ANS KF Transaction Limit Widget
|
||||
#define ANS_AKF_INTR2AXI_BASE_ADDR (IO_BASE + 0x008021000) // ANS KF Interrupt to AXI Widget
|
||||
#define ANS_ANC_PL301_TLMT_0_BASE_ADDR (IO_BASE + 0x008030000) // ANS NAND Controller Transaction Limit Widget
|
||||
#define ANS_ANC_PL301_TLMT_1_BASE_ADDR (IO_BASE + 0x008031000) // ANS NAND Controller Transaction Limit Widget
|
||||
#define ANS_ANC_INTR2AXI_0_BASE_ADDR (IO_BASE + 0x008038000) // ANS NAND Controller Interrupt to AXI Widget
|
||||
#define ANS_ANC_INTR2AXI_1_BASE_ADDR (IO_BASE + 0x008039000) // ANS NAND Controller Interrupt to AXI Widget
|
||||
#define ANS_AKF_BASE_ADDR (IO_BASE + 0x008040000) // ANS KF Wrapper
|
||||
// XXX AKF DBG (IO_BASE + 0x008060000) - (IO_BASE + 0x008070000)
|
||||
#define ANS_CFG_BASE_BADDR (IO_BASE + 0x008080000) // ANS Config
|
||||
#define ANS_PPN_N_PL_BASE_ADDR (IO_BASE + 0x008081000) // ANS PPN-N-PL Config
|
||||
#define ANS_ANC_BASE_ADDR (IO_BASE + 0x008700000) // ANC Broadcast writes to all ANCs
|
||||
#define ANS_ANC_0_BASE_ADDR (IO_BASE + 0x008800000) // ANS NAND Controller 0
|
||||
#define ANS_ANC_1_BASE_ADDR (IO_BASE + 0x008900000) // ANS NAND Controller 1
|
||||
#define ANS_IO_BUSMUX_BASE_ADDR (IO_BASE + 0x009000000) // ANS AF IO BusMux Config
|
||||
|
||||
#define IOBUSMUX_BASE_ADDR (IO_BASE + 0x009000000) // IO BusMux Config
|
||||
|
||||
#define SB_BASE_ADDR (IO_BASE + 0x00A000000) // South Bridge
|
||||
|
||||
#define ASIO_MISC_0_BASE_ADDR (IO_BASE + 0x00A000000) // ASIO Shim0 Misc Registers
|
||||
#define ASIO_AUD_MUX_BASE_ADDR (IO_BASE + 0x00A003000) // ASIO Audio I2S Switch Config
|
||||
#define ASIO_SPI_BASE_ADDR (IO_BASE + 0x00A080000) // ASIO SPI Device
|
||||
#define ASIO_SPI_TX_CFG_BASE_ADDR (IO_BASE + 0x00A081000) // ASIO SPI TX DMA Channel
|
||||
#define ASIO_SPI_RX_CFG_BASE_ADDR (IO_BASE + 0x00A081800) // ASIO SPI RX DMA Channel
|
||||
#define ASIO_SPI_TX_FIFO_BASE_ADDR (IO_BASE + 0x00A082000) // ASIO SPI TX DMA Shim FIFO
|
||||
#define ASIO_SPI_RX_FIFO_BASE_ADDR (IO_BASE + 0x00A083000) // ASIO SPI RX DMA Shim FIFO
|
||||
#define ASIO_MCA_BASE_ADDR (IO_BASE + 0x00A0A0000) // ASIO MCA Device
|
||||
#define ASIO_MCA_TX_CFG_BASE_ADDR (IO_BASE + 0x00A0A1000) // ASIO MCA TX DMA Channel
|
||||
#define ASIO_MCA_RX_CFG_BASE_ADDR (IO_BASE + 0x00A0A1800) // ASIO MCA RX DMA Channel
|
||||
#define ASIO_MCA_TX_FIFO_BASE_ADDR (IO_BASE + 0x00A0A2000) // ASIO MCA TX DMA Shim FIFO
|
||||
#define ASIO_MCA_RX_FIFO_BASE_ADDR (IO_BASE + 0x00A0A3000) // ASIO MCA RX DMA Shim FIFO
|
||||
#define ASIO_UART_BASE_ADDR (IO_BASE + 0x00A0C0000) // ASIO UART Device
|
||||
#define ASIO_UART_TX_CFG_BASE_ADDR (IO_BASE + 0x00A0C1000) // ASIO UART TX DMA Channel
|
||||
#define ASIO_UART_RX_CFG_BASE_ADDR (IO_BASE + 0x00A0C1800) // ASIO UART RX DMA Channel
|
||||
#define ASIO_UART_TX_FIFO_BASE_ADDR (IO_BASE + 0x00A0C2000) // ASIO UART TX DMA Shim FIFO
|
||||
#define ASIO_UART_RX_FIFO_BASE_ADDR (IO_BASE + 0x00A0C3000) // ASIO UART RX DMA Shim FIFO
|
||||
#define ASIO_MISC_1_BASE_ADDR (IO_BASE + 0x00A100000) // ASIO Shim1 Misc Registers
|
||||
#define ASIO_AES_BASE_ADDR (IO_BASE + 0x00A108000) // ASIO AES Config and DMA Registers
|
||||
#define ASIO_SMB_0_BASE_ADDR (IO_BASE + 0x00A110000) // ASIO I2C 0 Device
|
||||
#define ASIO_SMB_1_BASE_ADDR (IO_BASE + 0x00A111000) // ASIO I2C 1 Device
|
||||
#define ASIO_SMB_2_BASE_ADDR (IO_BASE + 0x00A112000) // ASIO I2C 2 Device
|
||||
#define ASIO_SMB_3_BASE_ADDR (IO_BASE + 0x00A113000) // ASIO I2C 3 Device
|
||||
#define ASIO_PWM_BASE_ADDR (IO_BASE + 0x00A118000) // ASIO PWM
|
||||
#define ASIO_DNSZ_AXI_0_BASE_ADDR (IO_BASE + 0x00A141000) // ASIO Downsizer 0 Configuration Registers
|
||||
#define ASIO_DNSZ_AXI_1_BASE_ADDR (IO_BASE + 0x00A142000) // ASIO Downsizer 1 Configuration Registers
|
||||
#define ASIO_AKF_BASE_ADDR (IO_BASE + 0x00AE00000) // ASIO KF Wrapper
|
||||
// XXX ASIO AKF DBG
|
||||
|
||||
#define AUSB_CTL_REG_BASE_ADDR (IO_BASE + 0x00C000000) // USBCTL Config
|
||||
#define AUSB_CTL_USB20PHY_REG_OFFSET (0x30) // USB20PHY Register offset within AUSBCTL registers
|
||||
#define AUSB_OTG_BASE_ADDR (IO_BASE + 0x00C100000) // USB OTG
|
||||
#define AUSB_USB2HOST0_EHCI_BASE_ADDR (IO_BASE + 0x00C200000) // EHCI0
|
||||
#define AUSB_USB2HOST0_OHCI_BASE_ADDR (IO_BASE + 0x00C300000) // OHCI0
|
||||
#define AUSB_USB2HOST1_EHCI_BASE_ADDR (IO_BASE + 0x00C400000) // EHCI1
|
||||
#define AUSB_USB2HOST1_OHCI_BASE_ADDR (IO_BASE + 0x00C500000) // OHCI1
|
||||
#define AUSB_PL301_BASE_ADDR (IO_BASE + 0x00C800000) // AUSB PL301 4-AHB Master to 1-AXI Slave
|
||||
#define AUSB_PL301_WIDGET_BASE_ADDR (IO_BASE + 0x00C900000) // AUSB PL301 Widget
|
||||
#define AUSB_INTR2AXI_BASE_ADDR (IO_BASE + 0x00CA00000) // AUSB Interrupt to AXI Widget
|
||||
#define AUSB_AFIFO_WIDGET_BASE_ADDR (IO_BASE + 0x00CB00000) // AUSB Async FIFO
|
||||
|
||||
#define ASEP_AKF_BASE_ADDR (IO_BASE + 0x00DA00000) // ASEP AKF control Registers
|
||||
|
||||
#define PMGR_BASE_ADDR (IO_BASE + 0x00E000000) // PMGR
|
||||
|
||||
#define AIC_BASE_ADDR (IO_BASE + 0x00E100000) // AIC
|
||||
#define AIC_WIRE_VIRT_BASE_ADDR (IO_BASE + 0x00E110000) // AIC Wrapper
|
||||
|
||||
#define DWI_BASE_ADDR (IO_BASE + 0x00E200000) // DWI
|
||||
|
||||
#define GPIO_BASE_ADDR (IO_BASE + 0x00E300000) // GPIO
|
||||
|
||||
#define AMPS_0_DQ0_BASE_ADDR (IO_BASE + 0x00E400000) // AMP 0 DQ0 DRAM PHY
|
||||
#define AMPS_0_DQ1_BASE_ADDR (IO_BASE + 0x00E410000) // AMP 0 DQ1 DRAM PHY
|
||||
#define AMPS_0_CA_BASE_ADDR (IO_BASE + 0x00E420000) // AMP 0 CA DRAM PHY
|
||||
#define AMPS_1_DQ0_BASE_ADDR (IO_BASE + 0x00E430000) // AMP 1 DQ0 DRAM PHY
|
||||
#define AMPS_1_DQ1_BASE_ADDR (IO_BASE + 0x00E440000) // AMP 1 DQ1 DRAM PHY
|
||||
#define AMPS_1_CA_BASE_ADDR (IO_BASE + 0x00E450000) // AMP 1 CA DRAM PHY
|
||||
#if SUB_PLATFORM_T7001
|
||||
#define AMPS_2_DQ0_BASE_ADDR (IO_BASE + 0x00E460000) // AMP 2 DQ0 DRAM PHY
|
||||
#define AMPS_2_DQ1_BASE_ADDR (IO_BASE + 0x00E470000) // AMP 2 DQ1 DRAM PHY
|
||||
#define AMPS_2_CA_BASE_ADDR (IO_BASE + 0x00E480000) // AMP 2 CA DRAM PHY
|
||||
#define AMPS_3_DQ0_BASE_ADDR (IO_BASE + 0x00E490000) // AMP 3 DQ0 DRAM PHY
|
||||
#define AMPS_3_DQ1_BASE_ADDR (IO_BASE + 0x00E4A0000) // AMP 3 DQ1 DRAM PHY
|
||||
#define AMPS_3_CA_BASE_ADDR (IO_BASE + 0x00E4B0000) // AMP 3 CA DRAM PHY
|
||||
#endif
|
||||
|
||||
#define LIO_MEM_PL301_BASE_ADDR (IO_BASE + 0x00E900000) // PL310 for pd_lio memory
|
||||
#define LIO_PIO_PL310_BASE_ADDR (IO_BASE + 0x00E940000) // PL310 for pd_lio PIO
|
||||
#define LIO_DNSZ_AXI_BASE_ADDR (IO_BASE + 0x00E9C8000) // PL310 for pd_lio downsizer
|
||||
#define LIO_SIO_AFIFO_WIDGETS_BASE_ADDR (IO_BASE + 0x00E9C0000) // SIO Async FIFO for pd_lio
|
||||
#define LIO_DAP_AFIFO_WIDGETS_BASE_ADDR (IO_BASE + 0x00E9E0000) // DAP Async FIFO for pd_lio
|
||||
#define LIO_AFC_AIU_BASE_ADDR (IO_BASE + 0x00F010000) // LIO AXI to AF Bridge
|
||||
|
||||
#define DBG_WRP_BASE_ADDR (IO_BASE + 0x00F000000) // Debug Sub-system Config
|
||||
#define ERR_REFLECTION_BASE_ADDR (IO_BASE + 0x00FFFF000)
|
||||
|
||||
#define APCIE_VERSION (1)
|
||||
#define APCIE_COMMON_BASE_ADDR (PCI_REG_BASE + 0x000000000)
|
||||
#define APCIE_CONFIG_BASE_ADDR (PCI_REG_BASE + 0x01004000)
|
||||
#define APCIE_CONFIG_PORT_STRIDE (0x01000000)
|
||||
#define APCIE_COUNTER_BASE_ADDR (PCI_REG_BASE + 0x800)
|
||||
|
||||
/* iBoot Specific Defs */
|
||||
|
||||
#define AKF_VERSION (1)
|
||||
|
||||
#define UART0_BASE_ADDR (ASIO_UART_BASE_ADDR)
|
||||
#define UART1_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x04000)
|
||||
#define UART2_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x08000)
|
||||
#define UART3_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x0C000)
|
||||
#define UART4_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x10000)
|
||||
#define UART5_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x14000)
|
||||
#define UART6_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x18000)
|
||||
#define UART7_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x1C000)
|
||||
#define UART8_BASE_ADDR (ASIO_UART_BASE_ADDR + 0x20000)
|
||||
#define UARTS_COUNT (9)
|
||||
#define UART_VERSION (1)
|
||||
|
||||
#define SPI0_BASE_ADDR (ASIO_SPI_BASE_ADDR)
|
||||
#define SPI1_BASE_ADDR (ASIO_SPI_BASE_ADDR + 0x04000)
|
||||
#define SPI2_BASE_ADDR (ASIO_SPI_BASE_ADDR + 0x08000)
|
||||
#define SPI3_BASE_ADDR (ASIO_SPI_BASE_ADDR + 0x0C000)
|
||||
#define SPI_VERSION (1)
|
||||
#define SPIS_COUNT (4)
|
||||
|
||||
#define IIC_BASE_ADDR (ASIO_SMB_0_BASE_ADDR)
|
||||
#define IIC_SPACING (0x00001000)
|
||||
#define IICS_COUNT (4)
|
||||
|
||||
#define USBPHY_VERSION (4)
|
||||
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define DSIM_BASE_ADDR (DISP0_MIPI_DSI_BASE_ADDR)
|
||||
#define DSIM_LANE_COUNT (4)
|
||||
#define DSIM_VERSION (1)
|
||||
#endif
|
||||
|
||||
#define EDP_BASE_ADDR (DISP0_DPTX_BASE_ADDR)
|
||||
#define DP_BASE_ADDR (DISP0_DPTX_BASE_ADDR)
|
||||
#define LPDP_PHY_BASE_ADDR (DISP0_DPTX_BASE_ADDR + 0x080000)
|
||||
#define DISPLAYPORT_VERSION (3)
|
||||
|
||||
#define ADBE_DISPLAYPIPE_BASE_ADDR (DISP0_BASE_ADDR)
|
||||
#define DISP_VERSION (5)
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define ADP_VERSION (1)
|
||||
#elif SUB_PLATFORM_T7001
|
||||
#define ADP_VERSION (2)
|
||||
#endif
|
||||
|
||||
#define AMP_REG_VERSION (3)
|
||||
#define AMP_BASE_ADDR (AMPS_0_DQ0_BASE_ADDR)
|
||||
#define AMP_SPACING (0x00030000)
|
||||
#define AMP_DQCA_SPACING (0x00010000)
|
||||
#define AMP_CA_SPACING (0x00020000)
|
||||
|
||||
#define CHIPID_BASE_ADDR (PMGR_BASE_ADDR + 0x2A000)
|
||||
|
||||
#define GPIO_VERSION (4)
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define GPIO_GROUP_COUNT (26)
|
||||
#elif SUB_PLATFORM_T7001
|
||||
#define GPIO_GROUP_COUNT (23)
|
||||
#endif
|
||||
#define GPIO_PAD_SPI (GPIO_GROUP_COUNT)
|
||||
|
||||
#define AIC_VERSION (1)
|
||||
#define AIC_INT_COUNT (256)
|
||||
|
||||
#define PMGR_WDG_VERSION (1)
|
||||
|
||||
#define USBOTG_BASE_ADDR (AUSB_OTG_BASE_ADDR)
|
||||
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define APCIE_NUM_LINKS (2)
|
||||
#elif SUB_PLATFORM_T7001
|
||||
#define APCIE_NUM_LINKS (4)
|
||||
#endif
|
||||
|
||||
#define DART0_BASE_ADDR (PCI_REG_BASE + 0x1002000)
|
||||
#define DART0_ADDR_MASK (0x3FFFFFFF)
|
||||
#define DART1_BASE_ADDR (PCI_REG_BASE + 0x2002000)
|
||||
#define DART1_ADDR_MASK (0x3FFFFFFF)
|
||||
#if SUB_PLATFORM_T7001
|
||||
#define DART2_BASE_ADDR (PCI_REG_BASE + 0x3002000)
|
||||
#define DART2_ADDR_MASK (0x3FFFFFFF)
|
||||
#define DART3_BASE_ADDR (PCI_REG_BASE + 0x4002000)
|
||||
#define DART3_ADDR_MASK (0x3FFFFFFF)
|
||||
#endif
|
||||
|
||||
#define PCIE_PORT0_DART_ID (0)
|
||||
#define PCIE_PORT1_DART_ID (1)
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define NUM_DARTS (2)
|
||||
#elif SUB_PLATFORM_T7001
|
||||
#define PCIE_PORT2_DART_ID (2)
|
||||
#define PCIE_PORT3_DART_ID (3)
|
||||
#define NUM_DARTS (4)
|
||||
#endif
|
||||
|
||||
#define AES_AP_BASE_ADDR (ASIO_AES_BASE_ADDR)
|
||||
#define AES_AP_VERSION (0)
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_HWREGBASE_H */
|
||||
@@ -0,0 +1,145 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_SOC_MIU_H
|
||||
#define __PLATFORM_SOC_MIU_H
|
||||
|
||||
#include <lib/devicetree.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rSECUREROMCTRL_ROMADDRREMAP (*(volatile u_int32_t *)(AMCC_BASE_ADDR + 0x0904))
|
||||
|
||||
|
||||
#define rMCCLOCKREGION_TZ0BASEADDR (*(volatile u_int32_t *)(AMCC_BASE_ADDR + 0x480))
|
||||
#define rMCCLOCKREGION_TZ0ENDADDR (*(volatile u_int32_t *)(AMCC_BASE_ADDR + 0x484))
|
||||
#define rMCCLOCKREGION_TZ1BASEADDR (*(volatile u_int32_t *)(AMCC_BASE_ADDR + 0x488))
|
||||
#define rMCCLOCKREGION_TZ1ENDADDR (*(volatile u_int32_t *)(AMCC_BASE_ADDR + 0x48c))
|
||||
#define rMCCLOCKREGION_TZ0LOCK (*(volatile u_int32_t *)(AMCC_BASE_ADDR + 0x490))
|
||||
#define rMCCLOCKREGION_TZ1LOCK (*(volatile u_int32_t *)(AMCC_BASE_ADDR + 0x494))
|
||||
|
||||
|
||||
#define ASIO_CLK_CTRL (0x100004)
|
||||
#define rASIO_CLK_CTRL (*(volatile u_int32_t *)(SB_BASE_ADDR + ASIO_CLK_CTRL))
|
||||
#define ASIO_AKF_IDLE_CTRL (0xe00024)
|
||||
#define rASIO_AKF_IDLE_CTRL (*(volatile u_int32_t *)(SB_BASE_ADDR + ASIO_AKF_IDLE_CTRL))
|
||||
#define DYN_CLK_GATING (0x49a0000)
|
||||
#define rDYN_CLK_GATING (*(volatile u_int32_t *)(SB_BASE_ADDR + DYN_CLK_GATING))
|
||||
#define SIO_ASYNC_FIFO_SB_RD_RATE_LIMIT (0x49c0000)
|
||||
#define rSIO_ASYNC_FIFO_SB_RD_RATE_LIMIT (*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_ASYNC_FIFO_SB_RD_RATE_LIMIT))
|
||||
#define SIO_ASYNC_FIFO_SB_WR_RATE_LIMIT (0x49c0004)
|
||||
#define rSIO_ASYNC_FIFO_SB_WR_RATE_LIMIT (*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_ASYNC_FIFO_SB_WR_RATE_LIMIT))
|
||||
#define SIO_ASYNC_FIFO_SB_WGATHER (0x49c0010)
|
||||
#define rSIO_ASYNC_FIFO_SB_WGATHER (*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_ASYNC_FIFO_SB_WGATHER))
|
||||
#define SIO_DAPASYNC_FIFO_SB_RD_RATE_LIMIT (0x49e0000)
|
||||
#define rSIO_DAPASYNC_FIFO_SB_RD_RATE_LIMIT (*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_DAPASYNC_FIFO_SB_RD_RATE_LIMIT))
|
||||
#define SIO_DAPASYNC_FIFO_SB_WR_RATE_LIMIT (0x49e0004)
|
||||
#define rSIO_DAPASYNC_FIFO_SB_WR_RATE_LIMIT (*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_DAPASYNC_FIFO_SB_WR_RATE_LIMIT))
|
||||
#define SIO_DAPASYNC_FIFO_SB_WGATHER (0x49e0010)
|
||||
#define rSIO_DAPASYNC_FIFO_SB_WGATHER (*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_DAPASYNC_FIFO_SB_WGATHER))
|
||||
#define AIU_SB_ARBCFG (0x5010000)
|
||||
#define rAIU_SB_ARBCFG (*(volatile u_int32_t *)(SB_BASE_ADDR + AIU_SB_ARBCFG))
|
||||
#define AIU_SB_CPG_CNTL (0x5010014)
|
||||
#define rAIU_SB_CPG_CNTL (*(volatile u_int32_t *)(SB_BASE_ADDR + AIU_SB_CPG_CNTL))
|
||||
|
||||
|
||||
#define SOCBUSMUX_ARBCFG (0x0000)
|
||||
#define rSOCBUSMUX_ARBCFG (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + SOCBUSMUX_ARBCFG))
|
||||
#if SUB_PLATFORM_T7001
|
||||
#define DWRRCFG_DISP0_RT (0x0004)
|
||||
#define rDWRRCFG_DISP0_RT (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + DWRRCFG_DISP0_RT))
|
||||
#endif
|
||||
#define DWRRCFG_DISPMUX_BULK (0x0008)
|
||||
#define rDWRRCFG_DISPMUX_BULK (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + DWRRCFG_DISPMUX_BULK))
|
||||
#if SUB_PLATFORM_T7001
|
||||
#define DWRRCFG_IOMUX_BULK (0x001c)
|
||||
#define rDWRRCFG_IOMUX_BULK (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + DWRRCFG_IOMUX_BULK))
|
||||
#endif
|
||||
#define TLIMIT_LVL0_DISP0 (0x0024)
|
||||
#define rTLIMIT_LVL0_DISP0 (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL0_DISP0))
|
||||
#define TLIMIT_LVL1_DISP0 (0x0028)
|
||||
#define rTLIMIT_LVL1_DISP0 (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL1_DISP0))
|
||||
#define TLIMIT_LVL2_DISP0 (0x002c)
|
||||
#define rTLIMIT_LVL2_DISP0 (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL2_DISP0))
|
||||
#define TLIMIT_LVL3_DISP0 (0x0030)
|
||||
#define rTLIMIT_LVL3_DISP0 (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL3_DISP0))
|
||||
#define TLIMIT_LVL0_CAMERAMUX (0x0034)
|
||||
#define rTLIMIT_LVL0_CAMERAMUX (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL0_CAMERAMUX))
|
||||
#define TLIMIT_LVL1_CAMERAMUX (0x0038)
|
||||
#define rTLIMIT_LVL1_CAMERAMUX (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL1_CAMERAMUX))
|
||||
#define TLIMIT_LVL1_MEDIAMUX (0x0048)
|
||||
#define rTLIMIT_LVL1_MEDIAMUX (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL1_MEDIAMUX))
|
||||
#define TLIMIT_LVL2_MEDIAMUX (0x004c)
|
||||
#define rTLIMIT_LVL2_MEDIAMUX (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL2_MEDIAMUX))
|
||||
#define TLIMIT_LVL0_IOMUX (0x0054)
|
||||
#define rTLIMIT_LVL0_IOMUX (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL0_IOMUX))
|
||||
#define TLIMIT_LVL1_IOMUX (0x0058)
|
||||
#define rTLIMIT_LVL1_IOMUX (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL1_IOMUX))
|
||||
#define TLIMIT_LVL2_IOMUX (0x005c)
|
||||
#define rTLIMIT_LVL2_IOMUX (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL2_IOMUX))
|
||||
#define TLIMIT_LVL3_IOMUX (0x0060)
|
||||
#define rTLIMIT_LVL3_IOMUX (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL3_IOMUX))
|
||||
#define SOCBUSMUX_CPG_CNTL (0x0088)
|
||||
#define rSOCBUSMUX_CPG_CNTL (*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + SOCBUSMUX_CPG_CNTL))
|
||||
|
||||
|
||||
#define IOBUSMUX_ARBCFG (0x0000)
|
||||
#define rIOBUSMUX_ARBCFG (*(volatile u_int32_t *)(IOBUSMUX_BASE_ADDR + IOBUSMUX_ARBCFG))
|
||||
#if SUB_PLATFORM_T7001
|
||||
#define IOBUSMUX_REGS_DWRRCFG_DISP1_BULK (0x0010)
|
||||
#define rIOBUSMUX_REGS_DWRRCFG_DISP1_BULK (*(volatile u_int32_t *)(IOBUSMUX_BASE_ADDR + IOBUSMUX_REGS_DWRRCFG_DISP1_BULK))
|
||||
#endif
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define IOBUSMUX_CPG_CNTL (0x0024)
|
||||
#elif SUB_PLATFORM_T7001
|
||||
#define IOBUSMUX_CPG_CNTL (0x002c)
|
||||
#endif
|
||||
#define rIOBUSMUX_CPG_CNTL (*(volatile u_int32_t *)(IOBUSMUX_BASE_ADDR + IOBUSMUX_CPG_CNTL))
|
||||
|
||||
|
||||
#define SWITCH_FAB_AMAP_LOCK (0x0000)
|
||||
#define rSWITCH_FAB_AMAP_LOCK (*(volatile u_int32_t *)(SWTCH_FAB_BASE_ADDR + SWITCH_FAB_AMAP_LOCK))
|
||||
#define SWITCH_FAB_ARBCFG (0x0008)
|
||||
#define rSWITCH_FAB_ARBCFG (*(volatile u_int32_t *)(SWTCH_FAB_BASE_ADDR + SWITCH_FAB_ARBCFG))
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define SWITCH_FAB_PIOLIMIT (0x0028)
|
||||
#elif SUB_PLATFORM_T7001
|
||||
#define SWITCH_FAB_PIOLIMIT (0x002c)
|
||||
#endif
|
||||
#define rSWITCH_FAB_PIOLIMIT (*(volatile u_int32_t *)(SWTCH_FAB_BASE_ADDR + SWITCH_FAB_PIOLIMIT))
|
||||
#if SUB_PLATFORM_T7000
|
||||
#define SWITCH_FAB_CPG_CNTL (0x0070)
|
||||
#elif SUB_PLATFORM_T7001
|
||||
#define SWITCH_FAB_CPG_CNTL (0x008c)
|
||||
#endif
|
||||
#define rSWITCH_FAB_CPG_CNTL (*(volatile u_int32_t *)(SWTCH_FAB_BASE_ADDR + SWITCH_FAB_CPG_CNTL))
|
||||
|
||||
|
||||
#define CP_DYN_CLK_GATING_CTRL (0x000c)
|
||||
#define rCP_DYN_CLK_GATING_CTRL (*(volatile u_int32_t *)(CP_COM_BASE_ADDR + CP_DYN_CLK_GATING_CTRL))
|
||||
|
||||
#define CPCOM_INT_NORM_REQUEST (0x0000)
|
||||
#define rCP_COM_INT_NORM_REQUEST (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CPCOM_INT_NORM_REQUEST))
|
||||
#define CPCOM_INT_NORM_MASK_SET (0x0004)
|
||||
#define rCP_COM_INT_NORM_MASK_SET (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CPCOM_INT_NORM_MASK_SET))
|
||||
#define CPCOM_INT_NORM_MASK_CLR (0x0008)
|
||||
#define rCP_COM_INT_NORM_MASK_CLR (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CPCOM_INT_NORM_MASK_CLR))
|
||||
|
||||
#define LIO_MEMCACHE_DATASETID_OVERRIDE (0x001000)
|
||||
|
||||
enum remap_select {
|
||||
REMAP_SRAM = 0,
|
||||
REMAP_SDRAM
|
||||
};
|
||||
|
||||
extern void miu_select_remap(enum remap_select sel);
|
||||
extern void miu_bypass_prep(void);
|
||||
extern void miu_update_device_tree(DTNode *pmgr_node);
|
||||
|
||||
#endif /* ! __PLATFORM_SOC_MIU_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_TRAMPOLINE_H
|
||||
#define __PLATFORM_TRAMPOLINE_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
/* ROM related registers in AMC space */
|
||||
|
||||
#define SECURITY_REG (AMCC_BASE_ADDR + 0x900)
|
||||
#define ROM_READ_DISABLE (1 << 0)
|
||||
|
||||
#define REMAP_REG (AMCC_BASE_ADDR + 0x904)
|
||||
|
||||
#endif /* ! __PLATFORM_TRAMPOLINE_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __PLATFORM_USBCONFIG_H
|
||||
#define __PLATFORM_USBCONFIG_H
|
||||
|
||||
/*
|
||||
* per Fiji Tunables Specification, Revision 1.18, August 13, 2013
|
||||
*/
|
||||
#define USBPHY_OTGTUNE0 (0x37477BF3)
|
||||
|
||||
#define USBOTG_AHB_DMA_BURST (DWCUSB_GAHBCFG_HBST_INCR16)
|
||||
|
||||
#endif /* ! __PLATFORM_USBCONFIG_H */
|
||||
Reference in new issue
Block a user